System on Chip Design Space Exploration: Design Trotter Framework
System on Chip Design Space Exploration: Design Trotter Framework
System on Chip Design Space Exploration: Design Trotter Framework
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Introducti<strong>on</strong> : Directi<strong>on</strong>s ☯<br />
☯ (Re)c<strong>on</strong>figurable Architectures<br />
Improve the Appli/Archi matching: GOPS/Watt & Gops/µm 2 metrics<br />
(Re)c<strong>on</strong>figurable architectures:<br />
Altera & Xilinx Platform : mixed grain (LUT, DSP blocks) design-time<br />
c<strong>on</strong>figurable plateform (Processor + Memories + DSP blocks + LUT)<br />
ARC (ARCtangent), Tensilica (Xtensa), HP/ST (Lx) : <strong>Design</strong>-time c<strong>on</strong>figurable<br />
processors => specific instructi<strong>on</strong>s => Performances X 10 to 100<br />
Academic "Run time" c<strong>on</strong>figurable architectures<br />
fine grain (LUT), coarse grain (Data Path, ALU, MAC)<br />
Industry "run-time" c<strong>on</strong>figurable processor : Stretch Inc, PACT,<br />
3G base-stati<strong>on</strong> rec<strong>on</strong>figurable DSP : MorphICs, Pico<strong>Chip</strong>, Morpho<br />
Tech.<br />
Means (Re) Targetable design flows: HW / SW Ad Hoc Compilers<br />
CAD tools for HW/SW explorati<strong>on</strong> & architecture selecti<strong>on</strong> before<br />
c<strong>on</strong>figurati<strong>on</strong> => <strong>Design</strong> <strong>Trotter</strong> CAD framework Objectives<br />
SÉMINAIRE SCEE SUPELEC, 21/10/2004 4
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