TCAD Technology CAD Process Simulation Dr. Lynn Fuller - People ...
TCAD Technology CAD Process Simulation Dr. Lynn Fuller - People ...
TCAD Technology CAD Process Simulation Dr. Lynn Fuller - People ...
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<strong>T<strong>CAD</strong></strong><br />
ROCHESTER INSTITUTE OF TECHNOLOGY<br />
MICROELECTRONIC ENGINEERING<br />
<strong>T<strong>CAD</strong></strong> <strong>Technology</strong> <strong>CAD</strong><br />
<strong>Process</strong> <strong>Simulation</strong><br />
<strong>Dr</strong>. <strong>Lynn</strong> <strong>Fuller</strong><br />
Webpage: http://people.rit.edu/lffeee<br />
Microelectronic Engineering<br />
Rochester Institute of <strong>Technology</strong><br />
82 Lomb Memorial <strong>Dr</strong>ive<br />
Rochester, NY 14623-5604<br />
Tel (585) 475-2035<br />
Fax (585) 475-5041<br />
Email: <strong>Lynn</strong>.<strong>Fuller</strong>@rit.edu<br />
Department webpage: http://www.microe.rit.edu<br />
Rochester Institute of <strong>Technology</strong><br />
Microelectronic Engineering<br />
3-10-2008 lec_tcad.ppt<br />
© March 10, 2008, <strong>Dr</strong>. <strong>Lynn</strong> <strong>Fuller</strong>, Professor<br />
Page 1
<strong>T<strong>CAD</strong></strong><br />
OUTLINE<br />
Introduction<br />
Why Simulate<br />
<strong>Process</strong> <strong>Simulation</strong><br />
Device <strong>Simulation</strong><br />
Circuit <strong>Simulation</strong><br />
Historical Perspective of Simulators<br />
Evolution of the Complexity of <strong>Process</strong> Simulators<br />
Oxidation <strong>Simulation</strong><br />
Implant <strong>Simulation</strong><br />
Diffusion <strong>Simulation</strong><br />
2-d and 3-d <strong>Simulation</strong><br />
Summary<br />
References<br />
Homework<br />
Rochester Institute of <strong>Technology</strong><br />
Microelectronic Engineering<br />
© March 10, 2008, <strong>Dr</strong>. <strong>Lynn</strong> <strong>Fuller</strong>, Professor<br />
Page 2
<strong>T<strong>CAD</strong></strong><br />
HIERARCHY OF SIMULATION TOOLS FOR IC<br />
DEVELOPMENT<br />
Rochester Institute of <strong>Technology</strong><br />
Microelectronic Engineering<br />
© March 10, 2008, <strong>Dr</strong>. <strong>Lynn</strong> <strong>Fuller</strong>, Professor<br />
Page 3
<strong>T<strong>CAD</strong></strong><br />
WHY SIMULATION<br />
Emperical Models (Analytic fits to emperical data) can not be<br />
extended beyond the limits for which data is available.<br />
Physical Models (models based on the physical and chemical<br />
fundamentals) can be extended into new regions<br />
<strong>Process</strong> <strong>Simulation</strong> – carrying out processing experiments with the<br />
aid of a computer, much less expensive.<br />
<strong>Process</strong> Sensitivity Studies – How much of a variation in oxide<br />
thickness can the device withstand and still meet specifications.<br />
These types of studies can be done much less expensively by<br />
simulation.<br />
Rochester Institute of <strong>Technology</strong><br />
Microelectronic Engineering<br />
© March 10, 2008, <strong>Dr</strong>. <strong>Lynn</strong> <strong>Fuller</strong>, Professor<br />
Page 4
<strong>T<strong>CAD</strong></strong><br />
PROCESS APPLICATIONS OF SIMULATION<br />
<strong>Process</strong> Information Obtained by <strong>Simulation</strong><br />
Doping profiles in silicon substrate<br />
Doping profiles in SiO2, Polysilicon and Silicide layers<br />
Junction depths<br />
Thickness of Material Layers<br />
Topography<br />
Lithography: resist profiles after develop<br />
Device cross-sections from layout<br />
Rochester Institute of <strong>Technology</strong><br />
Microelectronic Engineering<br />
© March 10, 2008, <strong>Dr</strong>. <strong>Lynn</strong> <strong>Fuller</strong>, Professor<br />
Page 5
<strong>T<strong>CAD</strong></strong><br />
PROCESS SIMULATION<br />
Rochester Institute of <strong>Technology</strong><br />
Microelectronic Engineering<br />
© March 10, 2008, <strong>Dr</strong>. <strong>Lynn</strong> <strong>Fuller</strong>, Professor<br />
Page 6
<strong>T<strong>CAD</strong></strong><br />
EXAMPLE DOPING PROFILES<br />
2-D Doping Profile<br />
Rochester Institute of <strong>Technology</strong><br />
Microelectronic Engineering<br />
1-D Doping Profile<br />
© March 10, 2008, <strong>Dr</strong>. <strong>Lynn</strong> <strong>Fuller</strong>, Professor<br />
Page 7
<strong>T<strong>CAD</strong></strong><br />
EXAMPLE DOPING PROFILES<br />
Arsenic<br />
Boron<br />
Rochester Institute of <strong>Technology</strong><br />
Microelectronic Engineering<br />
Surface Plot of Arsenic and Boron<br />
Concentrations in a 1 µm NMOSFET<br />
© March 10, 2008, <strong>Dr</strong>. <strong>Lynn</strong> <strong>Fuller</strong>, Professor<br />
Page 8
<strong>T<strong>CAD</strong></strong><br />
EXAMPLE DOPING PROFILES<br />
Before<br />
Oxidation<br />
After<br />
Oxidation<br />
Lateral Diffusion<br />
Of Impurities<br />
During Field<br />
Oxide Growth<br />
Rochester Institute of <strong>Technology</strong><br />
Microelectronic Engineering<br />
© March 10, 2008, <strong>Dr</strong>. <strong>Lynn</strong> <strong>Fuller</strong>, Professor<br />
Page 9
<strong>T<strong>CAD</strong></strong><br />
DEPICT LITHOGRAPHY AND ETCH SIMULATOR<br />
DEPICT<br />
Resist Develop<br />
Poly Etch<br />
Rochester Institute of <strong>Technology</strong><br />
Microelectronic Engineering<br />
Oxide Etch<br />
© March 10, 2008, <strong>Dr</strong>. <strong>Lynn</strong> <strong>Fuller</strong>, Professor<br />
Page 10
<strong>T<strong>CAD</strong></strong><br />
DEVICE APPLICATIONS OF SIMULATION<br />
Device Characteristics Obtained by <strong>Simulation</strong><br />
Potential and Electric Field Strength<br />
Carrier Concentrations<br />
Space Charge Regions<br />
Current Flow Paths<br />
Film Sheet Resistance<br />
Threshold Voltage<br />
Subthreshlod Currents<br />
Device Isolation Characteristics<br />
Latch-up Effects in CMOS<br />
Punchthrough<br />
Hot-carrier effects<br />
Rochester Institute of <strong>Technology</strong><br />
Microelectronic Engineering<br />
© March 10, 2008, <strong>Dr</strong>. <strong>Lynn</strong> <strong>Fuller</strong>, Professor<br />
Page 11
<strong>T<strong>CAD</strong></strong><br />
EXAMPLE OF BJT SIMULATION<br />
Base<br />
Current<br />
Collector<br />
Current<br />
Rochester Institute of <strong>Technology</strong><br />
Microelectronic Engineering<br />
© March 10, 2008, <strong>Dr</strong>. <strong>Lynn</strong> <strong>Fuller</strong>, Professor<br />
Page 12
<strong>T<strong>CAD</strong></strong><br />
EXAMPLE SIMULATION OF VT<br />
Rochester Institute of <strong>Technology</strong><br />
Microelectronic Engineering<br />
© March 10, 2008, <strong>Dr</strong>. <strong>Lynn</strong> <strong>Fuller</strong>, Professor<br />
Page 13
<strong>T<strong>CAD</strong></strong><br />
EXAMPLE OF SIMULATION OF SPACE CHARGE REGION<br />
Rochester Institute of <strong>Technology</strong><br />
Microelectronic Engineering<br />
© March 10, 2008, <strong>Dr</strong>. <strong>Lynn</strong> <strong>Fuller</strong>, Professor<br />
Page 14
<strong>T<strong>CAD</strong></strong><br />
EXAMPLE DEVICE POTENTIAL AND ELECTRIC FIELD<br />
Rochester Institute of <strong>Technology</strong><br />
Microelectronic Engineering<br />
© March 10, 2008, <strong>Dr</strong>. <strong>Lynn</strong> <strong>Fuller</strong>, Professor<br />
Page 15
<strong>T<strong>CAD</strong></strong><br />
EXAMPLE OF SUB VT SLOPE SIMULATION<br />
Rochester Institute of <strong>Technology</strong><br />
Microelectronic Engineering<br />
© March 10, 2008, <strong>Dr</strong>. <strong>Lynn</strong> <strong>Fuller</strong>, Professor<br />
Page 16
<strong>T<strong>CAD</strong></strong><br />
CIRCUIT APPLICATIONS OF SIMULATION<br />
Circuit Characteristics Obtained by <strong>Simulation</strong><br />
Device Parameters for Circuit Models<br />
Propagation Delay and Rise/Fall Times<br />
Voltages and Currents<br />
Power Consumption<br />
Parasitic Resistance and Capacitance of Interconnect<br />
Rochester Institute of <strong>Technology</strong><br />
Microelectronic Engineering<br />
© March 10, 2008, <strong>Dr</strong>. <strong>Lynn</strong> <strong>Fuller</strong>, Professor<br />
Page 17
<strong>T<strong>CAD</strong></strong><br />
EXAMPLE OF CIRCUIT SIMULATION<br />
Exclusive OR Circuit drawn by Jane Doe 10-3-97<br />
Input A<br />
Port<br />
in<br />
Input B<br />
Port<br />
in<br />
Vcc<br />
A’<br />
B<br />
A<br />
B’<br />
A’B<br />
AB’<br />
XOR<br />
Port<br />
out<br />
XOR = A’B+AB’<br />
Mentor Graphics<br />
QuickSim (Digital<br />
Circuit <strong>Simulation</strong>)<br />
Verification<br />
of the XOR<br />
circuit<br />
/A input<br />
/B input<br />
/XOR<br />
output<br />
Rochester Institute of <strong>Technology</strong><br />
Microelectronic Engineering<br />
0 1 0 1 0 1 0 1 0<br />
0<br />
1<br />
0<br />
1 0<br />
0 1 0<br />
1<br />
0<br />
0 100ns 200ns 300ns 400ns<br />
repeats<br />
time<br />
nano<br />
seconds<br />
© March 10, 2008, <strong>Dr</strong>. <strong>Lynn</strong> <strong>Fuller</strong>, Professor<br />
Page 18
<strong>T<strong>CAD</strong></strong><br />
EXAMPLE OF CIRCUIT SIMULATION<br />
Rochester Institute of <strong>Technology</strong><br />
Microelectronic Engineering<br />
© March 10, 2008, <strong>Dr</strong>. <strong>Lynn</strong> <strong>Fuller</strong>, Professor<br />
Page 19
<strong>T<strong>CAD</strong></strong><br />
PROCESS SIMULATORS<br />
Rochester Institute of <strong>Technology</strong><br />
Microelectronic Engineering<br />
© March 10, 2008, <strong>Dr</strong>. <strong>Lynn</strong> <strong>Fuller</strong>, Professor<br />
Page 20
<strong>T<strong>CAD</strong></strong><br />
PROCESS SIMULATORS<br />
Rochester Institute of <strong>Technology</strong><br />
Microelectronic Engineering<br />
© March 10, 2008, <strong>Dr</strong>. <strong>Lynn</strong> <strong>Fuller</strong>, Professor<br />
Page 21
<strong>T<strong>CAD</strong></strong><br />
AVALIABILITY OF PROCESS, DEVICE AND CIRCUIT<br />
SIMULATORS<br />
Rochester Institute of <strong>Technology</strong><br />
Microelectronic Engineering<br />
© March 10, 2008, <strong>Dr</strong>. <strong>Lynn</strong> <strong>Fuller</strong>, Professor<br />
Page 22
<strong>T<strong>CAD</strong></strong><br />
HISTORICAL VIEW OF PROCESS SIMULATION<br />
1-D Doping Profile and Oxidation Simulators<br />
SUPREM I – Stanford University, 1977<br />
SUPREM II – Stanford University, 1979<br />
SUPREM III – Stanford University, 1983<br />
2-D Doping Profile and 2-D Oxidation Simulators<br />
SUPRA – Stanford University, 1982<br />
SUPREM IV – Stanford University, 1986<br />
2-D Topographical Simulators<br />
SAMPLE – Berkeley, 1982<br />
Prolith – Dept. of Defense, 1986, now offered<br />
by Finle Technologies Inc.<br />
DEPICT-2 <strong>Technology</strong> Modeling Associates, 1985<br />
SIML – 1, SIMPL-2, SIMPL/DIX U.C. Berkeley, 1983<br />
In the past it was said that Stanford did from the surface down<br />
into the silicon and Berkeley did from the surface up (topography)<br />
Rochester Institute of <strong>Technology</strong><br />
Microelectronic Engineering<br />
© March 10, 2008, <strong>Dr</strong>. <strong>Lynn</strong> <strong>Fuller</strong>, Professor<br />
Page 23
<strong>T<strong>CAD</strong></strong><br />
1-D SUPREM-3 SIMULATION<br />
Poly<br />
Oxide<br />
P-type well<br />
N-type Silicon<br />
starting wafer<br />
Layer 3<br />
Layer 2<br />
Layer 1 Region 2<br />
Layer 1 Region 1<br />
SUPREM-3 does a one dimensional<br />
analysis of doping concentration, for a<br />
variety of oxide, diffusion, implant,<br />
deposition and etch processes.<br />
X<br />
Rochester Institute of <strong>Technology</strong><br />
Microelectronic Engineering<br />
N(x)<br />
Boron<br />
Phosphorous<br />
0 1 2 3 4µm<br />
x<br />
© March 10, 2008, <strong>Dr</strong>. <strong>Lynn</strong> <strong>Fuller</strong>, Professor<br />
Page 24
<strong>T<strong>CAD</strong></strong><br />
SUPREM-3 INPUT FILE DETAILS<br />
1… TITLE SIMULATION FOR NMOS TRANSISTOR IN THE PWELL<br />
3… Com Date: 5/3/99<br />
4… Com edited by L.<strong>Fuller</strong> for EMCR 732<br />
5… Com Location pwellcmos1.in 635dept emcr650.suprem<br />
6… Com<br />
7… Initialize silicon (100) P=7E14 thickness=8 dx=0.02<br />
8… Com<br />
9… Com Ramp Rate is taken as 16 C/min up and –8 C/min down<br />
10… Com All furnace steps push at 12 in/min at 900 C then<br />
11… Com Ramp up to soak temp ant then soak for the given time followed<br />
12… Com by ramp down to 1000 C and pull at 12 in/min<br />
13… Com Step1 ID01 Scribe Wafers<br />
14… Com Step2 DE01 Four Point Probe<br />
15… Com Step3 CL01 RCA Cleaned<br />
16… Com Step4 Alignment Oxide Growth<br />
18… Diffusion Time=12.5 Temp=900 WetO2 T.Rate=12<br />
19… Diffusion Time=35 Temp=1100 WetO2<br />
20… Diffusion Time=12.5 Temp=1100 WetO2 T.Rate=-8<br />
Rochester Institute of <strong>Technology</strong><br />
Microelectronic Engineering<br />
© March 10, 2008, <strong>Dr</strong>. <strong>Lynn</strong> <strong>Fuller</strong>, Professor<br />
Page 25
<strong>T<strong>CAD</strong></strong><br />
WELL MASKING OXIDE<br />
22… Print layers concentrations active phosphorous s.max=0 electric<br />
23… Com<br />
24… plot active phosphorous layer=2 title= “WELL MASKING OXIDE”<br />
…… + bottom=1e13 top=1e16 left=0 right=2.0 timestamp<br />
25… Com<br />
26… Extract Name=xox1 thickness layer=2<br />
27… label label=“ Oxide thickness: “@xox1” microns”<br />
28… label label=“ Masking Oxide Time = 35 min.”<br />
29… label label=“ Masking Oxide Temp = 1100 C”<br />
30… label label = “TMA LFF” CM X=17.0 Y=2.1<br />
31… Com<br />
Xox = 0.5748 µm<br />
= 5748 Å<br />
Rochester Institute of <strong>Technology</strong><br />
Microelectronic Engineering<br />
© March 10, 2008, <strong>Dr</strong>. <strong>Lynn</strong> <strong>Fuller</strong>, Professor<br />
Page 26
<strong>T<strong>CAD</strong></strong><br />
WELL IMPLANT AND DRIVE<br />
32… Com Step5 Ph03 Photo level 1 Well Region<br />
33… Com Step6 ET06 Oxide Etch<br />
34… Etch Oxide<br />
35… Com Step7 IM01 Implant Well<br />
36… Assign name=dwell n.value=4E12<br />
37… Assign name=ewell N.value=50<br />
38… Implant Boron Dose = dwell Energy = ewell<br />
39… Com Step 8 ET07 Strip photoresist<br />
40… Com Step9 Cl01 RCA Clean<br />
41… Com Step10 OX06 Well <strong>Dr</strong>ive<br />
41… Diffusion Temperature = 900 t.Final = 1125 <strong>Dr</strong>yo2 Time=14<br />
42… Diffusion Time=240 Temperature= 1125 <strong>Dr</strong>yo2<br />
43… Diffusion Time=960 Temperature=1125 Nitrogen<br />
45… Diffusion Temperature=1125 T.Final=1000 Nitrogen Time=15.6<br />
46… print layers concentrations_active_phosphorous boron combine layer=1<br />
+ x.max=0 electric<br />
48… Extract Name=xox3 thickness layer=2<br />
49… Extract Name=xjw net active x.extract y=0<br />
50… Electrical steps = 1<br />
51… Bias layer=1 V=0<br />
52… End<br />
53… Extract Rochester Institute Name=Rsw of <strong>Technology</strong>h.resistance layer=1 min.region=2<br />
Microelectronic Engineering<br />
55… Plot net active title=“IMPURITY PROFILE AFTER WELL DRIVE”<br />
… +<br />
© March 10, 2008, <strong>Dr</strong>. <strong>Lynn</strong> <strong>Fuller</strong>, Professor<br />
Page 27
<strong>T<strong>CAD</strong></strong><br />
AFTER WELL DRIVE<br />
Rochester Institute of <strong>Technology</strong><br />
Microelectronic Engineering<br />
© March 10, 2008, <strong>Dr</strong>. <strong>Lynn</strong> <strong>Fuller</strong>, Professor<br />
Page 28
<strong>T<strong>CAD</strong></strong><br />
PAD OXIDE GROWTH<br />
65… ETCH OXIDE<br />
66… Com Step 12 Gr01 Groove and Stain<br />
67… Com Step13 De01 Four Point Probe<br />
68… Com Step14 Ox05 Pad Oxide<br />
69… Diffusion Time=12.5 Temp=900 <strong>Dr</strong>yO2 T.Rate=16<br />
70… Diffusion Time=50 Temp=1100 <strong>Dr</strong>yO2<br />
71… Diffusion Time=12.5 Temp=1100 Nitrogen T.Rate=-8<br />
…<br />
85… Deposit Nitride Thickness = 0.15 Temperature = 810 Time = 20<br />
Xox = 0.099 µm<br />
= ~1000 Å<br />
Rochester Institute of <strong>Technology</strong><br />
Microelectronic Engineering<br />
© March 10, 2008, <strong>Dr</strong>. <strong>Lynn</strong> <strong>Fuller</strong>, Professor<br />
Page 29
<strong>T<strong>CAD</strong></strong><br />
AFTER FIELD OXIDE GROWTH<br />
97… Com Step24 Ox05 Field Oxide<br />
98… Diffusion Time=12.5 Temp=900 WetO2 T.Rate=16<br />
99… Diffusion Time=210 Temp=1100 WetO2<br />
100… Diffusion Time=12.5 Temp=1100 Nitrogen T.Rate=-8<br />
…<br />
115… Etch Oxide<br />
116… Etch Nitride<br />
117… Etch Oxide<br />
Xox = ~ 1000 Å<br />
Because nitride<br />
protects area over<br />
the well<br />
Rochester Institute of <strong>Technology</strong><br />
Microelectronic Engineering<br />
© March 10, 2008, <strong>Dr</strong>. <strong>Lynn</strong> <strong>Fuller</strong>, Professor<br />
Page 30
<strong>T<strong>CAD</strong></strong><br />
KOOI OXIDE GROWTH<br />
120… Com Step29 Ox04 Kooi Oxide Growth<br />
121… Diffusion Time=45 Temp=900 WetO2<br />
Rochester Institute of <strong>Technology</strong><br />
Microelectronic Engineering<br />
© March 10, 2008, <strong>Dr</strong>. <strong>Lynn</strong> <strong>Fuller</strong>, Professor<br />
Page 31
<strong>T<strong>CAD</strong></strong><br />
NMOS THRESHOLD ADJUST IMPLANT & ANNEAL<br />
135… Com Step30 Im01 PMOS Vt Adjust Ion Implant (blanket Implant)<br />
136… Assign Name=DPVT N.Value=5.3E11<br />
137… Assign Name=EPVT N.Value=60<br />
138… Implant Boron Dose= DPVT Energy=EPVT<br />
139… Com Step31 Ph03 Photo Level 4 NMOS Vt Adjust<br />
140… Com Step32 Im01 NMOS VT Adjust Ion Implant (masked Implant)<br />
141… Assign Name=DNVT N.Value=4E12<br />
142… Assign Name=ENVT N.Value=60<br />
138… Implant Boron Dose= DNVT Energy=ENVT<br />
Rochester Institute of <strong>Technology</strong><br />
Microelectronic Engineering<br />
© March 10, 2008, <strong>Dr</strong>. <strong>Lynn</strong> <strong>Fuller</strong>, Professor<br />
Page 32
<strong>T<strong>CAD</strong></strong><br />
AFTER GATE OXIDE GROWTH<br />
155… Etch Oxide<br />
156… Com Step35 Cl01 RCA Clean<br />
156… Com Step36 Ox06 Gate Oxide Growth<br />
98… Diffusion Time=12.5 Temp=900 Nitrogen T.Rate=16<br />
99… Diffusion Time=30 Temp=1100 <strong>Dr</strong>yO2<br />
100… Diffusion Time=12.5 Temp=1100 Nitrogen T.Rate=-8<br />
…<br />
Rochester Institute of <strong>Technology</strong><br />
Microelectronic Engineering<br />
© March 10, 2008, <strong>Dr</strong>. <strong>Lynn</strong> <strong>Fuller</strong>, Professor<br />
Page 33
<strong>T<strong>CAD</strong></strong><br />
AFTER POLY DOPING AND LPCVD GLASS<br />
175… Com Step39 Cv01 LPCVD Polysilicon<br />
176… Deposit Polysilicon Thickness=o.6 Temperature = 610 Time=60<br />
178… Diffusion Time=10 Temperature=900 SS.Phosphorous<br />
…<br />
186… Com Step52 CVD LPCVD Oxide<br />
187… Com Step53 Anneal Oxide<br />
187… Diffusion Time = 30 Temperature=1000 Nitrogen<br />
Rochester Institute of <strong>Technology</strong><br />
Microelectronic Engineering<br />
© March 10, 2008, <strong>Dr</strong>. <strong>Lynn</strong> <strong>Fuller</strong>, Professor<br />
Page 34
<strong>T<strong>CAD</strong></strong><br />
TRANSISTOR THRESHOLD VOLTAGE<br />
212… Com Electrical Analysis<br />
213… Electrical Steps=101 Vth.elect layer=1 file=Vth.dat min.regi=2 max.regi=2<br />
214… Bias Layer=1 Region=1 V=5<br />
215… Bias Layer=1 Region=2 V=0 V.min=0<br />
216… Bias Layer=3 V=-10 DV=0.2 Abscissa<br />
217… Assign Name=Qss N.value=3.6E11<br />
218… Qss Layer=1 Concentration=Qss<br />
219… End.Electrical<br />
220… Extract name=Vt V.threshold<br />
Rochester Institute of <strong>Technology</strong><br />
Microelectronic Engineering<br />
© March 10, 2008, <strong>Dr</strong>. <strong>Lynn</strong> <strong>Fuller</strong>, Professor<br />
Page 35
<strong>T<strong>CAD</strong></strong><br />
2-D SUPREM-4 P-WELL CMOS<br />
Rochester Institute of <strong>Technology</strong><br />
Microelectronic Engineering<br />
© March 10, 2008, <strong>Dr</strong>. <strong>Lynn</strong> <strong>Fuller</strong>, Professor<br />
Page 37
<strong>T<strong>CAD</strong></strong><br />
2-D SUPREM-4 CHANNEL STOP IMPLANT<br />
Rochester Institute of <strong>Technology</strong><br />
Microelectronic Engineering<br />
© March 10, 2008, <strong>Dr</strong>. <strong>Lynn</strong> <strong>Fuller</strong>, Professor<br />
Page 38
<strong>T<strong>CAD</strong></strong><br />
P-WELL CMOS SIMULATION USING SILVACO ATHENA<br />
Rochester Institute of <strong>Technology</strong><br />
Microelectronic Engineering<br />
© March 10, 2008, <strong>Dr</strong>. <strong>Lynn</strong> <strong>Fuller</strong>, Professor<br />
Page 39
<strong>T<strong>CAD</strong></strong><br />
2-D SUPREM-4 ANALYSIS OF BIRDS BEAK<br />
Rochester Institute of <strong>Technology</strong><br />
Microelectronic Engineering<br />
© March 10, 2008, <strong>Dr</strong>. <strong>Lynn</strong> <strong>Fuller</strong>, Professor<br />
Page 40
<strong>T<strong>CAD</strong></strong><br />
DEFECTS CAUSED BY STRESS IN LOCOS PROCESS<br />
The stress can be large enough to<br />
cause damage in the silicon at the edge<br />
of the LOCOS. The D/S junctions are<br />
also located at the edge of the LOCOS.<br />
The result is that the junctions are<br />
leaky.<br />
Stress increases with increased nitride<br />
thickness, increased field oxide<br />
thickness and decreased pad oxide<br />
thickness. In the RIT Pwell CMOS<br />
process pad oxide is 500 Å, nitride is<br />
1500 Å and field oxide is 11,000 Å.<br />
We may get more reliable results by<br />
decreasing the nitride to 1000 Å and<br />
decreasing the field oxide to 8000 Å<br />
Rochester Institute of <strong>Technology</strong><br />
Microelectronic Engineering<br />
© March 10, 2008, <strong>Dr</strong>. <strong>Lynn</strong> <strong>Fuller</strong>, Professor<br />
Page 41
<strong>T<strong>CAD</strong></strong><br />
HISTORY OF SILICON OXIDE SIMULATION<br />
All oxide simulations are based on the work of Deal and Grove done<br />
in the early 1960’s<br />
Rochester Institute of <strong>Technology</strong><br />
Microelectronic Engineering<br />
© March 10, 2008, <strong>Dr</strong>. <strong>Lynn</strong> <strong>Fuller</strong>, Professor<br />
Page 42
<strong>T<strong>CAD</strong></strong><br />
HISTORY OF SILICON OXIDE SIMULATION<br />
Rochester Institute of <strong>Technology</strong><br />
Microelectronic Engineering<br />
© March 10, 2008, <strong>Dr</strong>. <strong>Lynn</strong> <strong>Fuller</strong>, Professor<br />
Page 43
<strong>T<strong>CAD</strong></strong><br />
HISTORY OF SUPREM SIMULATIONS<br />
Rochester Institute of <strong>Technology</strong><br />
Microelectronic Engineering<br />
© March 10, 2008, <strong>Dr</strong>. <strong>Lynn</strong> <strong>Fuller</strong>, Professor<br />
Page 44
<strong>T<strong>CAD</strong></strong><br />
SYSTEM OF EQUATIONS TO BE SOLVED<br />
Rochester Institute of <strong>Technology</strong><br />
Microelectronic Engineering<br />
© March 10, 2008, <strong>Dr</strong>. <strong>Lynn</strong> <strong>Fuller</strong>, Professor<br />
Page 45
<strong>T<strong>CAD</strong></strong><br />
SUMMARY<br />
SUPREM analysis allows for the calculation of resultant impurity<br />
concentrations for processes such as oxidation, diffusion,<br />
implantation and deposition for temperatures above 800 C.<br />
Rochester Institute of <strong>Technology</strong><br />
Microelectronic Engineering<br />
© March 10, 2008, <strong>Dr</strong>. <strong>Lynn</strong> <strong>Fuller</strong>, Professor<br />
Page 46
<strong>T<strong>CAD</strong></strong><br />
REFERENCES<br />
1. Silicon <strong>Process</strong>ing for the VLSI Era, Vol.2., Stanly Wolf, 1990.<br />
2. The Science and Engineering of Microelectronic <strong>Process</strong>ing,<br />
Stephen Campbell.<br />
3. <strong>Technology</strong> Modeling Associates, TMA-SUPREM-4, Instruction<br />
Manual.<br />
4. Silvaco Modeling, Inc.<br />
5. MicroTec-3.03 release note of March 27, 1998 floppy-disk<br />
contains a complete set of MicroTec-3.03 programs for 2D<br />
semiconductor process and device simulation and the Manual in<br />
Adobe Acrobat format. http://www.siborg.ca<br />
6. Silicon <strong>Process</strong>ing for the VLSI Era, Vol.3., Ch.9., StanlyWolf<br />
7. VLSI <strong>Technology</strong>, 2 nd Ed. By S.M.Sze, McGraw Hill, Ch.10.,<br />
1988.<br />
Rochester Institute of <strong>Technology</strong><br />
Microelectronic Engineering<br />
© March 10, 2008, <strong>Dr</strong>. <strong>Lynn</strong> <strong>Fuller</strong>, Professor<br />
Page 47
<strong>T<strong>CAD</strong></strong><br />
HOMEWORK - <strong>T<strong>CAD</strong></strong><br />
1.<br />
Rochester Institute of <strong>Technology</strong><br />
Microelectronic Engineering<br />
© March 10, 2008, <strong>Dr</strong>. <strong>Lynn</strong> <strong>Fuller</strong>, Professor<br />
Page 48
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