Debugging Embedded Systems

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Serial Wire Debug – A new approach To address the issues with JTAG, a new packet-based protocol was develop: Serial Wire Debug (SWD). ARM designed a new debug architecture (CoreSight) taking into account the requirements for Debug and Trace. SWD was designed with this new debug architecture in mind. 36
ARM CoreSight Debug Architecture Overview Bus-based approach (instead of the serial scan interface) for onchip debug control and access. Advantages: It permits debug access while the CPU is running. Debug access is more abstract, less CPU-specific and more scalable. Provides advantage for SoCs that consist on multiple IP blocks from multiple vendors, often using multiple clock and power domains. Register-based access to debug configuration and status information. CPU can also access this registers, giving additional flexibility. Star Topology of the bus, providing true power and clock isolation. New ARM Debug Interface v5 (ADIv5) implements CoreSight architecture. The Debug Access Port (DAP) decouples the external debug interface (JTAG or SWD) from the internal bus-based debug and trace infrastructure. 37
Page 1 and 2: Debugging Embedded Systems Sergio S
Page 3 and 4: Debugging Embedded Systems What is
Page 5 and 6: Debuggers vs Front-Ends Debuggers:
Page 7 and 8: DDD Screenshot 7
Page 9 and 10: Insight Screenshot 9
Page 11 and 12: Debugger: Main Operations (Cont.) D
Page 13 and 14: GDB/MI Interface Command Line Inter
Page 15 and 16: GDB/MI Interface (Cont.) GDB/MI Out
Page 21 and 22: GDB/MI Interface (Cont.) GDB/MI Exa
Page 23 and 24: GDB Remote Serial Protocol GDB Remo
Page 25 and 26: GDB Remote Serial Protocol (Cont.)
Page 27 and 28: GDB Remote Serial Protocol (Cont.)
Page 29 and 30: Debugging Embedded Systems JTAG Ove
Page 31 and 32: IEEE 1149.1 (JTAG) Overview Origina
Page 33 and 34: JTAG TAP Controller State-Machine 3
Page 35: JTAG Shortcomings Not specifically
Page 39 and 40: Debug Access Port components AP (Ac
Page 41 and 42: Debug Access Port accesses descript
Page 43 and 44: Breakpoints: Hardware vs Software H
Page 45 and 46: Debugging Embedded Systems - Typica
Page 47 and 48: SWD Protocol - Header fields Header
Page 49 and 50: SWD Protocol - Timing relationship
Page 51 and 52: SWD - Transfer examples WAIT respon
Page 53 and 54: Connector Types - ETM Trace (legacy
Page 55 and 56: Connector Types - Cortex Debug+ETM
Page 57: Debugging Embedded Systems Debug Se

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