Router Configuration port access/configuration ... - SpaceWire

SpaceWire Router
Configuration Protocol
SpaceWire Working Group
Steve Parkes,
Chris McClements,
Martin Dunstan,
University of Dundee

Contents
! SpaceWire Router
! Configuration Protocol
– Read Register
– Write Register
! FEIC
– Protocol Extensions
! Requirements

SpaceWire Network
MEMORY
1
SENSOR 1
2
1
3 4
ROUTER
1
5
6
7
8
P 1 P 2
SENSOR 2
1
2
ROUTER
2
3 4
MEMORY
2
8
7
6
5
P 3 P 4
Processor Array

SpaceWire Network
MEMORY
1
SENSOR 1
RR
RR
RR
P 1 P 2
SENSOR 2
RR
RR
MEMORY
2
RR
P 3 P 4
Processor Array

SpaceWire
Interfaces
SpaceWire
Port 1
SpaceWire
Port 2
SpaceWire
Port 3
SpaceWire
Port 4
SpaceWire
Port 5
SpaceWire
Port 6
SpaceWire
Port 7
SpaceWire
Port 8
Control
Logic
Non-blocking
Crossbar
Switch
Routing
Table
Status/Error
Registers
Control
Registers
Configuration
Port
Status
Outputs
External
Input/Output
External
Input/Output
Input FIFO
Output FIFO
External Port
Input FIFO
Output FIFO
External Port
Tick
Counter
Time-Code
Inputs/Outputs

Configuration Port and Registers
CONTROL
REGISTERS
CONFIGURATION
PORT
CONFIGURATION BUS
LINK
REGISTER LINK
REGISTER LINK
REGISTER
ROUTING
TABLE
ROUTING
(224
TABLE
ADDR) ROUTING
TABLE

Configuration Packet Formats
Configuration write packets:
PATH
ADDR
PRCOL
RETURN
ADDR
CMD
REG
ADDR
DATA CHKSUM EOP
Configuration read packets:
PATH
ADDR
PRCOL
RETURN
ADDR
CMD
REG
ADDR
CHKSUM EOP
Configuration write and read reply packets:
PATH
ADDR
CMD
REG
ADDR
ACK/
DATA CHKSUM EOP
NACK

Configuration Packet Formats
The configuration commands have the following format:
7
0
1 RSV RSV RSV RSV A8 RD WR
WR is the write flag, when set the command is a write command.
RD is the read flag, when set the command is a read command.
A8 is the most significant bit of the 9-bit configuration register address.
RSV represents reserved bits.

Checksum Coverage
PATH
ADDR PRCOL RET
CMD REG
ADDR
ADDR
DATA
CHK
SUM
EOP
CHECKSUM COVERAGE

Write
Command
Configuration Port
Destination Address
Protocol
Write Address
Write Command
Return Address
Write Data
Checksum
COMMAND
6
2
0
32
3
8
WR
ADR DA0
DA1 DA2 DA3 CHKEOP
REPLY
5
3
8
WR
ADR DA0
DA1 DA2 DA3 ACKCHK
EOP
Return Port
Return Address
Copy Write Command
Copy Write Address
Copy Write Data
ACK/NACK
New Checksum

Read
Command
Configuration Port
Destination Address
Protocol
Checksum
Write Address
Read Command
Return Address
COMMAND
6
2
0
32
3
8
RD
ADR CHKEOP
REPLY
5 3 8 RD ADR DA0 DA1 DA2 DA3 ACKCHK
EOP
Return Port
Return Address
Copy Read Command
Copy Read Address
Read Data
ACK/NACK
New Checksum

Autonomous Planetary Landers
Position
Initialisation
Surface
Relative
Navigation
Hazard
Detection
Touch-down

Feature Tracking
“Landmark”
Tracking
Target
Landing
Site

Feature Extraction IC
Camera Control
SpaceWire
Mini-Router
Image
Memory
Feature
Detection
Local
Maximum
Feature
Tracking
Selection
Feature
List
Manage
FEIC

FEIC Video

Feature Extraction IC
Camera Control
Download Test Image (DMA)
SpaceWire
Mini-Router
Signal Event
Transfer Feature List
Read/Write Control/Configuration Registers
Image
Memory
Feature
Detection
Local
Maximum
Feature
Tracking
Selection
Feature
List
Manage
FEIC

FEIC Requirements
! Needed to extend the set of configuration
commands
! Write data block to consecutive registers
! Write data block to one register (DMA)
! Signal event from FEIC

Controlling the FEIC
! All interaction is via registers:
– executable command registers
– write-only configuration registers
– read-only status/information registers
– read-write configuration registers
! Example: reading LN list of new points:
– write to the “send-LN
LN-list” register
– FEIC will send the data later (but ASAP)

SpaceWire Interface
! Use router configuration packet format:
! Each packet defines a register operation:
– read/write from/to one 32-bit register
– write to consecutive 32-bit registers
! improve throughput for burst writes
– write multiple to one register (e.g.(
DMA)

Command Byte (1)
1 F1 F0 C2 A9 A8 C1 C0
C2
C1
C0
Description
0
0
0
Not valid
0
0
1
Write single 32-bit register
0
1
0
Read single 32-bit register
0
1
1
Read-modify
modify-write (not used in FEIC)
1
0
0
Write multiple to one register (DMA)
1
0
1
Write multiple to consecutive registers
1
1
0
List/event packet from FEIC
1
1
1
Not valid

Command Byte (2)
1 F1 F0 C2 A9 A8 C1 C0
! The F0/F1 bits are for fill bytes:
– indicate the number of padding bytes
– padding is between payload and checksum
– helps RISC CPUs (memory alignment)
! The A8/A9 bits are register address bits:
– FEIC has a 10-bit address space
– register address byte contains bits 0-70
– command byte has bits 8 and 9

Command Packets (to FEIC)
Checksum coverage
Target
Address
Protocol
Return
Address
Command
Register
Address
Checksum EOP
Target
Address
Return
Address
Data
Data
Data
Data

Data Packets from FEIC
Checksum coverage
Leading
zeros
are
dropped
by
FEIC
Target
Address
Target
Address
Target
Address
Target
Address
Command
(0x92)
Payload
Type
Payload
Payload
Payload
Payload
Checksum EOP
Payload

Write Multiple
Command
Configuration Port
Destination Address
Protocol
Write Address
Write Command
Return Address
Write Data
Checksum
CMD
DA1
REPLY
RP
DA2
RA1
DP
RA2
PI
WR
RA1 RA2
ADR D0
WR ADR D0
D1 D2 D3
D1 …. DN-1
ACKCHK
EOP
FILLCHKEOP
Return Port
Return Address
Copy Write Command
Copy Write Address
Copy Write Data
ACK/NACK
New Checksum

Requirements
! Read/Write Register (32-bit register)
! Read/Modify/Write Register
! Write to block of registers (start address, length?)
! Read from block of registers (start address, length)
! DMA Write Block of Data (start address, length?)
! DMA Read Block of Data (start address, length)
! Signal Event
! Send Data Block on Event
! For single register commands
– can buffer and check checksum before actually writing data
! When transferring large blocks
– cannot buffer and check first,
– just flag error at end of transfer
– if there was an error.
– Use of intermediate checksums?
! CRC or checksum?