Amplifiers

cMoS 

Amplifiers 

Most CMOS amplifiers have identical bipolar counterparts and can therefore be 

analyzed in the same fashion. Our study in this chapter parallels the developments in 

Chapter 5, identifying both similarities and differences between CMOS and bipolar 

circuit topologies. It is recommended that the reader review Chapter 5, specifically, 

Section 5.1. We assume the reader is familiar with concept such as I/O impedances, 

biasing, and dc and small-signal analysis. The outline of the chapter is shown below 

e 

;r'.s 

GENERAT COI{SIDERATIOI{S 

7.1.1 MOS Amplifier Topologies 

Recall from Section 5.3 that the nine possible circuit topologies using a bipolar transistor 

in fact reduce to three useful configurations. The similarity of bipolar and MOS 

small-signal models (i.e., a voltage-controlled current source) suggests that the same 

must hold for MOS amplifiers. In other words, we expect three basic CMOS amplifiers: 

the "common-source"(CS) stage, the "common-gate"(CG) stage, and the 

"source follower." 

7.1,2 Biasing 

Depending on the application, MOS circuits may incorporate biasing techniques 

that are quite different from those described in Chapter 5 for bipolar stages. Most of 

these techniques are beyond the scope of this book and some methods are studied 

in Chapter 5. Nonetheless, it is still instructive to apply some of the biasing concepts 

of Chapter 5 to MOS stages. 

329

330 Chapter 7 CMOS Amplifiers 

voo= 1'8v 

BD 

lD 

10 kO 

M1 

1 kc) 

Figure 7.1 MOS stage with biasing. 

consider the circuit shown in Fig. 7.1, where the gate voltage is deflned by R1 

and R2. We assume M1 operates in saturation. Also, in most bias calculations, we cal 

neglect channel-length modulation. Noting that the gate current is zero, we have 

Since[:VGs*IpRs, 

Also, 

v*: =P^ vro. ' 

" 

R1*Rz " 

R" 

alf *vDD:vcs * IoRs' 

1W 

Io:)pnC*7wcs-Vru)2. 

(7.1 

(7.2r 

(i.r) 

Equations (7.2) and (7.3) can be solved to obtain Ip and. v74, either by iteration or 

by finding Ip from (7.2) and replacing for it in (7.3): 

That is, 

/ h \l r w 

(-F&=voo - u.t) -vru)'. 

*: )u,c*7(vcs 

(7.4 

v65 : -(v1- vru) . - ,t- . (7.5 

lrr, -r-r' #Er"rr. 

where 

I 

r p^r/^^ 

''''\R,+R, 

: -(vt-vril * ,ln? +zv,( fzvpo= - v. \ 

\ 

"n)' 

(7.61 

I 

,,: e., 

*r,+A. 

This value of v6 can then be substitute d in (7.2) to obtain ID. of course, Vy musr 

exceed Vx -Vrn to ensure operation in the saturation region. 

Determine^ the bias current of M1 in Fig.7.1 assumin1Vrn:0.5V, llnCo*: 

l:O yA(y'z, W/L 5/0.18, and ,1. : = 

0. What is rhe maximum altowabte vatue of 

Rp for M 1to remain in saturation?

7.1 General Considerations331 

Solution 

We have 

u*: 

ffivoo 

:1.296V. 

(7.8) 

(7.e) 

With an initial guess VGS :1 V, the voltage drop across R5 can be expressed as 

Vx - Vcs: 286 mV, yielding a drain current of 286 prA. Substituting for 12 in 

Eq. (7.3) gives the new value of V65 as 

Vcs : Vrn * 

2Io 

-w 

&nCo*| I, 

(7.10) 

Consequently, 

and hence 

:0.954V. 

a 

Vx - Vcs 

In: 

:332 p,A, 

Vcs : 0.989 V. 

(7.1r) 

(7.12) 

(7.13) 

(7.1,4) 

This gives Io :297 p,A. 

As seen from the iterations, the solutions converge more slowly than those 

encountered in Chapter 5 for bipolar circuits. This is due to the quadratic (rather 

than exponential) Ip-V6 dependence. We may therefore utilize the exact result in 

(7.6) to avoid lengthy calculations. Since Vt :0.36Y, 

VGS :0.974V 

(7.1s) 

and 

Io: 

Vx - Vcs 

(7.1.6) 

:312 p.A. 

(7.17) 

The maximum allowable value of R2 is obtained if Vy : Vx - Vrn : 0'786 V' 

That is, 

Vno - Vv 

RD: 

Ip 

:3.25k9. 

(7.18) 

(7.1e) 

Exercise 

What is the value of R2 that places M1 at theedge of saturation?


In the circuit of Example 7.1., assume Mt islui' saturation and R2:2.5ke and 

compute (a) the maximum allowable value of w /L and(b) the minimum allowable 

value of R5 (withW lL: 5/0.18). Assume .i.: 0. 

Solution 

(a) As W/Lbecomes larger, Ml cancafiy a larger current for a given V65. With 

Rn :2.5 kQ and Vx : 1.286 V, the maximum allowable value of 1p is given by 

, Vno -VY 

to: 

Ro 

:406 p.A. 

(7.20) 

(7.21) 

The voltage drop across R5 is then equal to 406 mV, yielding Vcs:I.2B6V- 

0.406 V : 0.88 V. In other words, M1 must carry a current of 406 prA with Vcs : 

0.88 V: 

-1,W Io :'rtt,C*|{vo, - Vrtl)z 

(7.22) 

406 p.A: (50prA/v'7\1o.zavf , 

'L' 

(7.23) 

thus, 

w 

T :56'2' 

(7.24) 

(b) with w I L : 5 /0.1,8, the minimum allowable value of R5 gives a drain 

current of 406 pcA. Since 

Vcs : Vra * 

w 

P"C*T 

(7.2s) 

: 1.041V, 

the voltage drop across R5 is equal to Vy - V65 : 

Vx -Vcs 

/Kc:- ^ 

"Ip 

:604 O. 

245 mY .It follows that 

(7.26) 

(7.27) 

(7.28) 

Exercise Repeat the above example if V7s :0.35 V. 

The self-biasing technique of Fig. 5.22 can also be applied to MoS amplifiers 

Depicted in Fig. 7 .2, the circuit can be analyzed by noting that Ml is in saturation 

(why?) and the voltage drop across R5 is zero. Thus, 

IoRn *Vcs I RsIo:Voo. 

(7.29r 

Finding V55 from this equation and substituting it in (7.3), we have 

,o:ttr,C*[Voo- 

(Rs* Rn)Io -Vrr7' 

(7.30 r

7.1 General Considerations 333 

Fisure 7.2 Self-biased MOS stage. 

T'oo 

?"o 

B6 l 

;rtrro 

-q'' t"' 

where channel-length modulation is neglected. It follows that 

Ir 

(Rs + Ro)2 Po - zl tvoo - vrn)(Rs+ Rots- -L-- 

lro *,roo - vru)z : 0' 

I 

wnC^T ) 

,r.r9 

Calculate the drain current of M1 inFig. T .3 lf p'nCo": 100 prA/Vz, Vrn - 0.5 V, 

and .i,: 0. What value of Rp is necessary to reduce Ip by a factor of two? 

Vps= 1.8 Y 

flD 

20 kQ 

1ko 

W5 

Mt T 

=oro 

200 f, 

Figure 7.3 Example of self-biased MOS stage. 

Solution 

Equation (7.31) gives 

Io:556 PtA. 

To reduce Ip to278 prA, we solve (7.31) for R2: 

RD :2.867 kf2. 

(7.32) 

(7.33) 

Exercise 

Repeat the above example if Voo drops to 1'2 V' 

7,1.3 Realization of Gurrent Sources 

MOS transistors operating in saturation can act as current sources. As illustrated in 

Fig. 7.4(a), an NMOS device serves as a current source with one terminal tied to 

ground, i.e., it draws current from node X to ground. On the other hand, a PMOS


x x vu{l,'"z+? T'o'-T'* 

vo*jff, i nr.lf*i' 

n.+c",*6 

r-LYY=X 

?: 

(a) 

(b) 

Figure 7.4 (a) NMOS device operating as a current source, (b) PMOS device operating 

as a current source, (c) PMOS topology not operating as a current source, (d) NMOS 

topology not operating as a current source. 

(c) 

J 

(d) 

transistor [Fig. 7.4(b)] draws current from Vpp to node Y. If )" : 0, these currents 

remain independent of Vy or Vy (so long as the transistors are in saturation). 

It is important to understand that only the drainterminal of a MOSFET can draw 

a dc current and still present a high impedance. SpecificCly, NMOS or PMOS devices 

configured as shown in Figs. 7.4(c) and (d) do not operate as current sources because 

variation ofVy or Vy directly changes the gate-source voltage of each transistor, thus 

changing the drain current considerably. From another perspective, the small-signal 

model of these two structures is identical to that of the diode-connected devices 

in Fig. 6.34, revealing a small-signal impedance of only llg* (if ), 0) rather than 

- 

infinity. 

COMMON.SOURCE STAGE 

7.2.1 GS Gore 

Shown in Fig. 7.5(a), the basic CS stage is similar to the common-emitter topologi 

with the input applied to the gate and the output sensed at the drain. For small signals 

M1 converts the input voltage variations to proportional drain current changes, and 

R;r transforms the drain currents to the output voltage. If channel-length modulation 

is neglected, the small-signal model in Fig. 7.5(b) yields u;, : u1 and l)ss1 : -ganlRp- 

That is, 

uout 

Ui, 

a result similar to that obtainedfor the 

*S^Rn, (7.341 

common emitter stage in Chapter 5. 

T'oo 

to? 

tnput Apptied/ + 

to Gate 

. tsVout 

n"Jfl"' \ outP''t s"n""o 

(a) 

(b) 

Figure 7.5 (a) Common-source stage, (b) small-signal mode.

7.2 Common-Source Stage 335 

The voltage gain of the CS stage is also limited by the supply voltage. Since g- : 

J2 p."C*(W I L)I o, we have 

zp,c*!tpno, 

(7.3s) 

concluding thattf Ip or.R;r is increased, so is the voltage drop across Ra ( : I2,Rp).' 

For Ml to remain in saturation, 

that is, 

Vno-RnIo.Vcs-Vrn, 

RoIo


The drain voltage is equal to Vpp - RoIo 0.8 V. Since Y65 - 

- Vrn : 0.6 V, the 

device indeed operates in saturation and has a margin of 0.2 V with respect to the 

triode region. For example, if Rp is doubled with the intention of doubling,4,, 

then M1 enters the triode region and its transconductance drops. 

Exercise 

What value of V7s places M1 atthe edge of saturation? 

Since the gate terminal of MOSFETs draws a zero current (at very low frequencies), 

we say the CS amplifler provides a current gain of infinity. By contrast, the 

current gain of a common-emitter stage is equal to B. 

Let us now compute the I/O impedances of the CS amplifier. Since the gate 

current is zero (at low frequencies), 

(7.44j 

a point of contrast to the CE stage (whose R2 is equal to ro). The high input 

impedance of the CS topology plays a critical role in many analog circuits. 

The similarity between the small-signal equivalents of CE and CS stages indicates 

that the output impedance of the CS amplifier is simply equal to 

This is also seen from Fis. 7.7. 

Rout: Ro. 

(7.4s) 

,,F 

? 

v1 

9*vt 

flD 

Figure 7.7 Output impedance of CS stage. 

In practice, channel-length modulation may not be negligible, especially if R2 

is large. The small-signal model of CS topology is therefore modified as shown in 

Fig. 7.8, revealing that 

A,: 

Rin: 

-g^(Rollro) 

@ 

Rout: Rnllro. 

(7.46) 

(7.47) 

(7.48) 

In other words, channel-length modulation and the Early effect impact the CS and 

CE stages, respectively, in a similar manner. 

rtF- 

+ 

v1 

Figure 7.8 Effect of channel-length modulation on CS stage.


Assuming M1 operates in saturation, determine the voltage gain of the circuit 

depicted in Fig. 7.9(a) and plot the result as a function of the transistor channel 

length while other parameters remain constant. 

Yin*--l 

(a) 

(b) 

Figure 7.9 (a) CS stage with ideal current source as a load, (b) gain as a function of device 

channel leneth. 

l 

Solution 

The ideal current source presents an infinite small-signal resistance, allowing the 

use of (7.a6) with ftn : oo: 

Au: -fl,mfo, (7.4e) 

This is the highest voltage gain that a single transistor can provide. Writing g- - 

JTnERtrDI; andro: ().1p)-1, we have 

This result may imply that 

)," a L-1: 

lA,l - 

^.^fi; 

(7.s0) 

1,4, I falls as L increases, but recallfrom Chapter 6 that 

lA,l o< 

2p,nCo*WL 

Ip 

Consequently,lA,l increases with ,L[Fig. 7.9(b)]. 

(7.s1) 

Exercise Repeat the above example if a resistor of value Rr is tied between the gate and drain 

of M.. 

7.2.2 CS Stage With Gurrent-Source Load 

As seen in the above example, the trade-off between the voltage gain and the voltage 

headroom can be relaxed by replacing the load resistor with a current source. The 

observations made in relation to Fig. 7.4(b) therefore suggesthe use of a PMOS 

device as the load of an NMOS CS amplifier [Fig. 7.10(a)]. 

Let us determine the small-signal gain and output impedance of the circuit. 

Having a constant gate-source voltage, M2 simply behaves as a resistor equal to its 

output impedance [Fig.7.10(b)] because ur : 0 and hence gm2u1 :0. Thus, the drain 

node of M1 sees both re1 and 162 to ac ground. Equations (7.46) and (7.48) give 

A,: 

-5il(rotllroz) 

Rout : rorllroz. 

(7.s2) 

(7.s3)


i 

.,1 -- i 

r1:HH1: i 

,lFj 

,; 

Yino-l 

Yin4 

M1 

(a) 

(b) 

Figure 7.10 (a) CS stage using a PMOS device as a current source, (b) small-signal model. 

Figure 7.11 shows a PMOS CS stage using an NMOS currgnt source load. Compute 

the voltage gain of the circuit. 

voo 

Figure 7.'t 1 CS stage using an NMOS device as current source. 

Sofution 

Tiansistor Mz generates a small-signal current equal to gTTouin; which 

through r ot"llr oz, producing u o6 : - gm2v) in(r ollr oz). Thus, 

A,: 

-E*z(rorllro). 

then flows 

(7.s4) 

Exercise 

Calculate the gain if the circuit drives a loads resistance equal to R;. 

7.2.3 GS Stage With Diode-Gonnected Load 

In some applications, we may use a diode-connected MOSFET as the drain load. 

Illustrated in Fig. 7.12(a), such a topology exhibits only a moderate gain due to the 

relatively low impedance of the diode-connected device (Section 7.7.3). With ). : 0, 

M2 acls as a small-signal resistance equal to L l gnp, and (7.34) yields 

1 

Au: -8m1.' - 

8"a 

J'NE;@TDJ; 

JTNE;OTTDJ; 

(wlL)t 

(wlL)z 

(7.ss) 

(7.s6 

(7.s7


Figure7.12,"l ioo, stage using 

" o,oa"-"ol?"cted load, (b) bipolar *t,lllro"rt, 

(c) simplifled circuit of (a). 

Interestingly, the gain is given by the dimensions of M1 and M2 and remains independent 

of process parameters p.n andCo, and the drain current, 12. 

The reader may wonder why we did not consider a common-emittel stage with 

a diode-connected load in Chapter 5. Shown r* Fig. 7.12(b), such a circuit is not used 

because it provides a voltage gain of only unity: 

1, 

Ar: -$mI - 

8mZ 

Icr 1 

Vr. IczlVr 

x -1. 

(7.60) 

(7.s8) 

(7.se) 

The contrast between (7.57) and (7.60) arises from a fundamental difference between 

MOS and bipolar devices: transconductance of the former depends on device 

dimensions whereas that of the latter does not. 

A more accurate expression for the gain of the stage in Fig. 7.12(a) must take 

channel-length modulation into account. As depicted in Fig. 7.12(c), the resistance 

seen at the drain is now equal to (1lg^z)llroz11161, and hence 

/t' \ 

A, : - gnt 

\-llr 

ozllr ot ). 

Similarly, the output resistance of the stage is given by 

(7.61) 

Ro,t: Lllrorllror. 

8m2 

(7.62) 

-I Ifll[f Determine the voltage gain of the circuit shown in Fig' 7.13(a) if L + 0' 

E 

Yi"*l 

Figure 7.1 3 CS stage with diode-connected PMOS device.


Solution 

This stage is similar to that in Fig. 7.72(a), but with NMOS devices changed to 

PMOS transistors: M1 serves as a common-source device and Mt as a diodeconnected 

load. Thus. 

A,: -gm2(*u"'ll'or)' 

(7.63) 

Exercise 

Repeat the above example if the gate of M1 is tied to a constant voltage equal to 

0.5 v. 

7.2.4 CS Stage With Degeneration 

Recall from Chapter 5 that a resistor placed in series with the emitter of a bipolar 

transistor alters characteristicsuch as gain,Ilo impedarces, and linearity. we expect 

similar results for a degenerated CS amplifier. 

Figure 7.14 (a) CS stage with degeneration, (b) small-signal model. 

Figure 7.14 depicts the stage along with its small-signal equivalent (if ), : 0). As 

with the bipolar counterpart, the degeneration resistor sustains a fraction of the input 

voltage change. From Fig. 7.1.4(b), we have 

l)in: 

Ul * g*u1R5 

(7.64) 

and hence 

uin 

,,:1+g;Rr. 

(7.6s) 

Since g-u1 flows through Rp, t)6y7 - -gaulRp and 

I)out _ _ 8*Rn 

'uin 1 * g-Rg 

: - 

Rp 

I *or' 

8^ 

a result identical to that expressed by (5.157) for the bipolar counterpart. 

(7.66) 

(7.67)


Ī 

a.+:lrrl.lt:I 

ffiComputethevoltagegainofthecircuitshowninFig.7.15(a)if)":0. 

vin4 

1 

9mz 

(a, 

Fisure 7.15 (a) Example of CS stage with degeneration, (b) simplified circuit. 

(b) 

Sofution 

Exercise 

Tiansistor M2 sewes as a diode-connectedevice, presenting an impedance of 

1.1g",21Eig.7.15(b)]. The gain is therefore given by (7.67)it R5 is replaced with 

r/g'a: 

What happens if ), t' 0 for M2? 

R.t 

a -_ " 

11 

_+_ 

9mr 9r,a 

(7.68) 

In parallel with the developments in Chapter 5, we may study the effect of a 

resistor appearing in series with the gate (Fig. 7.16). However, since the gate current 

is zero (at low frequencies), R5 sustains no voltage drop and does not affect the 

voltage gain or the I/O impedances. 

Effect of Transistor Output lrnpedance As with the bipolar counterparts, the 

inclusion of the transistor output impedance complicates the analysis and is studied 

in Problem 31. Nonetheless, the output impedance of the degenerated CS stage plays 

a critical role in analog design and is worth studying here. 

Figure 7.17 shows the small-signal equivalent of the circuit. Since R5 carries a 

current equal to 176 (why?), we have q : -ixRs. Also, the current throttghro is equal 

Figure 7.16 CS stage with gate resistance.


,rF 

f 

,! 

T 

l 

Figure 7.17 Output impedance of CS stage with degeneration. 

to iv - gmuL : ix - B^GiyR5) : ix * g*ixRs. Adding the voltage drops across rp 

and R5 and equating the result to ux, we have 

and hence 

ro(ix * g-ixRs) * iaRs : yy, 

UY 

,.:ro(1 

LX 

+g-Rs)+Rs 

: (1 + g^ro)Rs * ro 

(7.6e) 

(7.70) 

(7.71) 

x g*rsRs * ro. 

(7.72) 

Alternatively, we observe that the model in Fig. 7.I1 is similar to its bipolar counterpart 

in Fig. 5A6@) but with ro : oo. Lettin Ern --> oo in Eqs. (5.196) unO 1S.tlZ; yi"ta, 

the same results as above. As expected from our study of the bipolar degenerated 

stage, the MOS version also exhibits a ,,boosted" output impedance. 

compute the output resistance of the circuit in Fig. 7.1g(a) if M1 and, M2 are 

identical. 

[- Fout 

T' 

Yo*.|lnrr 

--t 1ryil, 

; 

(a) 

l- Fout 

?V 

,,r-{f*,o, 

*'l 

f fi,"'", 

; 

(b) 

Figure 7.18 (a) Example of cS stage with degeneration, (b) simplified circuit. 

Solution 

The diode-connectedevice M2 can be represented by a small-signal resistance 

of (l/g"a)llroz x 118-2. Tiansistor M1 is degenerated by this resistance, and from 

(7.70): 

1 

Rout: ror(1+ r^*) * (7.73) 

8*z


which, since g-t : gnD: g., reduces to 

Rort:Zror+L (7.74) 

8* 

x 2ror. 

Q.75) 

Exercise Do the results remain unchanged lf Mz isreplaced with a diode-connected PMOS 

device? 

Determine the output resistance of the circuit in Fig. 7.1-9(a) and compare the result 

with that in the above example. Assume M1 and M2 are in saturation. 

?Y I 

voz4\tr', 

I 

vot 4E M, 

I ; 

(a) 

[- Rout * 

[- Fout 

?V 

t-r 

,,HE *ro, 

'' t- 

* ro, 

; 

o) 

Figure 7.19 (a) Exampte of CS stage with degeneration, (b) simplified circuit. 

Solution 

With its gate-source voltage flxed, transislor M2 operates as a current source, introducing 

a resistance of r 62 ftomthe source of M1 to ground [Fig. 7.19(b)]. 

Equation (7.71) can therefore be written as 

Rout : (I * gnro)roz I rot Q.76) 

N gmtrorro2 + ro1. Q '77) 

Assuming Smrroz ) 1 (which is valid in practice), we have 

Rout N gmtrolroz. 

We observe that this value is quite higher than that in (7.75). 

Q.78) 

Exercise Repeat the above example for the PMOS counterpart of the circuit. 

7.2.5 GS Gore With Biasing 

The effect of the simple biasing network shown in Fig. 7.1 is similar to that analyzed for 

the bipolar stage in Chapter 5. Depicted in Fig. 7.20(a) along with an input coupling 

capacitor (assumed a short circuit), such a circuit no longer exhibits an infinite input 

impedance: 

Rin: RtllRz. 

(7.7e)

344 Chapter Z CMOS Amplifiers 

voo 

voo 

(a) 

G) {c} 

t11 (a) cS stage 

:l1ll" 

with input coupling capaciror, (b) 

(c) 

incrusion 

use of bypass 

of gate 

capacitor. 

resistance, 

ffiui,:i: 

circuit is driven bv a finite source impedange fFig.7.z0(b) r, the vortage 

a RrllRz 

- 

-Rp 

--' : pol ft1lRz l : 

(7.80) 

- 

s- +Rt 

where .1, is assumed to be zero. 

As mentioned in chapler 5, it is possibre to_utilize degeneration 

stability for 

but eliminate 

bias point 

its eifect on the small-signut p"rro.*u-i"" 

capacitor 

i] *"ur* of a bypass 

[Fig' 7'20(c)], the case of !$ike 

bipolar realizarion, 

input 

) 

this does 

impedance 

not alter 

of the 

the 

CS staee: 

I- 

Err 

Ef 

but raises the voltage gain: 

R;" : RrllRz, 

(7.81) 

RtllRz 

,a' ^ : -F;T Rr ilE 8^Rn' (7.82) 

Desiqn the cS stage of Fig. 7.20(cXor a voltage gain of 5, an 

50 input 

kd, impedance 

anda powJr 

of 

b"dg;; of 5'mW arr'_Jrric,, : 100 p.A/yr, vir: 0.5 v, 

'l' = 0, andVpp: 1.8 V. Also, assume a voltage drop of 400 mV across R(. 

solution 

The power budget along with vno..= 1.8 v implies a maximum supply current of 

2'78 mA' As an initial guess, we allocate 2.7 ;A to M1 andthe rem'aining s0 pcA 

to R1 and R2. It follows that 

Rs : 148 Q. 

(7.83) 

As with typical design problems, the choice of g* and,R2 

so 

is 

long 

somewhat 

as g*Rp : 

flexible 

5. However, with 12 known, we must ensure 

for 

a 

765, 

reasonabre 

e.8., Vcs: 

value 

1 V. This choice yields 

2In 

Vcs - Vru 

1 

92.6c"' 

(7.84) 

(7.8s)

7.3 Common-Gate Stage 345 

and hence 

Writing 

Ro:4639' 

_ 1 

Io:ip,C^7tV.t-Vrn)' 

^W 

(7.86) 

(7.87) 

glves 

y:no. 

L 

With tr/65 : 1V and a 400-mV drop across R5, the gatevoltage reaches 1.4 V, 

requiring that 

R2 r, 

nt a *Voo:'L'4V' 

which, along with R;, : RrllRz: 50 k$), yields 

Rr : 64'3 kQ 

Rz:225k9. 

(7.88) 

(7.8e) 

(7.e0) 

(7.e1) 

We must now check to verify that Mt indeed operates in saturation. The drain 

voltage is given by Voo - InRo: l-.8 V - 1.25 V : 0.55 V. Since the gate voltage 

is equal to 1.4 Y the gate-drain voltage difference exceeds V7s, driving Ml into 

the triode region! 

How did our design procedure lead to this result? For the given Ip, we have 

chosen an excessively large Rp,i.e., an excessively small g- (because S^Ro:5). 

even though tr/65 is reasonable. We must therefore increase g. so as to allow a lower 

value for R2. For example, suppose we halve R2 and double g- by increasingW lL 

by a factor of four: 

w 

(7.e2) 

- :864 

L, 

6m- 

46.3rj"' 

The correspondingate-source voltage is obtained from (7.84): 

Vcs:250mV' 

(7.e3) 

{7.e4) 

yielding a gate voltage of 650 mV. 

Is M1 in saturation? The drain voltage is equal to Voo - RoIn:1.17Y, a 

value higher than the gate voltage minus V7s. Thus, M1 operates in saturation. 

Exgrcise Repeat the above example for a power budget of 3 mW and Vpp : L.2Y . 

v.ffi 

COMMON.GATE STAGE 

Shown in Fig. 7.2\, the CG topology resembles the common-base stage studied in 

Chapter 5. Here, if the input rises by a small value, AV, then the gate-source voltage 

of M1 decreases by the same amount, thereby lowering the drain current by g*LV


tnput Apptied/ 

to Source 

Figure'1.21 Common-gate stage. 

T'oo 

?'o 

F Vout 

/u.,lFno \ou,oursensed 

Vin# 

at Drain 

and raising Vou, by g*LV Rp. That is, the voltage gain is positive and equal to 

Ar: 

g^Rp. 

The CG stage suffers from voltage headroom-gain trade-offs similar to those -r 

the CB topology. In particular, to achieve a high gain, a high 1p or Rp is necessa:tr 

but the drain voltage, Vno - IoRo, must remain above Va -Vrn to ensure M, li 

saturated. 

A microphone having a dc level of zero drives a CG stage biased at Ip - 0.5 mA. 

It W I L : 50, ptnCo* : 100 pAlYz, Vra : 0.5 V, and Vpp : 1.8 V, determine the 

maximum allowable value of Rp and hence the maximum voltage gain. Neglect 

channel-lensth modulation. 

Solution 

WifhW lL known, the gate-source voltage can be determined from 

,o :'rr,c^!rro, - vrn)t (7.96t 

AS 

For M1 to remain in saturation, 

Vcs -- 0.947 Y. 

(7.e7 t 

and hence 

Vnn-IoRo>Vn-Vt.u 

RD


V6 = 0.947 V 

Figure 7.22 Signalevels in CG stage. 

We now compute the I/O impedances of the CG stage, expecting to obtain results 

similar to those of the CB topology. Neglecting channel-length modulation for now, 

we have from Fig. 7.23(a) ur : -ux and 

iy: 

-grdlt 

(7.101) 

(7.102) 

: $mUX. 

That is, 

R,n: L, (7.103) 

8m 

a relatively low value.Also, from Fig.l.23(b),u1 : 0 and hence 

Rou : RD, 

Q.L04) 

an expected result because the circuits of Figs. 7.23(b) and7.7 are identical. 

Let us study the behavior of the CG stage in the presence of a finite source 

impedance (Fig. 7.2q but still with ). : 0. In a manner similar to that depicted in 

Chapter 5 for the CB topology, we write 

1, 

g- 

UX: -T:-Uin 

(7.10s) 

:+R.s 

8* 

1, 

- -tl. 

1+ g^Rs"'n' 

(7.106) 

(a) 

Figure 7.23 (a) Input and (b) output impedances of CG stage.

348 Ghapter 7 CMOS Amplifiers 

Uout 

FYo 

Fs vx 

-{!1-- 

"'"Ql 

Figure7.24 Simplification of CG stage with signal source resistance. 

E= 

+* 

Thus, 

Uout 

uin 

uout . 

uX 

UX Uin O 

(7.ru7) 

8^Ro 

1*g-Rs 

(7.108) 

Ro 

: -l--' 

(7.1@) 

-+Rs 

8m 

The gain is therefore equal to that of the degenerated CS stage except for a negative 

sign. 

In contrast to the common-source stage, the CG amplifier exhibits a current gain 

of unity: the current provided by the input voltage source simply flows through the 

channel and emerges from the drain node. 

The analysis of the common-gate stage in the general case, i.e., including both 

channel-length modulation and a finite source impedance, is beyond the scope of 

this book (Problem 4L). However, we can make two observations. First, a resistance 

appearing in series with the gate terminal [Fig. 7.25(a)] does not alter the gain or vo 

impedances (at low frequencies) because it sustains a zero potential drop-as if its 

value were zero. Second, the output resistance of the CG stage in the general case 

[Fig. 7.25(b)] is identical to that of the degenerated CS topology: 

Rout:(I+g*ro\Rs+ro. (7.110) 

(a) 

(b) 

Figure 7.25 (a) cG stage with gate resistance, (b) output resistance of cG stage.


For the circuit shown in Fig. 7 .26(a), calculate the voltage gain if ). : 0 and the 

output impedance if ). > 0. 

vpo 

RD 

Vout 

vb 

Figure 7.26 (a) Example of CG stage, (b) equivalent'lnput network, (c) calculation of 

output resistance. 

We first compute uyf u;nwith the aid of the equivalent circuit depicted in Fig. 

7.26(b): 

1ll 1 

UX c*llc^ 

(7.111) 

wtn 

1il1 

:ll: +ns 

4mz ll 9mt 

Noting that uouyf uy : gmrRD, we have 

1 

1-t (g^t * g"a)Rs 

(7.112) 

uout 

,^: 

SnRn 

l+@^1 +g,,rfu 

(7.1.r3) 

To compute the output impedance, we first consider R6ys1, as shown in Fig. 

7.26(c), which from (7.110) is equal to 

Routt : (t* s*tro) (fitlr-tt^r) * ro' 

N s-rot(a rror) * rot. 

\4mz / 

The overall output impedance is then given by 

Rout 

- Rou*llRo 

r / 1 \ 'lll 

xlB^tror { - llRs}+rp1 llln2. 

L \8-z / lll 

(7.114) 

(7.11s) 

(7,1.1,6) 

(7.1r7) 

Exercise 

Calculate the output impedance if the gate of M2 is tied to a constant voltage.


7.3.7 GG Stage With Biasing 

Following our study of the cB biasing in chapter 5, we surmise the cG amplifier 

can be biased as shown in Fig. 7.27.Providing a path for the bias current to ground. 

resistor R3 lowers the input impedance-and hence the voltage gain-if the signal 

source exhibits a finite output impedance, R5. 

voo 

R1 

Bs 

vin"-tr!H 

Figure 7.27 CG stage with biasing. 

Since the impedance seen to the right of node X is equal to full(Ilg), 

we have 

Uout 

uin 

uX . 

Uout 

uin 

Dx 

(7.118) 

Rzll(1/s^) 

'**Rn, 

(7.11e) 

&ll(Ils; + Rs 

where channel-length modulation is neglected. As mentioned earlier, the voltage 

divider consisting of R1 and R2 does not affect the small-signal behavior of the circuit 

(at low frequencies). 

Design the common-gate stage of Fig. 7.27 for the following parameters: voulf 

1)in : 5, Rs - 0, R: : 500 {2, I/g^: 50 Q, power budget : 2mW, Voo :1.8Y. 

Assume &nCor:100 p,A/Yz,Vra :0.5 V, and l. : 0. 

Solution 

From the power budget, we obtain a total supply current of 1.11 mA. Allocating 

10 pA to the voltage divider, R1 and R2, we leave 1.1 mA for the drain current of 

M1. Thus, the voltage drop across R3 is equal to 550 mV. 

We must now compute two interrelated parameters: W/L and Ra. A larger 

value ofW lL yields a greatet gm,allowing a lower value of R2. As in Example j.1,j,, 

we choose an initial value for v6s to arrive at a reasonable guess for W lL.For example,if 

V65 - 0.8 V, thenW/L :244,and g*:2Inl(Vcs - Vrn): (136.4 e)-1, 

dictating Ro : 682f2 for uou.f u;, : 5. 

Let us determine whether M1 operates in saturation. The gate voltage is equal 

to V1;s plus the drop across R3, ilmourrting to 1.35 V. On the other hand, the 

drain voltage is given by Von - IoRo: 1.05 V. Since the drain voltage exceeds 

Vc - Vrn, Mt is indeed in saturation.

7.4 Source Follower 3F1 

The resistive divider consisting of R1 and R2 must establish a gate voltage equal 

to 1.35 V while drawing 10 prA: 

Vno 

: 10 pr.A 

(7.120) 

Rr*Rz 

R, 

n' 

-t 

*Voo : l'35 V' 

It follows that Ri : 45 kO and R2 : 135 kS2. 

(7.121) 

Hxercise 

nW/L cannot exceed 100, what voltage gain can be achieved? 

re 

.g.E- 

rE 

re 

Suppose in Example 7.1.4,we wish to minimize w lL (and hence transistor capacitances). 

What is the minimum acceptable valug of W lL? 

Solution 

For a given 1p , asW I L decreases, Vcs - Vra increases. Thus, we must first compute 

the maximum allowable V65. We impose the condition for saturation as 

Von - InRo > Vcs * Vnz - Vrn, (7.122) 

where I/p3 denotes the voltage drop across R3, and set g*Rp to the required gain: 

=,21'== RD:At. 

Vcs - Vru-'' 

Eliminating R2 from (7.122) and (7.123) gives: 

(7.123) 

and hence 

In other words, 

It follows that 

vno -!v., 

-vra) > vcs -vrn *vnz 

\r Vno - Vnz 

vGS_vrH._T;. 

wlL, 

2In 

2 '' 

u,c*(z\ff)' 

w/L > 172.5. 

(7.724) 

(7.12s) 

(7.126) 

(7.127) 

Exerc?se Repeat the above example for,4, : lQ. 

P.S, 

SOURCE FOTLOWER 

The MOS counterpart of the emitter follower is called the "source follower" (or the 

"common-drain" stage) and shown in Fig. 7.28.The amplifier senses the input at the 

gate and produces the output at the source, with the drain tied to Voo. The circuit's 

behavior is similar to that of the bipolar counterpart.


Input Applied 

to Gate 

Figure 7.28 Source follower. 

Yin"-{ 

T'oo 

8,, 

F 

ltt 

F 

vou, 

\ourpur sensed 

atSource 

7.4,1 Source Follower Gore 

If the gate voltage of My in Fig. 7.28 is raised by a small amount, LVin,the gate-source 

voltage tends to increase, thereby raising the source current and hence the outpur 

voltage. Thus, Vrrl "follows" V;n. Since the dc level of 7r4 is lower than that of V; 

by Vcs, we say the follower can serve as a "level shift" circuit. From our analysis of 

emitter followers in Chapter 5, we expect this topololy to exhibit a subunity gain. 

too. 

Figure 7.29(a) depicts the small-signal equivalent of the source follower, including 

channel-length modulation. Recognizing that rs appears in parallel with R1, l*-e 

have 

Also, 

It follows that 

Smur(rollRL) : ,ou,. 

Dout 

uin 

uin=ul *uout. 

8^(rollRL) 

1- * g*(r6llR1) 

rollRr 

1 

I + rollRr 

8^ 

(7.128t 

(7.129t 

(7.130r 

(7.131\ 

The voltage gain is therefore positive and less than unity. It is desirable to maximize 

R; (and rp). 

As with emitter followers, we can view the above result as voltage division between 

a resistanc equal to 1/g^ and another equal to rollRr [Fig. 7.29(b)]. Nore" 

however, that a resistance placed in series with the gate does not affect (7.131)(at 

low frequencies) because it sustains a zero drop. 

1 

9m 

;lMrffvout 

"'"Q] f ".tr'o 

(a) 

(b) 

Figure 7.29 (a) Small-signal equivalent of source follower, (b) simplifled circuit.

7.4 Source Follower 353 

A source follower is realized as shown in Fig. 7.30(a), where M2 serves as a current 

source. Calculate the voltage gain of the circuit. 

4n'{ 

4n'--{ 

M1 

Yo*{ 

(a) 

Figure 7.30 (a) Follower with ideal current source, (b) simplifled circuit. 

(b) 

Sofution 

Since M2simply presents an impedanc" of l,oifro- the output node to ac ground 

[Fig. 7.30(b)], we substitute R; : rozin Eq. (7.131): 

Au: 

If relllrs2) 1/g^r, thenA, * l. 

rollroz 

1, 

- + rotllroz 

8ml 

(7.132) 

Exercise Repeat the above example if a resistance of value R5 is placed in series with the 

source of Mt. 

Design a source follower to drive a 50-Q load with a voltage gain of 0.5 and a 

power budget of 10 mW. Assume FnCox :1.00 p.AlYz, Vrn :0.5 V, i. : 0, and 

Voo:1.8Y. 

Solution 

With Rr : 50 O and 16 : oo in Fig.7 .28, we have 

a-- 

tLD - 

Rr 

1 

-l- + Rr 

8m 

and hence 

1 

8-: 

(7.134) 

50e' 

The power budget and supply voltaggllglq 3 rn4mum supply current of 5.56 mA. 

Using this value for Ip in g^: J2p."C*(W lL)Ip gives 

W/L :360. 

(7.r33) 

(7.13s) 

Exercise What voltage gain can be achieved if the power budget is raised to 15 mW?


It follows from (7.141) that 

w 

L 

L07. (7.rs2) 

Exercise What voltage gain can be achieved itW lL cannot exceed 50? 

Equation (7.140) 

reveals that the bias current of the source follower varies with 

the supply voltage. To avoid this effect, integrated circuits bias the follower by mean. 

of a current source (Fig. 7.33). 

vin'-l 

+ 

Yin"--l 

c2 

c2 

F Vout F Vout 

Figure 7.33 Source follower with biasing. 

y.ffi{ 

SUilIMARY AND'IOIIITIONAT frXAIWFTMS 

In this chapter, we have studied three basic CMOS building blocks, namely, th. 

common-source stage, the common-gate stage, and the source follower. As observe; 

throughout the chapter, the small-signal behavior of these circuits is quite similar tc 

that of their bipolar counterparts, with the exception of the high impedance seen a: 

the gate terminal. We have noted that the biasing schemes are also similar, with tho 

quadratic In-Vcs relationship supplanting the exponential 16-Vps characteristic. 

In this section, we consider a number of additional examples to solidify th. 

concepts introduced in this chapter, emphasizing analysis by inspection. 

- 

HtI 

Calculate the voltage gain and output impedance of the circuit shown in Fig. 73a@). 

(a) 

(b) 

Figure 7"34 

(a) Example of CS stage, (b) simplified circuit.

7.5 Summary and Additional Examples 357 

Sof ution 

We identify M1 as a common-source device because it senses the input at its gate 

and generates the output at its drain. Tiansistors M2 and M3 therefore act as the 

load, with the former serving as a current source and the latter as a diode-connected 

device. T}rtrs, M2 can be replaced with a small-signal resistance equal to re2, &rrd 

Mz with another equal to (1/Srs)llroz. The circuit now reduces to that depicted in 

Fig.73a(b), yielding 

Au: -$m1 

(fitv"'n,o,tt,o,) (7.1s3) 

and 

Note that 1,/9,6 is dominant in both expressions. 

Rout : lllrorllrozllroz. (i.154) 

8^z 

Exercise Repeat the above example if Mzis converted to a diode-connectedevice. 

Compute the voltage gain of the circuit shown in Fig. 7.35(a). Neglect channellength 

modulation in Mr. 

4nd 

Yo-{ 

vpo 

Ms 

M1 

Vout 

M2 

lr 

4n,_-lf nr1 

fitt.o, 

Vout 

(a) 

Figure 7.35 (a) Example of CS stage, (b) simplifled circuit. 

(b) 

Sof ution 

Operating as a CS stage and degenerated by the diode-connectedevice M3,Iransistor 

M1 drives the current-source load, M2. Simplifying the amplifier to that in 

Fig.7.35(b), we have 

a 

-_ 

r02 

71 

- + -llroz 

8m1. 8"a 

(7.1ss) 

Exercise 

Repeat the above example if the gate of M3 is tied to a constant voltage.

358 Chaoter 7 CMOS Amplifiers 

Determine the voltage gain of the amplifiers illustrated in Fig. 7.36.For simplicitl'. 

assume rot : Q in Fig. 7.36(b). 

Yind 

Yo'-l 

M.l 

M1 

(a.) 

(b) 

Fisure 7.3s Examples of (a) CS and (b) CG stages. 

Sofution 

Exereise 

Degenerated by R5, transistor M1 in Fig. 7.36(a) presents an impedance of 

(I * g*1rs1)Rs * rot to the drain of M7 Thus the total impedance seen at the 

drain is equal to l(1" -f g*trot)Rs * ror]llr 02, giving a voltage gain of 

A, : - E*z{f(l * g*tr ot)Rs + ror] | lror}. (7.1s61 

In Fig. 7.36(b),M1 operates as a common-gate stage and M2 as the load, obtaining 

(7.10e): 

^ 

11,,) : =--. 

roz 

t +R, 

8*r 

Replace R5 with a diode-connected device and repeat the analysis. 

(7.157 r 

n 

Ifllfl Calculate the voltage gain of the circuit shown in Fig. 7 .37(a) if i. : 0. 

vop 

RD 

Vout 

vb 

vin 

(al 

(b) 

Figure 7.37 

(a) Example of a composite 

stage, (b) simplified circuit.

7.5 Summary and Additional Examples 3S$ 

Solution 

In this circuit, M1 operates as a source follower and M2 as a CG stage (why?). A 

simple method of analyzing the circuit is to replace uia &nd M1 with a Thevenin 

equivalent. From Fig. 7.29(b), we derive the model depicted in Fig. 7.37(b). Thus, 

R^ 

A,: -T---: 1 

_+_ 

8m7 

8m2 

(7.1s8) 

'r'*r{:r$What 

happens if a resistance of value R1 is placed in series with the drain of Mf 

The circuit of Fig. 7.38 produces two outputs. Calculate the voltage gain from the 

input to Y and to X. Assume .1. : 0 for My. 

Fiqiin i :lr,r Example of composite stage. 

Solution 

For Vou11, the circuit serves as a source follower. The reader can show that if 

ro1 : @, then M3 and Ma do not affect the source follower operation. Exhibiting 

a small-signal impedance of (119^z)11162, transistor Mz acts as a load for the 

follower, yielding from (7.131) 

DoutL 

uin 

1 

-lVoz 

8m2 

1 1,' 

-llroz + - 

8,ra 

6mi 

(7.Ise) 

For Vou12, M1 opetates as a degenerated CS stage with a drain load consisting of 

the diode-connected device M3 and the current source Mq.This load impedance is 

equal to (llS"B)llrozllrp4, resulting in 

1 

-llrozllroq 

Dout2 

- 

8m3 

(7.160) 

wrn 1I 

- + -llroz 

9mt 8,ra 

:',r*rci:sq Which one of the two gains is higher? Explain intuitively why.

Amplifiers

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