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Motivation and Overview<br />

Compensation<br />

DIGITAL CONTROL SYSTEM<br />

EEE354<br />

<strong>Digital</strong> <strong>Controller</strong> <strong>Design</strong><br />

MUHAMMAD NASIRUDDIN MAHYUDDIN<br />

<strong>School</strong> of <strong>Electrical</strong> and <strong>Electronic</strong> Engineering,<br />

UNIVERSITI SAINS MALAYSIA<br />

week 13<br />

Semester II 2007/2008<br />

nasiruddin@eng.usm.my EEE 354 : DIGITAL CONTROLLER DESIGN


Outline<br />

Motivation and Overview<br />

Compensation<br />

week 13: 10/03/2008 - 15/03/2008<br />

1 Motivation and Overview<br />

2 Compensation<br />

Phase-Lag Compensation<br />

Phase-Lead Compensation<br />

nasiruddin@eng.usm.my EEE 354 : DIGITAL CONTROLLER DESIGN


Motivation and Overview<br />

Compensation<br />

Overview of system performance specification<br />

The desired characteristic or performance specification generally<br />

relate to:<br />

steady-state accuracy<br />

transient response<br />

relative stability<br />

sensitivity to change in system parameters<br />

nasiruddin@eng.usm.my EEE 354 : DIGITAL CONTROLLER DESIGN


Motivation and Overview<br />

Compensation<br />

Steady state accuracy<br />

The steady state accuracy is increased if poles at z=1 are added to<br />

the open-loop function and/or if the open loop gain is increased.<br />

However, added poles at z=1 in the open loop function introduce<br />

phase lag into the open loop frequency response, resulting in<br />

reduced stability margins.<br />

The control system design is usually a trade-off between steady state<br />

accuracy and acceptable relative stability.<br />

nasiruddin@eng.usm.my EEE 354 : DIGITAL CONTROLLER DESIGN


Motivation and Overview<br />

Compensation<br />

Transient Response<br />

Typical performance criteria are:-<br />

rise time t r<br />

peak overshoot or peak magnitude M p<br />

resonance peak M r<br />

time-to-peak overshoot t p<br />

settling time t s<br />

nasiruddin@eng.usm.my EEE 354 : DIGITAL CONTROLLER DESIGN


Motivation and Overview<br />

Compensation<br />

transient response<br />

The transient system is related to system bandwidth.<br />

To decrease the tise time and increase speed of response, the<br />

system bandwidth must be increased. However, if significant<br />

high-frequency noise sources are present in the system.<br />

A trade-off must be made between a fast rise time and an acceptable<br />

response.<br />

nasiruddin@eng.usm.my EEE 354 : DIGITAL CONTROLLER DESIGN


Motivation and Overview<br />

Compensation<br />

Characteristic of second-order system<br />

nasiruddin@eng.usm.my EEE 354 : DIGITAL CONTROLLER DESIGN


Motivation and Overview<br />

Compensation<br />

Characteristic of second-order system<br />

Given a second order LTI analog system with transfer function<br />

T(s) =<br />

2<br />

ω n<br />

s 2 +2ζω ns+ω 2 n<br />

which has unit step response, the following<br />

characteristic can be obtained:<br />

√ −ζπ<br />

M p = 1 + e<br />

1−ζ 2<br />

1<br />

M r = √<br />

2ζ 1−ζ<br />

(1)<br />

2<br />

ω n t p<br />

π<br />

= √<br />

1<br />

1−ζ 2<br />

Rule of thumb: resonance peak, M r is set at 2 dB in order to have<br />

suitable peak magnitude, M p . Peak magnitude will have an effect on<br />

the overshoot of the system.<br />

nasiruddin@eng.usm.my EEE 354 : DIGITAL CONTROLLER DESIGN


Motivation and Overview<br />

Compensation<br />

Relative stability<br />

The stability margins (gain margins and phase margins) are related to<br />

peak overshoot M p .<br />

The phase margin can be expressed as,<br />

[<br />

]<br />

φ m = tan −1 q<br />

2ζ √<br />

4ζ 4 +1−2ζ 2<br />

nasiruddin@eng.usm.my EEE 354 : DIGITAL CONTROLLER DESIGN


Sensitivity<br />

Motivation and Overview<br />

Compensation<br />

We prefer that the control system characteristics do not vary as<br />

certain parameters in the system vary due to change in temperature,<br />

humidity, altitude, age and so on. This is due to the fact that the<br />

system characteristic are a function of the system parameters.<br />

A closed-loop transfer function of a discrete system is given by<br />

T(s) =<br />

G(z)<br />

1+G(z)<br />

Sensitivity to a parameter a, is normally defined as a measure of the<br />

percentage change in T(z) to a percentage change in parameter a.<br />

∆T/T<br />

One such definition is sensitivity ≈<br />

∆a/a = ∆T a<br />

∆a T<br />

nasiruddin@eng.usm.my EEE 354 : DIGITAL CONTROLLER DESIGN


Sensitivity<br />

Motivation and Overview<br />

Compensation<br />

∆T is the variation in T caused by ∆a, the variation in parameter a.<br />

Now, we are to find the sensitivity of T with respect to G for a discrete<br />

system:<br />

SG T = ∂T G<br />

∂G<br />

T = 1+G(z)−G(z) G(z)<br />

[1+G(z)] 2 G(z)/[1+G(z)] = 1<br />

1+G(z)<br />

At the frequency ω, we let z = e jωT , and<br />

S T G = 1<br />

1+G(e j ωT)<br />

For this sensitivity to be small within the system bandwidth, we<br />

require that G(e jωT >> 1<br />

Therefore, we can reduce the sensitivity of T to G by increasing<br />

the open loop gain. However, this action will cause stability<br />

problems. Again, a trade-off is there to decide.<br />

nasiruddin@eng.usm.my EEE 354 : DIGITAL CONTROLLER DESIGN


Motivation and Overview<br />

Compensation<br />

Disturbance Rejection<br />

Figure 2: Discrete Control System<br />

In the system shown in Figure 2, F(s) is a disturbance. Since R(s) is<br />

the control input, we design the system such that c(t) is approx equal<br />

to r(t). If F is zero, then<br />

C(z) =<br />

D(z)G 1G 2 (z)<br />

1+D(z)G 1 G 2 (z)R(z)<br />

nasiruddin@eng.usm.my EEE 354 : DIGITAL CONTROLLER DESIGN


Motivation and Overview<br />

Compensation<br />

Disturbance Rejection<br />

hence, in terms of frequency response, we require that<br />

D(e jωT )G 1 G 2 (e jωT ) >> 1<br />

over the desired system bandwidth. Then, C(e jωT ) ≈ R(e jωT )<br />

If we consider only the disturbance input in Figure 2, then,<br />

C(z) =<br />

G 2 F(z)<br />

1+D(z)G 1 G 2 (z)<br />

hence, over the desired system bandwidth,<br />

C(e jωT ) ≈<br />

G 2 F(e jωT )<br />

D(e jωT )G 1 G 2 (e jωT )<br />

nasiruddin@eng.usm.my EEE 354 : DIGITAL CONTROLLER DESIGN


Disturbance<br />

Motivation and Overview<br />

Compensation<br />

Referring to the previous slide, the disturbance response will be<br />

small since the denominator of the expression<br />

is large. Disturbance rejection for the system shown is good<br />

provided we have a high loop gain not occuring at the direct path<br />

between the disturbance input and the system output.<br />

nasiruddin@eng.usm.my EEE 354 : DIGITAL CONTROLLER DESIGN


Control Effort<br />

Motivation and Overview<br />

Compensation<br />

Any physical motor will have a maximum torque that can be<br />

developed. If we can this control effort (the torque) u(t), then |u(t)| will<br />

be bounded. Usually the system to be controlled is simulated without<br />

considering this limitation on the control effort. Then, worst-case<br />

condition is included in the simulation including considering the real<br />

physical characteristic of the motor (or any other actuator).<br />

nasiruddin@eng.usm.my EEE 354 : DIGITAL CONTROLLER DESIGN


Compensation<br />

Motivation and Overview<br />

Compensation<br />

Phase-Lag Compensation<br />

Phase-Lead Compensation<br />

We will learn how to design compensator limited to SISO<br />

system. The compensators to be learnt are the followings:<br />

Phase-Lag Compensator<br />

Phase-Lead Compensator<br />

Lead-Lag Compensator (sekiranya ada masa)<br />

In this chapter, Bode Plot will be used as a tool to design our digital<br />

compensators in frequency response. Therefore, my students are<br />

encouraged to review back steps/procedure in drawing bode plot<br />

correctly. <strong>Controller</strong> <strong>Design</strong> via root locus is not covered.<br />

nasiruddin@eng.usm.my EEE 354 : DIGITAL CONTROLLER DESIGN


Motivation and Overview<br />

Compensation<br />

Phase-Lag Compensator<br />

Phase-Lag Compensation<br />

Phase-Lead Compensation<br />

The transfer function of the phase-lag controller in w-domain:<br />

D lag (w) = K α<br />

w+ω h<br />

w+ω l<br />

,<br />

ω l


Motivation and Overview<br />

Compensation<br />

Phase-Lag Compensator<br />

Phase-Lag Compensation<br />

Phase-Lead Compensation<br />

Figure 3: phase-lag compensator<br />

ω l : low break frequency<br />

ω h : high break frequency.<br />

nasiruddin@eng.usm.my EEE 354 : DIGITAL CONTROLLER DESIGN


Motivation and Overview<br />

Compensation<br />

Phase-Lag Compensation<br />

Phase-Lead Compensation<br />

Procedure to design Phase-Lag Compensator<br />

1 Set the gain K, to the value that satisfies the steady-state error<br />

requirement.<br />

2 Obtain the bode plot using the value of the gain K as defined in<br />

Step 1.<br />

3 Calculate using the formula relating the phase margin with the<br />

transient response specifications.<br />

recap<br />

[<br />

]<br />

φ m = tan −1 q √<br />

2ζ<br />

4ζ 4 +1−2ζ 2<br />

nasiruddin@eng.usm.my EEE 354 : DIGITAL CONTROLLER DESIGN


Motivation and Overview<br />

Compensation<br />

Phase-Lag Compensation<br />

Phase-Lead Compensation<br />

Procedure to design Phase-Lag Compensator<br />

4 Determine the required additional phase φ Mlag to be<br />

contributed by the phase-lag controller in order to satisfy<br />

Step 3 as follows:<br />

φ Mlag = φ Mcomp + φ<br />

φ is the correcting factor to compensate for the phase angle<br />

contribution of the lag compensator. Normally, the correcting factor<br />

within the region of 5 ◦ ≤ φ ≤ 12 ◦ is used. This is due to the fact that<br />

the phase angle contribution of the lag compensator may still<br />

contribute anywhere from −5 ◦ ≤ φ ≤ −12 ◦ of phase at the gain<br />

crossover frequency.<br />

nasiruddin@eng.usm.my EEE 354 : DIGITAL CONTROLLER DESIGN


Motivation and Overview<br />

Compensation<br />

Phase-Lag Compensation<br />

Phase-Lead Compensation<br />

Procedure to design Phase-Lag Compensator<br />

5 Determine the gain crossover frequency f g (rad/s) from the bode<br />

plot which yield φ Mlag . At this frequency, f g , the magnitude plot<br />

must cross the 0 dB line.<br />

6 Determine the magnitude G M (dB) at the gain cross over<br />

frequency f g rad/s from the magnitude plot. Thus, the lag<br />

compensator must contribute −G M dB attenuation so that the<br />

magnitude plot will cross the 0 dB line at f g .<br />

7 Draw the high frequency asymptote of the lag compensator at<br />

−G M dB. Select the higher break frequency about one decade<br />

below the gain crossover frequency f g , that is, ω h = 0.1f g rad/s.<br />

Draw a -20 dB/decade line starting at the intersection of the<br />

higher break frequency ω h with the lag compensator’s high<br />

frequency asymptote until the 0dB line.<br />

nasiruddin@eng.usm.my EEE 354 : DIGITAL CONTROLLER DESIGN


Motivation and Overview<br />

Compensation<br />

Phase-Lag Compensation<br />

Phase-Lead Compensation<br />

Procedure to design Phase-Lag Compensator<br />

8 Locate the lag’s compensator’s lower break frequency ω l at the<br />

intersection of the -20dB/decade line with the 0 dB line. Hence,<br />

the phase-lag compensator’s transfer function is given in the<br />

form of equation.<br />

D lag (w) = K α<br />

w+ω h<br />

w+ω l<br />

,<br />

ω l


Motivation and Overview<br />

Compensation<br />

Phase-Lag Compensation<br />

Phase-Lead Compensation<br />

Procedure to design Phase-Lag Compensator<br />

Figure 4: Bode plot of uncompensated system and the phase-lag<br />

compensator<br />

nasiruddin@eng.usm.my EEE 354 : DIGITAL CONTROLLER DESIGN


Motivation and Overview<br />

Compensation<br />

Phase-Lead Compensator<br />

Phase-Lag Compensation<br />

Phase-Lead Compensation<br />

The transfer function of the phase-lead controller in w-domain will be<br />

of the form:<br />

D lead (w) = 1 β<br />

(<br />

w+ωl<br />

w+ ω l<br />

β<br />

)<br />

=<br />

( )<br />

w+ω<br />

K l<br />

β w+ω h<br />

, ω l


Motivation and Overview<br />

Compensation<br />

Phase-Lead Bode plot<br />

Phase-Lag Compensation<br />

Phase-Lead Compensation<br />

Figure 5: Bode plot of the phase lead compensator<br />

nasiruddin@eng.usm.my EEE 354 : DIGITAL CONTROLLER DESIGN


Motivation and Overview<br />

Compensation<br />

Phase-Lag Compensation<br />

Phase-Lead Compensation<br />

Procedure to design phase-lead controller<br />

1 Set the gain K for the uncompensated system to a value<br />

satisfying the steady state error<br />

2 Draw the bode plot using the value of K above and determine<br />

the uncompensated system phase margin, φ Muncomp .<br />

3 Calculate the closed-loop bandwidth, ω b required to meet the<br />

transient response requirement using correct formula.<br />

4 Calculate the phase angle, φ Mcomp required to meet the damping<br />

ratio or percentage overshoot requirement.<br />

5 Determine the additional phase contribution φ Mlead required from<br />

the phase-lead compensator, in order to meet the desired phase<br />

angle,<br />

φ Mlead<br />

= φ Mcomp − φ Muncomp + φ<br />

φ is normally set at 10 ◦ , a correction factor to compensate for the lower uncompensated system’s phase angle at<br />

this higher phase-margin frequency.<br />

nasiruddin@eng.usm.my EEE 354 : DIGITAL CONTROLLER DESIGN


Motivation and Overview<br />

Compensation<br />

Phase-Lag Compensation<br />

Phase-Lead Compensation<br />

Procedure to design phase-lead controller<br />

6 Determine the value of β from the phase lead compensator’s<br />

required phase margin as follows:<br />

[ ] [ ]<br />

φ Mlead = tan −1 1−β<br />

2 √ = sin −1 1−β<br />

β<br />

1+β<br />

7 Determine the compensator’s magnitude at the peak of the<br />

phase curve using the following formula:<br />

|G lead (jω max )| = 1 √ β<br />

nasiruddin@eng.usm.my EEE 354 : DIGITAL CONTROLLER DESIGN


Motivation and Overview<br />

Compensation<br />

Phase-Lag Compensation<br />

Phase-Lead Compensation<br />

Procedure to design phase-lead controller<br />

8 Determine the new gain crossover frequency ω max on the Bode<br />

plot by finding where the uncompensated system’s curve is the<br />

negative value of |G lead (jω max )| as obtained above. At this<br />

frequency ω max , the uncompensated system’s magnitude plot<br />

must cross the 0 dB line. Since, the compensator’s magnitude<br />

contributes |G lead (jω max )|dB at this frequency, the uncompensated<br />

system’s magnitude curve must be −|G lead (jω max )|dB at this<br />

frequency.<br />

9 Calculate the phase-lead compensators break frequencies ω l<br />

and ω h using the following formula:<br />

ω max = ωl √ β<br />

nasiruddin@eng.usm.my EEE 354 : DIGITAL CONTROLLER DESIGN


Motivation and Overview<br />

Compensation<br />

Phase-Lag Compensation<br />

Phase-Lead Compensation<br />

Procedure to design phase-lead controller<br />

10 The phase-lead compensator’s transfer function is given in the<br />

form of,<br />

( ) (<br />

)<br />

D lead (w) = 1 w+ω l<br />

w+ω<br />

β w+ ω l = K l β w+ω<br />

β<br />

h<br />

, ω l

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