Incisive Platform - Cadence - Cadence Design Systems

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CADENCE INCISIVE PLATFORM FUNCTIONAL VERIFICATION FOR NANOMETER-SCALE ICs 95 50 CONFIDENCE PERCENTAGE TIME Desired Actual Scheduled tapeout Quality gap Predictability gap Final tapeout Changing specs and plans • Changing specs and verification plans • Scarce metrics to guide what to do next • Poor interfaces and limited reuse Scarce metrics • Lack of metrics for ‘done’ • Incomplete spec & plan • Unanticipated scenarios Limited reuse • Unexpected iterations • Time to market delays • Field recalls Project complexity risks Existing and emerging languages Aspect-oriented programming e/IEEE P1647 Executable verification plans Object-oriented programming PSL SystemC/OSCI SystemVerilog/PIEEE 1800 Verilog 2001 VHDL extensions Existing and emerging methodologies Assertion-based verification Constrained directed random test Coverage-driven verification Design for Verification IP reuse Design-level formal analysis Hardware/software co-verification Transaction-based acceleration Transaction-level modeling Verification management Language and methodology risks 1
THE VERIFICATION RISK PARADOX • New languages • New methodologies • New technologies Increase risk Increased complexity • Exponential verification vs. design growth • Super integration • Multiple specialists • Analog and software content Lower risk • Meet schedules • Eliminate results • Eliminate recalls • Avoid cost over-runs The verification risk paradox The electronic design process is filled with uncertainties. Will the design work? Will the software work? Will the device meet performance goals? On top of these and other unknowns, predicting when you will get a design out the door has become less of a science and more of an art. And one missed bug along the way can have the potential to trigger a product recall. While verification acts as an insurance policy against these risks, the exploding complexity of design projects can quickly overwhelm current verification capabilities. This trend is driving design teams to consider new technologies, new languages, and new methodologies. However, any changes to an existing verification environment can introduce unwelcome variables. Every design team today faces this fundamental paradox — how to avoid adding risk while trying to reduce it. The Cadence ® Incisive ® functional verification platform removes risks by automating the verification process and unifying the verification environment. Based on the broadest range of proven technologies and the lowest-risk application of languages and methodologies, it helps to ensure your product will meet specs, ship without bugs, and get to market on time. 2
Page 1: PLATFORM OVERVIEW CADENCE INCISIVE
Page 5 and 6: AUTOMATING THE VERIFICATION PROCESS
Page 7 and 8: Verification management Incisive ve

Incisive Platform - Cadence - Cadence Design Systems

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