Itanium Performance Insights from the IMPACT Compiler
Itanium Performance Insights from the IMPACT Compiler
Itanium Performance Insights from the IMPACT Compiler
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Hot Chips 13<br />
<strong>Performance</strong> of Memory Hierarchy<br />
August 21, 2001<br />
Satisfied accesses x latency (1E12)<br />
1.8<br />
1.6<br />
1.4<br />
1.2<br />
1.0<br />
0.8<br />
0.6<br />
0.4<br />
0.2<br />
0.0<br />
Main memory<br />
(est. 80 cycles)<br />
L3 cache<br />
L2 cache<br />
L1D cache<br />
L1I cache (demand)<br />
L1I cache (prefetch)<br />
INT REQ<br />
L1 I Cache<br />
16KB<br />
4-way<br />
32B lines<br />
2 cycles<br />
L1 D<br />
Cache<br />
16KB<br />
4-way<br />
32B lines<br />
2 cycles<br />
FP REQ<br />
MISS<br />
MISS<br />
L2 Unified<br />
Cache<br />
96KB<br />
6-way<br />
64B lines<br />
6 cycles int<br />
9 cycles fp<br />
MISS<br />
L3 Unified<br />
off chip, on<br />
package<br />
cache<br />
2MB<br />
21 cycles int<br />
24 cycles fp<br />
gcc<br />
ecc<br />
impact<br />
gcc<br />
ecc<br />
impact<br />
gcc<br />
ecc<br />
impact<br />
gcc<br />
ecc<br />
impact<br />
gcc<br />
ecc<br />
impact<br />
gcc<br />
ecc<br />
impact<br />
gcc<br />
ecc<br />
impact<br />
gcc<br />
ecc<br />
impact<br />
gcc<br />
ecc<br />
impact<br />
164 175 181 186 197 254 255 256 300<br />
<strong>Itanium</strong> <strong>Performance</strong> <strong>Insights</strong> <strong>from</strong> <strong>the</strong> <strong>IMPACT</strong> <strong>Compiler</strong><br />
<strong>IMPACT</strong>
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