Multiplexer, Encoder and Decoder

Multiplexer,
Encoder and
Decoder
Lab 05
Prepared By: Rakesh Mahto

Objective
• Basic of Multiplexer
• Basic of Decoder
• Basic of Encoder
• VHDL Code for Decoder
• VHDL Code for Encoder
• Using Components in VHDL

A3
A2
A1
A0
Multiplexer
Input S1 S0 B
S1 S0
Output
B
VHDL
Code
0 0 A0
0 1 A1
1 0 A2
1 1 A3
case S is
when “00” => B B B B

Decoder

Decoder

Encoder
• An encoder performs the inverse function of a
decoder. If input y i is 1 and the other inputs are 0,
then abc outputs represent a binary number
equal to i.
• For example, if y 3 = 1, then abc = 011.
• If more than one input is 1, the highest numbered
input determines the output.
• An extra output, d, is 1 if any input is 1, otherwise d is
0. This signal is needed to distinguish the case of all 0
inputs from the case where only y 0 is 1.

8-to-3 Priority Coder
y 0 y 1 y 2 y 3 y 4 y 5 y 6 y 7 a b c d
0 0 0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0 0 1
X 1 0 0 0 0 0 0 0 0 1 1
X X 1 0 0 0 0 0 0 1 0 1
X X X 1 0 0 0 0 0 1 1 1
X X X X 1 0 0 0 1 0 0 1
X X X X X 1 0 0 1 0 1 1
X X X X X X 1 0 1 1 0 1
X X X X X X X 1 1 1 1 1

VHDL code for decoder
process (I)
begin
case I is
when "00" => O O O O O

VHDL code for encoder
entity prio_encoder42 is port(
r: in std_logic_vector(3 downto 0);
code: out std_logic_vector(1 downto 0);
active: out std_logic
); end prio_encoder42;
input
r
Output
code active
architecture cond_arch of prio_encoder42 is
begin
code

Component Declaration
component component_name
generic(
generic_declaration;
generic_declaration;
…………
);
Port(
port_declaration;
port_declaration;
……….
);

Components in VHDL
architecture xor_arch of even_detector is
signal odd: std_logic;
begin
even

Continue…
Courtesy: Dr. James Plusquellic

architecture str_arch of even_detector is component xor2
-- declaration for xor gate
port( i1, i2: in std_logic; o1:
out std_logic
); end component;
component not1 -- declaration for
inverter port(
i1: in std_logic;
o1: out std_logic
); end component;
signal sig1,sig2: std_logic;
begin
-- instantiation of the 1st xor instance unit1: xor2
port map (i1 => a(0), i2 => a(1), o1 => sig1);
-- instantiation of the 2nd xor instance unit2: xor2
port map (i1 => a(2), i2 => sig1, o1 => sig2);
---instantiation of inverter unit3: not1
port map (i1 => sig2, o1 => even);
end str_arch;

Reference
• Pong P. Chu, “ RTL Hardware Design Using VHDL”.
• Charles H. Roth Jr., Larry L. Kinney, “Fundamentals of
Logic Design”.