Multiplexer, Encoder and Decoder
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<strong>Multiplexer</strong>,<br />
<strong>Encoder</strong> <strong>and</strong><br />
<strong>Decoder</strong><br />
Lab 05<br />
Prepared By: Rakesh Mahto
Objective<br />
• Basic of <strong>Multiplexer</strong><br />
• Basic of <strong>Decoder</strong><br />
• Basic of <strong>Encoder</strong><br />
• VHDL Code for <strong>Decoder</strong><br />
• VHDL Code for <strong>Encoder</strong><br />
• Using Components in VHDL
A3<br />
A2<br />
A1<br />
A0<br />
<strong>Multiplexer</strong><br />
Input S1 S0 B<br />
S1 S0<br />
Output<br />
B<br />
VHDL<br />
Code<br />
0 0 A0<br />
0 1 A1<br />
1 0 A2<br />
1 1 A3<br />
case S is<br />
when “00” => B B B B
<strong>Decoder</strong>
<strong>Decoder</strong>
<strong>Encoder</strong><br />
• An encoder performs the inverse function of a<br />
decoder. If input y i is 1 <strong>and</strong> the other inputs are 0,<br />
then abc outputs represent a binary number<br />
equal to i.<br />
• For example, if y 3 = 1, then abc = 011.<br />
• If more than one input is 1, the highest numbered<br />
input determines the output.<br />
• An extra output, d, is 1 if any input is 1, otherwise d is<br />
0. This signal is needed to distinguish the case of all 0<br />
inputs from the case where only y 0 is 1.
8-to-3 Priority Coder<br />
y 0 y 1 y 2 y 3 y 4 y 5 y 6 y 7 a b c d<br />
0 0 0 0 0 0 0 0 0 0 0 0<br />
1 0 0 0 0 0 0 0 0 0 0 1<br />
X 1 0 0 0 0 0 0 0 0 1 1<br />
X X 1 0 0 0 0 0 0 1 0 1<br />
X X X 1 0 0 0 0 0 1 1 1<br />
X X X X 1 0 0 0 1 0 0 1<br />
X X X X X 1 0 0 1 0 1 1<br />
X X X X X X 1 0 1 1 0 1<br />
X X X X X X X 1 1 1 1 1
VHDL code for decoder<br />
process (I)<br />
begin<br />
case I is<br />
when "00" => O O O O O
VHDL code for encoder<br />
entity prio_encoder42 is port(<br />
r: in std_logic_vector(3 downto 0);<br />
code: out std_logic_vector(1 downto 0);<br />
active: out std_logic<br />
); end prio_encoder42;<br />
input<br />
r<br />
Output<br />
code active<br />
architecture cond_arch of prio_encoder42 is<br />
begin<br />
code
Component Declaration<br />
component component_name<br />
generic(<br />
generic_declaration;<br />
generic_declaration;<br />
…………<br />
);<br />
Port(<br />
port_declaration;<br />
port_declaration;<br />
……….<br />
);
Components in VHDL<br />
architecture xor_arch of even_detector is<br />
signal odd: std_logic;<br />
begin<br />
even
Continue…<br />
Courtesy: Dr. James Plusquellic
architecture str_arch of even_detector is component xor2<br />
-- declaration for xor gate<br />
port( i1, i2: in std_logic; o1:<br />
out std_logic<br />
); end component;<br />
component not1 -- declaration for<br />
inverter port(<br />
i1: in std_logic;<br />
o1: out std_logic<br />
); end component;<br />
signal sig1,sig2: std_logic;<br />
begin<br />
-- instantiation of the 1st xor instance unit1: xor2<br />
port map (i1 => a(0), i2 => a(1), o1 => sig1);<br />
-- instantiation of the 2nd xor instance unit2: xor2<br />
port map (i1 => a(2), i2 => sig1, o1 => sig2);<br />
---instantiation of inverter unit3: not1<br />
port map (i1 => sig2, o1 => even);<br />
end str_arch;
Reference<br />
• Pong P. Chu, “ RTL Hardware Design Using VHDL”.<br />
• Charles H. Roth Jr., Larry L. Kinney, “Fundamentals of<br />
Logic Design”.