Fractional Dual-Modulus Prescaler with Regenerative Divider

The 13th IEEE International Symposium on Consumer Electronics (ISCE2009)
Fractional Dual-Modulus Prescaler with
Regenerative Divider
Yue-Fang Kuo and Ro-Min Weng
Dept. of Electrical Engineering,
National Dong Hwa University,
Hualien 97401, Taiwan, Republic of China
romin@mail.ndhu.edu.tw
Abstract—A fractional dual-modulus prescaler (FDMP) with
regenerative divider for 5 GHz band is presented using 0.13 µm
CMOS technology. It provides a solution to generate a dualmodulus
fractional division ratio which keeps up with high
operation frequency from a voltage-controlled oscillator. The
maximum operation frequency of FDMP is 6.3 GHz consuming
6.75 mW at 1.2 V supply voltage. The proposed FDMP achieves
both high operation frequency and large output swing of the
quadrature outputs.
f REF
Phase
Frequency
Detector
Q
R
S
Charge
Pump
Pulse (N P )
Counter
Sallower (N S )
Counter
Loop Filter
Dual-Modulus
Prescaler
N A /N A +1
Modulus
Control
VCO
f VCO,I
f VCO,Q
f VCO
Keywords-Fractional Dual-Modulus Prescaler; Regenerative
Divider; Miller Divider.
I. INTRODUCTION
A dual-modulus prescaler (DMP) is a key block of a
frequency divider in a frequency synthesizer. The division
number of a pulse-swallower divider is decided by DMP. To
keep up with high frequency output from a voltage-controlled
oscillator (VCO) and to reduce the power consumption, there is
a trade-off between the speed and the divide-by-N of DMP.
Commonly, a fixed-ratio prescaler is inserted between DMP
and VCO in order to relax the speed constraint of DMP [1].
However, the channel spacing becomes large and resolution is
decreased by this solution. For maintaining the same channel
spacing, the reference frequency f REF is required to be reduced
by a factor of the fixed-ratio. Low reference frequency results
in decreasing the useful bandwidth of a phase-locked loop
(PLL). This solution increases the settling time and decreases
phase noise performance. In this work, a new dual-modulus
prescaler based on regenerative divider is introduced to solve
the above problems and to achieve high operating frequency
with the fractional division ratio.
II.
CIRCUIT DESIGN
Fig. 1 depicts a frequency synthesizer based on a proposed
fractional dual-modulus prescaler (FDMP) and a pulse
swallower counter without employing a fixed-ratio prescaler.
The output of FDMP is counted by the pulse swallower counter
simultaneously. The division ratio of FDMP is changed by an
S-R flip-flop which enables each state by generating variable
swallow pulses from a pulse swallower divider. Therefore, the
synthesized frequency f VCO is equal to
VCO
( N A
N P
N S
) f REF
f = + , (1)
TABLE I.
f REF
(MHz)
Divider
Figure 1. Architecture of the frequency synthesizer.
SPECIFICATION OF THE PULSE SWALLOWER DIVIDER FOR
DIFFERENT CHANNEL SPACING AND N A OF 3.5
N P N S M = 3.5N P + N S
Channel
Spacing
(MHz)
Channel
Numbers
20 70 5-55 250-300 20 51
10 142 3-103 500-600 10 101
7 204 3-143 717-857 7 141
3.5 408 1-286 1429-1714 3.5 286
1.75 816 2-573 2858-3429 1.75 572
where N P is the number of the pulses into each reference period
of FDMP, N S is the number of the swallowed pulses per
reference period, and N A is the division ratio of FDMP. For
5GHz unlicensed band such as Wireless LAN and WiMAX
[2][3], Table I shows the division number M of the pulse
swallower counter with different reference frequency and N A of
3.5. According to (1), the synthesized frequency can be
covered between 5 GHz to and GHz with difference channel
spacing. Therefore, FDMP can be applied to different system
specifications without using a fixed-ratio prescaler for various
channel spacing.
Fig. 2 shows the principle of FDMP with regenerative
frequency divider, which consists of a single sideband (SSB)
mixer with LC-tank, two divide-by-2 dividers, and a dual-mode
divide-by-2 divider [4]. The differential output of SSB mixer is
obtained by the difference combination of two double sideband
(DSB) mixers [5]. The switching pairs of an SSB mixer are
connected to the quadrature outputs of a dual-mode divide-by-2
divider which provides two opposite phase sequences. The up-
978-1-4244-2976-9/09/$25.00 ©2009 IEEE 495

SSB Mixer
DOWN
Conversion
UP
Conversion
Voltage
Controlled
Oscillator
f VCO,I
f VCO,Q
DSB
Mixer1
+
+
2 N f VCO
2 N +1
C
2
2L
2 N f VCO
2 N -1
+
f out1
-
f out4,I
2 N f VCO
LC-Tank
2 N + 1
f out4,Q
Divider
1/2
+
f out2
-
2 N -1 f VCO
2 N + 1
N = 3
Divider
1/2
+
f out3
-
2 N -2 f VCO
2 N + 1
Dual-Mode
Divider
1/2
DSB
Mixer2
2 N -3 f VCO
2 N + 1
Figure 2. Principle of FDMP.
V DD
LC-Tank
L
L
Mode
C
C
f out1
+
f VCO,I
-
DFF1
D Q
DFF2
D Q
M 1 M 2 M 3 M 4
M 7 M 8 M 9 M 10
f MCML
out2
f out3
D Q D Q
Divide-by-2
CK CK CK CK
M 5 R M 6 M 11 M 12
1
R +
2
f VCO,Q
-
MCML Divide-by-2
I S I S
I S
I S
Mode = 1
CW
DSB Mixer2
DSB Mixer1
M 34 M 35 M 36
t
f out4,I1
f out4,Q2,270 f out4,Q1,90
f out4,I2 f
f out4,I1,0 out4,Q1
f
Mode = 0
out4,Q2 CCW
M 13 M 14 M 15 M 16 M 17 M 18 M 19 M 20 M 21 M 22 M 23 M 24
t
M 25 M 26 M 27
M 28 M 29 M 30 f out4,Q1,270 f out4,Q2,90
f out4,I1,0
Mode
M 31 M 32
M 33
V DD
Mode
I SS
Dual-Mode Divide-by-2 Divider
conversion or down-conversion output of an SSB mixer can be
obtained by choosing different quadrature phase to tune the
LC-tank load. When center frequency of the resonant LC-tank
is around (2 N f VCO )/(2 N -1), the SSB mixer generates the upconversion
and suppresses the down-sideband. The
regenerative modulation of the input sinusoidal signal is
generated from f VCO to (2 N-3 f VCO )/(2 N -1). The output frequency
of FDMP will be succeed to achieve the differential output
frequency, f OUT = (1/3.5) f VCO , when N is equal to 3. Assuming
that the resonant LC-tank tunes the center frequency from
(2 N f VCO )/(2 N -1) to (2 N f VCO )/(2 N +1) at the output of the SSB
mixer. In additional, the dual-mode divider changes the
opposite quadrature phase at the frequency of (2 N-3 f VCO )/(2 N +1).
Then, the up-sideband suppression can be increased where
FDMP is divided by 4.5.
A Gilbert double-balanced DSB mixer is used for
providing the quadrature inputs of the SSB mixer which
accomplish addition and subtraction of frequency, as shown in
Fig. 3. The resonant LC-tank composes of a symmetric shared
inductor with centre-tap and two switched capacitors. The
linearity and flat voltage gain can be improved during the
Figure 3. Schematic of proposed FDMP
desired division ratio of FDMP. For high-frequency operation
of the SSB mixer, its output is halved by a divide-by-2 divider
with MOS current mode logic (MCML) circuits which
achieves both low phase noise and wide operating frequency
range of (2 N+1 f VCO )/(2 2N -1) [6]. The schematic of the dual-mode
divide-by-2 divider is introduced by Lee [7]. Two phase
patterns of both clockwise and counterclockwise sequences are
provided. According to the pattern selection switch signal
Mode, the tail current of transistor M 31 (M 32 ) steers the MCML
circuits and controls different phases transferring to the output
ports.
III.
SIMULATION RESULT
The proposed regenerative frequency divider is simulated
with 0.13 µm CMOS process parameters at 1.2 V power
supply. Fig. 4 shows the output signal of the proposed divider
with an input 200 mV peak-to-peak voltage of 6 GHz
operating frequency. It is obvious that the input signal of a
divide-by-4.5 state has one more delay than that of a divideby-3.5
state. Fig. 5 shows the sensitivity curves of the
proposed divider in two different division ratios. The results
496

show that the proposed divider achieves large output swing
with small input signal between 5 GHz and 6 GHz. The
operating range of FDMP is limited by the center frequency of
the resonant LC-tank. With 6 GHz input signal, the output
spectrum of SSB mixer shows Fig. 6. In Fig. 6(a), the SSB
mixer generates a down-conversion signal of 6.855 GHz and
suppresses both 3.43 GHz and 10.28 GHz below 30dB. The
sideband around 2.668 GHz and 8 GHz are at least 25dB lower
than output of SSB mixer at 5.335 GHz, as shown in Fig. 6(b).
The input signal of VCO and the sideband signal are
effectively suppressed by the resonant LC-tank. The power
consumption within the operating frequency band is less than
6.75 mW.
IV.
CONCLUSION
A novel fractional dual-modulus precsaler with
regenerative divider is presented. The proposed presclaer
provides a dual-modulus fractional division ratio for keeping
up with high operation frequency under a small input voltage
swing. The simulated results prove that the proposed prescaler
achieves high operation frequency with a large output swing.
The designed prescaler can be further applied to the frequency
dividers for high speed systems.
1.6
1.4
1.2
Divide-by-3.5
Divide-by-4.5
fvco
fout3
Mode
ACKNOWLEDGMENT
The tsmc 0.13µm CMOS process parameters for this work
are supported by the National Chip Implementation Center
(CIC) of the National Applied Research Laboratories, Taiwan.
REFERENCES
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[5] Y. F. Kuo and R. M. Weng, “Regenerative Frequency Divider for 14
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Jan. 2008.
[6] X. P. Yu, M. A. Do, J. G. Ma, K. S. Yeo, R. Wu, and G. Q. Yan, “1V
10GHz CMOS Frequency Divider with Low Power Consumption,”
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0
1.0
-20
voltage, V
0.8
0.6
0.4
Power, dBm
-40
-60
0.2
-80
0.0
28.0 28.5 29.0 29.5 30.0 30.5 31.0 31.5 32.0 32.5 33.0
time, ns
-100
0 2 4 6 8 10 12 14
Frequency, GHz
Figure 4. Output waveforms of FDMP.
0
(a)
minmum input peak-to-peak voltage, V
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
-0.1
4.0 4.4 4.8 5.2 5.6 6.0 6.4 6.8 7.2 7.6
operating frequency, GHz
Divide-by-3.5
Divide-by-4.5
1.11
1.10
1.09
1.08
1.07
1.06
1.05
1.04
1.03
1.02
1.01
output peak-to-peak voltage, V
Power, dBm
-20
-40
-60
-80
-100
0 2 4 6 8 10 12 14
Frequency, GHz
(b)
Figure 6. Output spectrum of SSB mixer with (a) divide-by-3.5 and (b)
divide-by-4.5 mode.
Figure 5. Sensitivity simulation for each operation frequency.
497