National Level Workshop on VLSI, MEMS ... - VIT University

Address for Correspondence
Dr. A. Ravi Sankar, Prof. / SENSE,
Prof. Augusta Sophy, Asst. Prof. / SENSE,
VIT University (Chennai Campus),
Vandalur – Kelambakkam Road,
Chennai – 600 048.
Telefax : (044) 3993 2555
Telephone: (044) 3993 1274/43
Email: ravisankar.a@vit.ac.in, augustasophyt.t@vit.ac.in
Facilitators
1. Prof. M Kalyan Chakravarti, AP/SENSE (8148736577)
2. Prof. Reena, AP/SENSE (9840837624)
3. Prof. Rani Alex, ACP/SENSE (9094908549)
Target Participants
Faculty members, Research Scholars and graduate students
from Engineering Institutions and participants from Industry.
Registration Fee
Faculty/Industry participants: Rs. 1000/ -
Research Scholars/ students: Rs. 700/-
Registration fee includes registration kit, lunch and
refreshment for both the days. Local accommodation will be
provided based on request by mail/phone atleast a week
before the event at nominal cost.
Payment Mode
The Registration form in the prescribed format, along with
non-refundable DD drawn in favour of “VIT University,
Chennai Campus”, payable at Chennai, to be sent to the
above mentioned contact address on or before 30 Nov. 2011.
Important Dates
Last date for registration : 06-12-2011
Duration of program : 09 th & 10 th Dec. 2011
Objective of the Program
The objective of the workshop is to bring people engaged in
teaching, research, industries and education together to
enhance their knowledge level in the fields of VLSI, MEMS
and their Integration. Eminent resource persons from
academia and industries will share and disseminate scientific
knowledge and design methodologies, which will help the
participants to set new millstones in the above mentioned
fields of research for their pursuit.
The FDP program will mainly focus on the following
parameters:
a) Frontend and backend design of VLSI circuits
b) Digital IC design flow using Mentor EDA tool flow
c) Functional Verification Synthesis, simulation
mismatches - a study using Modelsim, Leonardo
Spectrum and precision RTL
d) Comparison between ASIC and FPGA synthesis flow
e) Focus on backend design flow with relevant details
on physical design & verification
f) Overview of parasitic extraction and back annotation
g) Process modeling and electromechanical design
MEMS and Micro-sensors
h) Multi-physics analysis and system level modeling of
MEMS and Micro-sensors
Program Highlights
Lectures by academics and researchers from reputed
institutions, such as IISc, and IIT Madras, VIT Chennai
Campus, followed by presentations, demonstrations and
hands-on training by the EDA Tool vendors.
Day 1
Session I Lecture by Dr Navakantha Bhat, Prof.,
Department of ECE, IISc, Bangalore
Session II Concepts of Full custom & semicustom IC
Design flow
Session III
Overview of Netlist to GDS flow
Session IV - Hands-on session on schematic and layout
simulations - Concepts of physical verification –LVS
checks
- Physical Verification using Calibre & Post Layout
Simulation using ELDO
Day 2
Session I Mentor Graphics Tools - Concepts of parasitic
extraction and back annotation
Session II MEMS Design Flow using Intellisuite
Session III Process simulation - 3D Builder – Case Study
– Pressure/Acceleration Sensor – Simulation
<strong>National</strong> <strong>Level</strong> <strong>Workshop</strong> on
VLSI, MEMS & INTEGRATION
December 09-10, 2011
REGISTRATION FORM
Name :............................................................
Designation :............................................................
Department :............................................................
Address : ...........................................................
: ...........................................................
: ...........................................................
Mobile No :............................................................
Email ID :............................................................
Payment Details
DD No.: …………………. ..........................................
Date: ………………
Amount Rs.: ……………..
Bank: ……………………..
Signature & Date

VIT University - Chennai Campus
VIT University has made a mark in the field of higher
education in India during the past 25 years, imparting quality
education in a cross-cultural ambience, intertwined with
extensive application oriented research. VIT has secured the
8th position (India Today 2010) among the Engineering
Institutions in India. It was established by the well-known
educationalist and former Parliamentarian, Dr.G.Viswanathan,
Founder and Chancellor. Being a visionary, he transformed
VIT into a Center of Excellence in higher technical education.
His dream has materialized further as the new campus at the
heart of the Chennai City, as VIT University, Chennai Campus
(VIT-CC). Spearheaded by Mr. G. V. Selvam, Vice President,
the institution is making leaps and bounds in professional
programs. The Vice President has a mission to make this
institution a global center with the latest learning facilities. Dr.
V. Raju, former Professor of State University of New York,
USA, currently the Vice Chancellor, strives to internationalize
the educational standards. Dr. Anand A. Samuel, Pro-Vice
Chancellor leads the team in Chennai with the following
objectives:
• To maximize Industrial Connectivity and create Centers of
Excellence in niche areas of research
•To enrich Technological and Managerial Human Capital
nurtured in a multicultural ambience
• To provide a platform for the agglomeration of ideas of
personnel from various walks of life for learning enrichment
• To create opportunities and exploit the available resources
to benefit industry /society
• To encourage participation in the <strong>National</strong> Agenda of
knowledge building
• To foster International collaborations for mutual benefits in
all frontier areas of research.
The School
The School of Electronics Engineering at VIT University was
established for imparting a state-of the- art education, training
and research in the field of Electronics and Communication
Engineering and allied areas. It offers B.Tech., and Ph. D.
Programmes in the domain of Electronics and
Communication Engineering. The expertise of the faculty
members include VLSI, Optical Communication, Image and
Signal Processing and all frontier areas.
Mentor Graphics
Mentor Graphics® provides
software and hardware
design solutions enabling
companies to develop faster and efficient electronic products
more cost-effectively. It helps engineers in overcoming the
design challenges in the increasingly complex worlds of board
and SoC designs.
CoreEL Technologies
CoreEL echnologies is a technology company with
businesses spread across design services & product
development, distribution and training. Head Quartered in
Bangalore, India, CoreEL is a leading provider of VLSI &
Embedded System design services and Intellectual Property.
Its Services offerings include Distribution of Silicon solutions,
EDA tools, COTS products, Engineering Services (Turn Key
Systems Design, Turn Key FPGA Design and High Speed
PCB Design), Education and Manufacturing.
Sponsored by
TMI Systems
And
<strong>National</strong> <strong>Level</strong> <strong>Workshop</strong> on
VLSI, MEMS & INTEGRATION
December 09-10, 2011
CO-ORDINATORS
Dr. V.S. Kanchana Bhaaskaran, Prof. / ECE
Dr. A. Ravisankar Prof. / ECE
Organized by
VIT University (Chennai Campus)
School of Electronics Engineering
Vandalur – Kelambakkam Road,
Chennai 600048
Telefax : (044) 3993 2555
Telephone: (044) 3993 1274/43
www.vit.ac.in