A robust feedforward compensation scheme for multistage ...

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 2, FEBRUARY 2003 237 

A Robust Feedforward Compensation Scheme for 

Multistage Operational Transconductance Amplifiers 

With No Miller Capacitors 

Bharath Kumar Thandri and José Silva-Martínez, Senior Member, IEEE 

Abstract—A multistage operational transconductance amplifier 

with a feedforward compensation scheme which does not use 

Miller capacitors is introduced. The compensation scheme uses 

the positive phase shift of left-half-plane (LHP) zeroes caused 

by the feedforward path to cancel the negative phase shift of 

poles to achieve a good phase margin. A two-stage path increases 

further the low frequency gain while a feedforward single-stage 

amplifier makes the circuit faster. The amplifier bandwidth is 

not compromised by the absence of the traditional pole-splitting 

effect of Miller compensation, resulting in a high-gain wide-band 

amplifier. The capacitors of a capacitive amplifier using the 

proposed techniques can be varied more than a decade without 

significant settling time degradation. Experimental results for 

a prototype fabricated in AMI 0.5- m CMOS process show dc 

gain of around 90 dB and a 1% settling time of 15 ns for a load 

capacitor of 12 pF. The power supply used is 1.25 V. 

Index Terms—Analog circuits, feedforward techniques, multistage 

amplifiers, operational transconductance amplifiers (OTA), 

phase compensation. 

Fig. 1. 

Typical OTA-based capacitor amplifier. 

I. INTRODUCTION 

THE EVER-INCREASING demand for more performance 

from monolithic analog and mixed-mode signal-processing 

circuits poses challenging requirements on the basic 

building block: the operational transconductance amplifier 

(OTA). High-end applications such as analog-to-digital (A/D) 

converters and switched-capacitor filters require fast settling 

and precise amplifiers. The step response of a capacitive loaded 

amplifier, shown in Fig. 1, consists of two phases, the initial 

slew phase and the settling phase. The latter phase is determined 

by the gain-bandwidth product ( of the amplifier and, 

in many practical cases, dominates the overall settling time. If 

the slew phase is neglected, the amplifier’s pulse response is 

approximately given by 

In this expression, the effective unity-gain frequency is given by 

Manuscript received April 16, 2002; revised August 23, 2002. 

The authors are with the Analog and Mixed-Signal Center, Department 

of Electrical Engineering, Texas A&M University, College Station, TX 

77843-3128 USA (e-mail: jsilva@ee.tamu.edu). 

Digital Object Identifier 10.1109/JSSC.2002.807410 

(1) 

(2) 

Fig. 2. 

Step response of an amplifier with sufficient phase margin. 

In these equations, 

is the ideal amplifier gain, 

is the feedback factor and 

is the open-loop dc gain of the amplifier. The error in the final 

value is inversely proportional to the dc gain of the amplifier, 

as shown in Fig. 2. A high-performance amplifier should have 

high (for fast settling) and high dc gain (for an accurate 

final value). It is very difficult to design an amplifier with 

both high gain and high bandwidth because of contradicting design 

requirements. High-gain amplifiers use multistage designs 

with long channel length transistors biased at low current levels. 

High-bandwidth amplifiers use single-stage designs with short 

channel length transistors biased at high current levels [1]. Cascading 

individual gain stages gives a high-gain amplifier, but 

each stage introduces a low-frequency pole, which produces 

negative phase shift and degrades the overall phase margin. The 

phase margin of the open-loop amplifier should be at least 45 

for stable operation in closed loop. Many phase-compensation 

schemes for multistage amplifiers have been reported in the literature 

[2]–[7]. These reported schemes are a variation of the 

basic Miller compensation scheme for a two-stage amplifier. In 

0018-9200/03$17.00 © 2003 IEEE

238 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 2, FEBRUARY 2003 

Fig. 3. 

Block diagram of basic NCFF compensation scheme for two-stage amplifier. 

a Miller compensated amplifier, the dominant pole is pushed to 

lower frequencies due to the Miller effect (pole splitting), resulting 

in lower bandwidth structures. Also, a right-half-plane 

(RHP) zero is created which degrades the phase response. A 

nulling resistor is usually used to cancel the effect of the RHP 

zero. Other reported schemes use the positive phase shift of a 

left-half-plane (LHP) zero created by a feedforward path to improve 

the phase response [2], [4], but all of these still use Miller 

capacitors. Recently, active feedforward techniques have been 

used for the design of multistage amplifiers. In [11], a theoretical 

analysis on the effects of feedforward networks is presented, and 

in [12], the technique is used for the design of low-frequency instrumentation 

amplifiers. 

The compensation scheme used in this paper employs a feedforward 

path to create LHP zeros, but does not use any Miller 

capacitor. The dominant pole is not pushed to lower frequencies, 

resulting in a higher gain-bandwidth product with a fast 

step response. The proposed compensation scheme is described 

in Section II. The effects of pole–zero mismatch on the performance 

of the amplifier are discussed in Section III. It is shown 

that the proposed technique is robust even if the integrating and 

load capacitors are varied by more than a decade. Section IV 

describes the circuit implementation. The simulation and experimental 

results are discussed in Section V, and conclusions are 

drawn in Section VI. 

(a) 

(b) 

Fig. 4. Amplifier frequency response and pole–zero locations in open and 

closed loop. (a) Perfect pole–zero cancellation. (b) Pole–zero mismatch. 

II. NO-CAPACITOR FEEDFORWARD (NCFF) COMPENSATION 

SCHEME FOR MULTISTAGE AMPLIFIERS 

stages have a common pole at 

amplifier voltage gain is 

. The overall 

The proposed NCFF compensation scheme alleviates the 

drawbacks of Miller compensation schemes. The block diagram 

of the NCFF scheme is shown in Fig. 3. The compensation 

scheme uses the positive phase shift of LHP zeros, created by 

a feedforward path, to compensate the negative phase shift due 

to the poles. The pole–zero pair is created at high frequencies 

to avoid slow settling components associated with pole–zero 

cancellation at low frequencies [8]. The main concept can be 

explained by assuming a single-pole response for the three 

blocks. , , and are the dc gains of the first, second, 

and feedforward stages of the amplifier. The pole of the first 

stage is located at 

and the second and third 

The OTA transfer function has two poles and a LHP zero created 

by the feedforward path. The dc gain is given by 

(3)

THANDRI AND SILVA-MARTÍNEZ: ROBUST FEEDFORWARD COMPENSATION SCHEME FOR MULTISTAGE OTAS WITH NO MILLER CAPACITORS 239 

Fig. 5. 

NCFF compensation scheme for n-stage amplifier. 

and the dominant pole is located at 

zero is 

. The location of the LHP 

Notice that the location of the LHP zero is approximately at 

times the gain-bandwidth product of the first stage, where 

. The second and feedforward stages can be designed 

such that the negative phase shift due to is compensated by 

the positive phase shift of the LHP zero. When the frequency of 

exactly coincides with that of the LHP zero, the amplifier 

phase margin is 90 and the unity-gain frequency is given by 

. The open- and closed-loop transfer 

functions for perfect and imperfect pole–zero cancellation are 

shown in Fig. 4(a) and (b), respectively. The implications of 

pole–zero mismatch are discussed in Section III. 

This compensation scheme results in an amplifier with high 

gain and fast response. The bandwidth improvement is due to 

the fact that the poles are not split, as is the case in any amplifier 

with Miller compensation. There can be a substantial reduction 

in area and power, especially as compared to multistage 

amplifiers, which use two or more capacitors for phase compensation. 

If the nondominant pole of the first stage is also considered, 

then the resulting transfer function has three poles and two 

LHP zeros. In general, the number of LHP zeros created by the 

feedforward path is equal to the order of the first stage. The main 

restriction here is that the nondominant pole of the feedforward 

and second stage must be placed after the overall unity-gain 

bandwidth of the amplifier in order to minimize phase degradation. 

This compensation scheme can be extended for a generic 

-stage amplifier, as shown in Fig. 5. 

III. OPTIMIZATION OF CLOSED-LOOP RESPONSE 

The OTA is commonly used in closed-loop configuration with 

feedback capacitors as shown in Fig. 1. Imperfect pole–zero 

cancellation results in a pole–zero doublet that might affect the 

(4) 

performance of the amplifier. The transconductances of individual 

gain stages should be selected properly to alleviate this 

drawback, as shown in the following discussion. 

It has already been shown that a pole–zero doublet may 

degrade the settling time according to the pole–zero spacing 

and the zero’s frequency [8]. The closed-loop transfer function 

of a capacitive amplifier is affected by the feedback factor, 

as shown in (1) and (2). Usually, an amplifier with open-loop 

phase margin of around 60 –70 gives the fastest step response 

for the overall amplifier [9], [10]. However, the capacitive 

amplifier’s pulse response in the presence of a pole–zero 

doublet is more complex. Let us now consider the capacitive 

amplifier shown in Fig. 1 using the proposed OTA. By using 

typical circuit analysis techniques, it can be shown that the 

overall closed-loop transfer function is 

The zero and poles are given by 

where and are the effective 

OTA load capacitor and first-stage load capacitor (see Figs. 1 

and 3), respectively. The parameter 

is the feedback factor, and 

Notice that 

(5) 

(6) 

(7) 

(8) 

is the OTA output conductance. 

, and that real poles are obtained if 

. In (5), it is assumed 

that the frequency of the RHP zero due to gate–drain capacitors 

is placed at very high frequency, which is usually the case, and


its effects can be neglected. For the sake of simplicity, other 

parasitic poles are not considered. If , the closed-loop 

amplifier pulse response can be obtained from (5) as 

(9) 

Low-frequency pole–zero pair degrades the settling-time performance 

and the slow-settling components can be avoided if 

the cancellation occurs at high frequencies. If and are not 

close to each other, dominates the speed of the system. For 

0.1% accuracy in the final value, a settling time of around s 

is required. If is around , then a settling time of around 

s is enough. Notice in (9) that the slowest component is 

associated with the closed-loop dominant pole , therefore it 

is important to match the frequency of the zero with this pole in 

order to minimize the settling time. If the amplifier is designed 

such that 

, the zero 

and poles are approximately located at the following frequencies: 

(10) 

Fig. 6. 

Single-ended amplifier with NCFF compensation scheme. 

TABLE I 

TRANSISTOR DIMENSIONS AND BIAS CURRENTS 

(11) 

(12) 

This condition guarantees that and are close to each 

other, regardless of the absolute value of capacitors used. This 

condition is illustrated in Fig. 4(b). It is worth mentioning 

that reducing the parasitic capacitors at the output of the first 

stage increases the frequency of both and and 

the pole–zero cancellation occurs at high frequencies. If the 

zero cancels the dominant pole, the speed of the amplifier 

is determined by the highest frequency pole— . Typical 

process parameter variations and different load conditions are 

such that the pole locations can change by a factor of two 

or three, but the mismatch between the dominant pole and 

the zero is much less than that, especially if the condition 

is satisfied. Another 

important point to be noted is that complex poles may appear 

for large load capacitors . 

IV. CIRCUIT REALIZATION 

The two-stage amplifier using the NCFF compensation 

scheme has the following design considerations. 

1) The second and feedforward stage should not have any 

nondominant pole before the overall . 

2) The pole–zero cancellation should occur at high frequencies 

for best settling-time performance. 

3) The overall amplifier’s dc gain should be high. 

These conditions can be met if the stages are chosen as 

follows. The first stage can be designed to have a high gain 

and small load capacitance. The second and feedforward stages 

should be optimized for high bandwidth and medium gain performance. 

The schematic of the single-ended amplifier using 

the NCFF compensation scheme is shown in Fig. 6. The first 

stage (M1, M4, M5, M6) is a telescopic amplifier with high dc 

gain. The second (M2, M7) and feedforward stages (M3, M7) 

are single-ended differential amplifiers. Equations (13)–(17) 

show the dc gain of the three stages, internal capacitor (load 

capacitor of first stage), and output conductance. 

(13) 

(14) 

(15) 

(16) 

(17) 

The design strategy is to place the LHP zero and the closed-loop 

dominant pole, which are given by (10) and (11), at the same 

frequency. The bias currents and aspect ratios of the second 

and feedforward stage are adjusted such that 

. The transistor dimensions and bias currents are given 

in Table I. The amplifier was designed in AMI 0.5- m technology 

with a power supply of 1.25 V. Power-supply voltages 

of 0–2.5 V can also be used if the proper common-mode


(a) 

Fig. 8. 

OTA pulse response in noninverting unity-gain (buffer) configuration. 

(b) 

Fig. 7. Open-loop ac response of the OTA. (a) Magnitude response. (b) Phase 

response. 

level (1.25 V) is generated. In the technology used, the typical 

threshold voltage of an nMOS transistor is 700 mV and 

for a pMOS transistor is 900 mV. The first stage of the amplifier 

(telescopic cascode) was designed for maximum gain 

performance and relatively small time constant ( 

pF/700 AV ns). The swing of the first stage need 

not be high (it is typically in the order of a few millivolts) as it is 

amplified further by the gain of the second stage. The dc bias of 

transistor M1 is at ground and the dc bias for M4 and M5 are set 

by a bias circuit. The transconductance of the second and feedforward 

stage is increased as much as possible to push the poles 

to high frequencies: mA/V and mA/V. 

Since the values of the first pole and the LHP zero depend on 

parasitic capacitances and the feedback factor, exact cancellation 

may not be possible; however, the effect of the pole–zero 

mismatch is small because the partial cancellation occurs at high 

frequencies. 

This structure is well suited for fully differential implementation, 

where the reduced number of parasitic poles (due to the 

absence of differential to single-ended conversions) makes the 

structure faster. In this case, additional common-mode feedback 

circuits have to be added for both the first and second stage to 

control the common-mode voltages. 

V. EXPERIMENTAL AND SIMULATION RESULTS 

The simulated open-loop ac magnitude and phase response 

of the single-ended OTA is shown in Fig. 7(a) and (b), respec- 

Fig. 9. Pulse response post-layout simulation—parametric sweep of feedback 

and load capacitors. 

Fig. 10. 

Microphotograph of the OTA. 

tively. The load capacitor used in the simulations was 8 pF 

and the design was optimized for this loading. The OTA dc 

gain, unity-gain frequency, and phase margin are around 94 dB, 

300 MHz, and 74 , respectively. The OTA pulse response for 

a noninverting unity-gain configuration (buffer configuration) 

loaded by a capacitor of 8 pF is shown in Fig. 8. An input step 

of 400 mV and 100-ps rise time was used for the simulations, 

and 1% settling time is less than 7 ns. Parametric sweep simulations 

for the capacitive amplifier with 

(see


Fig. 13. 

Measured pulse response for large input signal. 

Fig. 11. Experimental results for the single-ended amplifier. Input step (falling 

edge) signal and amplifier response. 

TABLE II 

POST-LAYOUT SIMULATION AND EXPERIMENTAL RESULTS 

WITH LOAD CAPACITOR OF 12 pF 

*Due to noise limitations, 0.1% settling time was difficult to measure properly. 

Fig. 12. Post-layout simulation results for the capacitive amplifier. Pulse 

response with a real input signal, including all parasitic capacitors. 1% settling 

time is around 14 ns. 

Fig. 1 for the identification of the capacitors) are shown in Fig. 9. 

The values used for the capacitors are 0.25, 0.5, 1, 3, 7, and 

10 pF. The amplifier’s output represents the typical exponential 

behavior of an underdamped system and the phase margin is always 

greater than 45 . The 1% settling time is 2.4 and 8 ns for 

capacitors of 0.25 and 10 pF, respectively, when the input step 

had a fall time of 100 ps. The feedback and loop gain factors 

are reduced if the parasitic capacitors are comparable with the 

main capacitors, and the parasitic poles and the RHP zero cannot 

be neglected because they are comparable with . These poles 

and zeros introduce negative excess phase, reducing the phase 

margin. A small overshoot appears in the pulse response of the 

amplifier for small capacitors of less than 3 pF, which can be observed 

in Fig. 9. Also, the effects of the drain–gate capacitor of 

transistor M3 are evident in these simulations. increases 

the effective feedback capacitor and this effect can be avoided 

if cascode amplifier is used in the feedforward stage. 

The single-ended amplifier was fabricated in the AMI 

0.5- m technology through the MOSIS Educational program. 

The chip microphotograph is shown in Fig. 10. The active area 

for the amplifier is around 0.16 mm . An inverting capacitive 

amplifier, similar to the one shown in Fig. 1, was used for 

measuring the OTA pulse response. For the test setup, external 

capacitors of 5 pF were employed and the load capacitance 

was 12 pF (estimated capacitance of measurement equipment 

probe capacitance and package bond-pad capacitance). The 

pulse response of the fabricated OTA was measured and is 

shown in Fig. 11. The 1% settling time for an input step of 

0.7 V was 15 ns—around 8 ns corresponds to slew-rate phase 

and 7 ns are associated with the settling phase limited by the 

effective gain–bandwidth product. For these results, the input 

edge had a fall time of around 3 ns. It was difficult to obtain 

a better step input due to the printed circuit board (PCB), 

bond-pad parasitics (DIP-40 package was used), and equipment 

loading effects. The output step response has no ringing, which 

shows a good phase margin. Post-layout simulation result for 

the amplifier is shown in Fig. 12, with a 3-ns fall-time input 

step. The feedback and load capacitors are similar to the ones 

indicated in the measurement setup. The 1% settling time is 

around 14 ns, which is in conformance with the measured 

results. The 0.1% settling time is around 20 ns. Monte Carlo 

simulations including 1% transistor mismatches have shown 

almost no effect on the speed of the amplifier. 

The ac voltage at the noninverting terminal was very small, 

even below the noise level. From measurements, the dc gain was 

estimated to be around 90 dB. The OTA pulse response for large 

input signals (up to 1 V) is shown in Fig. 13 and most of the 

settling time is due to slew-rate limitation. The input-referred 

noise density is around 10.3 nV/Hz . and gain


transfer functions are around 6 and 10 dB at low frequencies, 

respectively. Post-layout simulation and experimental results 

for the single-ended amplifier using integrating and feedback 

capacitors of 5 pF are compared in Table II. 

CONCLUSION 

A compensation scheme for multistage amplifiers with no 

Miller capacitors was proposed. This scheme uses positive 

phase shift of LHP zeros created by the feedforward path 

to cancel the negative phase shift of the poles (closed-loop 

dominant pole). A single-ended amplifier using the proposed 

NCFF compensation scheme was designed and fabricated in 

AMI 0.5- m technology. The amplifier combines high gain, 

high gain bandwidth, and good phase margin. Pulse response 

shows that the phase margin is better than 45 for capacitors in 

the range of 0.25–10 pF. The effect of pole–zero mismatch on 

the amplifier performance was studied and it was shown that 

the pole–zero cancellation should occur at high frequencies 

for best settling-time performance. Experimental results of the 

OTA show fast settling time and good stability. 

[11] M. Schlarmann, E. Lee, and R. Geiger, “A new multipath amplifier design 

technique for enhancing gain and bandwidth,” in Proc. IEEE Int. 

Symp. Circuits and Systems, vol. II, June 1999, pp. 610–615. 

[12] A. Thomsen, “A five-stage chopper stabilized instrumentation amplifier 

using feedforward compensation,” in Proc. Symp. VLSI Circuits, Honolulu, 

HI, June 1998, pp. 220–223. 

Bharath Kumar Thandri received the B.E. (Hons) 

degree in computer science from Birla Institute of 

Technology and Science, Pilani, India, in 1998 and 

the M.S. degree in electrical engineering from Texas 

A&M University, College Station, in 2001. 

From 1998 to 1999, he worked in the DSP group of 

Texas Instruments (India) Ltd., Bangalore, where he 

developed software simulators for TI’s C6X range of 

DSPs. He was an Intern in the Computer Peripherals 

and Control Products Group of Texas Instruments, 

Dallas, TX, in the fall of 2000. Since November 2001, 

he has been with Cypress Semiconductors, Austin, TX, where he is working 

on the design of optical communication transceiver ICs and mixed-signal CAD 

flow development. His main research interests are in the area of high-performance 

and high-frequency analog circuits for communication and signal-processing 

ICs. 

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[2] R. Eschauzier and J. H. Huijsing, Frequency Compensation Techniques 

for Low-Power Operational Amplifiers. Boston, MA: Kluwer, 1995. 

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large capacitive load amplifier with damping-factor-control frequency 

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2000. 

[4] F. You, S. H. K. Embabi, and E. Sanchez-Sinencio, “A multistage amplifier 

topology with nested Gm–C compensation for low-voltage application,” 

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[8] Y. B. Kamath, R. G. Meyer, and P. R. Gray, “Relationship between frequency 

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1999. 

José Silva-Martínez (SM’98) was born in 

Tecamachalco, Puebla, México. He received the 

B.S. degree in electronics from the Universidad 

Autónoma de Puebla in 1979, the M.Sc. degree 

from the Instituto Nacional de Astrofísica Optica y 

Electrónica (INAOE), Puebla, in 1981, and the Ph.D. 

degree from the Katholieke Univesiteit Leuven, 

Leuven, Belgium, in 1992. 

From 1981 to 1983, he was with the Department 

of Electrical Engineering, INAOE, where he was 

involved with switched-capacitor circuit design. 

In 1983, he joined the Department of Electrical Engineering, Universidad 

Autónoma de Puebla, where he remained until 1993. He was a cofounder of 

the graduate program on opto-electronics in 1992. From 1985 to 1986, he was 

a Visiting Scholar in the Department of Electrical Engineering, Texas A&M 

University, College Station. In 1993, he rejoined the Department of Electrical 

Engineering, INAOE, and from May 1995 to December 1998, was the Head 

of the Electronics Department. He was a cofounder of the Ph.D. program on 

electronics in 1993. He is currently with the Analog and Mixed Signal Center, 

Department of Electrical Engineering, Texas A&M University, where he is 

an Associate Professor. He is the inaugural holder of the TI Professorship I 

in Analog Engineering, Texas A&M University. His current field of research 

is in the design and fabrication of integrated circuits for communication and 

biomedical application. 

Dr. Silva-Martínez has served as IEEE Circuits and Systems Vice President 

Region 9 (1997–1998), and as Associate Editor for IEEE TRANSACTIONS ON 

CIRCUITS AND SYSTEMS PART II from 1997 to 1998 and May 2002 until the 

present. He was the main organizer of the 1998 and 1999 International IEEE 

Circuits and Systems Tour in region 9, and Chairman of the International Workshop 

on Mixed-Mode IC Design and Applications (1997–1999). He was a corecipient 

of the 1990 European Solid-State Circuits Conference Best Paper Award.

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