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Underfill Flow as Viscous Flow Between Parallel Plates Driven - Profile

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136 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING, AND MANUFACTURING TECHNOLOGY-PART C, VOL. 19, NO. 2, APRIL 1996<br />

Consider the c<strong>as</strong>e where the flip-chip is oriented vertically<br />

such that the underfill flows from top to bottom aided by<br />

the hydrostatic pressure induced by gravity acting on the<br />

underfill. Assuming underfill with a ycose value of 0.015<br />

N/m w<strong>as</strong> used on a chip with a 75 pm standoff (separation<br />

distance), the capillary pressure given by (7) would be 395<br />

Pa. The median hydrostatic pressure generated during the<br />

flow would be pgH/2 where p is the m<strong>as</strong>s density of the<br />

underfill, g = 9.81 m/s2, and H is the chip size. A typical<br />

underfill m<strong>as</strong>s density of 1600 kg/m3 on a 10 mm square<br />

flip-chip would generate a median hydrostatic pressure of 78<br />

Pa. Since the hydrostatic pressure is only about 1/5 of the<br />

capillary pressure, it is unlikely to significantly enhance the<br />

flow rate, especially when the gap (separation distance) is<br />

small. Vacuum enhancements can generate driving pressures<br />

of up to one atmosphere (lo5 Pa). Since this is more than<br />

250 times the capillary pressure, the vacuum enhancement will<br />

have a significant effect on the flow rate. An example of the<br />

use of vacuum to enhance underfill flow h<strong>as</strong> been demonstrated<br />

by Banerji et al. [21].<br />

V. CONCLUSION<br />

An exact model w<strong>as</strong> developed for understanding the flow<br />

time (t) for qu<strong>as</strong>isteady, laminar flow between parallel<br />

plates driven by capillary action, <strong>as</strong> a function of flow<br />

distance (L), separation distance (h), wetting angle (e),<br />

surface tension (y), and the absolute viscosity (p). The<br />

flow time is given by<br />

The flow time for viscous flow between parallel plates<br />

driven by capillary action is inversely proportional to the<br />

surface tension, separation distance and cosine of the wetting<br />

angle, and directly proportional to the viscosity and<br />

the square of the flow distance. This model agreed well<br />

with experimental results of a typical underfill material<br />

flowing between plates of gl<strong>as</strong>s and ceramic.<br />

The flow rate of an underfill is strongly related to two<br />

underfill material properties: surface tension (y) and<br />

viscosity (p). The quantity<br />

w<strong>as</strong> defined <strong>as</strong> the coescient of planar penetrance (Q)<br />

where 8 is the wetting angle of the underfill to the planes.<br />

The ycos8 term can be determined by me<strong>as</strong>uring the<br />

capillary rise of a progressing meniscus.<br />

This parameter me<strong>as</strong>ures the penetrating power of a<br />

liquid into a gap between parallel plates, and h<strong>as</strong> units<br />

of velocity. This parameter w<strong>as</strong> strongly related to the<br />

temperature of the underfill material.<br />

Gravity will not significantly enhance the flow rate of<br />

underfill materials flowing under flip-chips. Vacuum enhancement,<br />

however, can generate pressures of more than<br />

250 times the capillary pressure, and will effectively<br />

enhance underfill flow rates.<br />

VI. RECOMMENDATIONS<br />

In order to characterize the flow behavior of an underfill<br />

material under a flip-chip, the coeficient of planar<br />

penetrance should be specified at the recommended flow<br />

temperature.<br />

Gravity (inclined or vertical flow) should not be pursued<br />

<strong>as</strong> a method to enhance underfill flow rates. Vacuum<br />

enhancements, however, should be pursued.<br />

This work does not consider the effects of surface roughness,<br />

solder bumps, flux residues, or other obstructions<br />

on the underfill flow. This model also does not consider<br />

non-Newtonian flow behavior. A more complicated model<br />

could be developed to include these factors, however its<br />

usefulness would be limited due to additional complexity.<br />

An empirical approach, b<strong>as</strong>ed on the simple model shown<br />

here, is recommended for optimizing processes including<br />

these other factors.<br />

ACKNOWLEDGMENT<br />

The authors would like to thank L. Powers-Maloney and T.<br />

Og<strong>as</strong>awara for their characterization of the underfill properties,<br />

to C. Avila, M. Evans, J. Glazer, H. Holder, and G. Margaritis<br />

for their editing, encouragement and support, and to J. A.<br />

Emerson for helpful comments on underfill surface tension<br />

values.<br />

REFERENCES<br />

[I] R. R. Tummala and E. J. Rym<strong>as</strong>zewski, Microelectronics Packaging<br />

Handbook. New York: Van Nostrand Reinhold, 1989, pp. 366-391.<br />

[2] K. DeHaven and J. Dietz, “Controlled collapse chip connection<br />

(C4)-An enabling technology,” in Proc. 44th ECTC, 1994, pp. 1-6.<br />

[3] M. Kelly and J. Lau, “Low cost solder bumped flip-chip MCM-L<br />

demonstration,” Circuit World, vol. 21, no. 3, pp. 25-28, Mar. 1995.<br />

[4] B. Wun and J. Lau, “Characterization and evaluation of the underfill<br />

encapsulants for flip chip <strong>as</strong>sembly,” Circuit World, vol. 21, no. 4, pp.<br />

14-17, July 1995.<br />

[5] Y. Tsukada et al., “Reliability and stress analysis of encapsulated flipchip<br />

joint on epoxy b<strong>as</strong>e printed circuit board, advances in electronic<br />

packaging,” in Proc. 1992 Joint ASME/JSME Con$ Eleciron. Packaging,<br />

1992, vol. 2, pp. 827-835.<br />

[6] A. Rai et al., “COB (chip on board) technology: Flip chip bonding onto<br />

ceramic substrates and PWB (printed wiring boards),” in Proc. I990 iat.<br />

Symp. Microelectron. (ISHM), 1990, pp. 474481.<br />

[7] A. Rai et al., “Flip-chip COB technology on PWB,” in Proc. 1MC 1992,<br />

Yokohama, Japan, June 3, 1992, pp. 144-149.<br />

[8] Y. Tsukada et al.> “Surface laminar circuit packaging,” in Proc. 42nd<br />

ECTC, 1992, pp. 22-27.<br />

[9] J. Lau, “Experimental and analytical studies of encapsulated flip-chip<br />

solder bumps on surface laminar circuit boards,” Circuit World, vol. 19,<br />

no. 3, pp. 18-24, 1993.<br />

[lo] J. Kloeser el al., “Low-cost flip-chip bonding on FR-4 boards” Circuit<br />

World, vol. 22, no. 1, pp. 18-21, Oct. 1995.<br />

[ll] F. Nakano et al., “Resin-insertion effect on thermal cycle resistivity of<br />

flip-chip mounted LSI devices,” in Proc. 1987 Int. Symp. Microelectron.<br />

(ISHM), 1987, pp. 536-541.<br />

[I21 D. Suryanarayana et al., “Enhancement of flip-chip fatigue life by<br />

encapsulation,” IEEE Trans. Comp., Packag., Munufact. Technol., vol.<br />

14, no. I, pp. 218-223, Mar. 1991.<br />

[13] D. Suryanarayana et al., “Encapsulants used in flip-chip packages,”<br />

IEEE Trans. Comp., Packag., Manufact. Technol., vol. 16, no. 8, pp.<br />

858-862, Dec. 1993.<br />

[14] D. W. Wang and K. I. Papathom<strong>as</strong>, “Encapsulant for fatigue life<br />

enhancement of controlled collapse chip connection (C4),” IEEE Trans.<br />

Comp., Packag., Manufact. Technol., vol. 16, no. 8, pp. 863-867, Dec.<br />

1993.<br />

[lS] J. Clementi et al., “Flip-Chip encapsulation on ceramic substrates,” in<br />

Proc. 43rd ECTC, 1993, pp. 175-181.

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