Zinc and Tin-Zinc Via-Filling for the Formation of Through ... - KAIST

Journal of ELECTRONIC MATERIALS, Vol. 38, No. 5, 2009
DOI: 10.1007/s11664-008-0646-6
Ó 2009 TMS
Regular Issue Paper
Zinc and Tin-Zinc Via-Filling for the Formation
of Through-Silicon Vias in a System-in-Package
Y.K. JEE, 1 J. YU, 1,3 K.W. PARK, 2 and T.S. OH 2
1.—Center for Electronic Packaging Materials, KAIST, 373-1 Guseong-dong, Yuseong-gu, Daejeon
305-701, Korea. 2.—Material Science and Engineering, Hongik University, 72-1 Sangsu-dong,
Mapo-gu, Seoul 121-791, Korea. 3.—e-mail: jinyu@kaist.ac.kr
Microvias of 50 lm diameter in a Si chip were filled with Zn or Sn-Zn to form
through-silicon vias by means of an electroplating/reflow process or a dipping
method. In the case of the electroplating/reflow process, Zn was electroplated
on a Cu seed layer in via holes, and a reflow was then performed to fill the via
holes with the electroplated Zn. In the case of the dipping method, Zn
via-filling and Sn-Zn via-filling were performed by dipping a via hole specimen
into a molten bath of Zn or Sn-Zn. A filling pressure greater than 3 MPa
during the via-filling is essential for ensuring that the via holes are completely
filled with Zn or Sn-Zn and for preventing voids from being trapped in the
vias. The melting temperature and electrical conductivity of the Sn-Zn alloys
increases almost linearly with the content of Zn, implying that the thermal
and electrical properties of the Sn-Zn vias can be easily controlled by varying
the composition of the Sn-Zn vias. A chip-stack specimen was fabricated by
flip-chip bonding of three chips with Zn vias.
Key words: Chip-stack package, system-in-package, through-silicon via,
Zn via, Sn-Zn via
INTRODUCTION
Recently, a three-dimensional (3D) system in
package (SiP) has been extensively researched for
advanced high-performance mobile devices of small
size and diverse functionality. 1–4 Although wire
bonding has been used for electrical connection
between stacked devices and the circuit board, it is
not an adequate process for high-performance SiPs
of small size and high-frequency characteristics. 1,2
A through-silicon via (TSV) has been recommended
as a new chip-to-chip vertical interconnection technology
for 3D stack packages. 5,6 A TSV, which provides
a shorter interconnection than wire bonding,
can reduce the RC delay and power consumption of
SiPs. TSV formation has been performed with various
methodologies, such as electroplating of Cu and
chemical vapor deposition (CVD) of Cu (or W). 5
However, via-filling with the electroplating of Cu or
(Received July 14, 2008; accepted December 23, 2008;
published online January 13, 2009)
CVD of Cu requires a long process time and a
complicated control of process variables; it may also
cause defects in TSVs, such as voids and pinch-off. 7
The Sn via-filling method consisting of Sn
electroplating and reflow is suggested as a simple
low-cost via-formation technology. 8 However, the
relatively low melting point of Sn (about 232°C) may
limit the application of Sn vias to a 3D stack process
in which multiple reflows are normally conducted
for chip-to-chip bonding; furthermore, the remelting
of Sn during chip-to-chip bonding severely deteriorates
the reliability of the package.
In this study, new via-filling methods, namely the
electroplating/reflow method and the dipping
method of Sn-Zn and Zn vias, were developed for 3D
interconnection technologies. The new methods
complement the disadvantages of Cu via-filling and
Sn via-filling technologies. The melting temperatures
and electrical conductivities of Sn-Zn specimens
were measured to investigate the thermal and
electrical properties of Sn-Zn vias. The effect of the
filling pressure on Zn via-filling was also studied.
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EXPERIMENTAL PROCEDURE
Via holes of 50 lm diameter, 150 lm depth, and
150 lm pitch were formed on a 550-lm-thick p-type
(100) Si wafer by using deep reactive-ion etching.
On the surface of the Si wafer and via holes, a SiO 2
layer of 0.3 lm thickness was deposited by means of
thermal oxidation as an insulation layer. Subsequently,
Ta/Cu (270 nm/0.5 lm thick) films were
formed on the wall and bottom of the via holes by
means of ionized metal plasma sputtering.
Schematic illustrations of Zn via-filling by means
of a combined electroplating and reflow method are
shown in Fig. 1a. The via holes were partially filled
with Zn by the electroplating of Zn in a Zn bath of
zinc chloride (60 g/L), potassium chloride (150 g/L),
boric acid (28 g/L), Unizinc ACZ 552 (humectant,
40 mL/L), and Unizinc ACZ 554 (brightener, 2 mL/L).
The electroplating current density was varied
from 5 mA/cm 2 to 20 mA/cm 2 and the plating time
was changed in a range of 60 min to 120 min to
investigate how the electroplating conditions affect
the Zn via-filling. After the electroplating of Zn,
the specimen was put in an autoclave and maintained
at 430°C, which is 10°C higher than the
melting point of Zn (about 421°C) for complete
melting of the Zn, under a pressure of 0 MPa to
3 MPa for 60 s.
Via-filling was also conducted by dipping a via
hole specimen into a bath of molten Sn-xZn
(x = 20 wt.%, 30 wt.%, and 100 wt.%) as shown in
Fig. 1b. Granules of high-purity (99.99%) Sn and Zn
were charged in a crucible and melted at 430°C to
form the molten Sn-xZn, and the relative amounts of
the Sn and Zn granules were weighed to the
appropriate amounts before being charged in the
crucible. A via hole specimen was fixed at the holder
and immersed in the Sn-xZn crucible under a certain
pressure (0 MPa to 4 MPa) controlled by N 2
gas. Finally, the specimen was pulled out of the bath
and cooled under the N 2 gas pressure.
After the via-filling process, chip stacking was
conducted as shown in Fig. 2. Chemical mechanical
Fig. 1. Schematic illustrations of via-filling using (a) the electroplating/reflow process, and (b) the dipping process.

Zinc and Tin-Zinc Via-Filling for the Formation of Through-Silicon Vias in a System-in-Package 687
Fig. 2. The process flow of chip stacking for 3D interconnection.
polishing and backside grinding were performed on
the Si wafer until the wafer was 100 lm thick. The
interconnections between chips were formed by the
fabrication of Cu/Sn bumps of 70 lm diameter above
the Zn vias. The fabrication of the bumps involved a
process of electroplating 10-lm-thick Cu and 2-lmthick
Sn after the deposition of a Ti/Cu (10 nm/
100 nm thick) seed layer. For the fabrication of a
stacked package, three chips with Zn vias were
aligned one over another on an alumina substrate at
250°C with 100 N for 2 min after the dispensation of
a nonconductive adhesive.
The liquidus temperatures of the Sn-xZn
(x = 0 wt.% to 100 wt.%) alloys were measured by
means of differential scanning calorimetry, and the
electrical conductivities of the Sn-xZn alloys were
also evaluated at room temperature with the aid of a
four-point probe (Suss PM5 probe station) with bulk
Sn-Zn specimens (10 mm 9 10 mm 9 5 mm).
Microstructural analysis was conducted by means
of scanning electron microscopy (SEM) after crosssectioning
the Si wafers with the Sn-xZn vias and
the stacked package specimens. The compositions of
the phases formed in the Sn-xZn vias and the Cu-Sn
bumps were identified by means of energy-dispersive
spectroscopy.
RESULTS AND DISCUSSION
The liquidus temperatures and the electrical and
thermal conductivities of the Sn-Zn alloys are presented
in Table I. It can be seen that variations in
the liquidus temperatures of the Sn-Zn specimens
are very consistent with the reported data. 9 The
electrical conductivities of Sn-Zn specimens
increase with the amount of Zn, a phenomenon
attributed to the fact that the electrical conductivity
of Zn (0.169 (lXcm) 1 ) is higher than that of Sn
(0.082 (lXcm) 1 ). The thermal conductivities of
the studied Sn-Zn alloys, which were obtained from
the data of the electrical conductivities of these alloys
by using the Wiedemann–Franz law and the
Lorenz number (2.45 9 10 8 WX/K 2 ), 10 also increased
with the content of Zn. Because the thermal
conductivity of Si is 148 W/m K, 10 the Sn-Zn vias of
high Zn content have the advantages of a low
thermal expansion mismatch with Si and a high
heat transfer capacity. However, the Sn-Zn vias of
high Zn content have high liquidus temperatures
and may have a drawback in terms of the via-filling
process. Thus, the optimum composition of Sn-Zn
vias should be determined by a trade-off between
these two aspects.
Table I. Physical Properties of the Sn-Zn Alloys with Various Zn Contents
Zn Content in Sn-Zn
Alloy (wt.%)
Liquidus
Temperature (°C)
Electrical Conductivity
(1/lX cm) at Room Temperature
Thermal Conductivity
(W/m K) at Room Temperature
0 232.1 8.5 ± 0.1 62.5 ± 0.9
10 208 9.2 ± 0.2 67.6 ± 1.4
20 232 10.5 ± 0.16 77.2 ± 1.1
40 307 11.2 ± 0.2 82.3 ± 1.3
60 345 12.3 ± 0.2 90.4 ± 1.1
80 370 14.0 ± 0.2 102.9 ± 1.5
100 420 17.2 ± 0.2 126.4 ± 1.5

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Jee, Yu, Park, and Oh
Fig. 4. Optical micrographs of Zn vias filled by electroplating
(5 mA/cm 2 , 120 min) and reflow (430°C, 1 min): (a) without a filling
pressure and (b) with a filling pressure of 3 MPa.
Fig. 3. SEM micrographs of the Zn layers electroplated into via holes
at (a) 20 mA/cm 2 for 60 min and (b) 5 mA/cm 2 for 120 min.
SEM micrographs of the Zn layer electroplated
into the via holes at a current density of 20 mA/cm 2
for 60 min are shown in Fig. 3. A pinch-off can be
observed near the via mouth, as illustrated in
Fig. 3a, because the plating rate was higher, with a
faster charge and mass transfer rate, near the via
mouth than at the via bottom. 7 With such a pinchoff
formation, it would be difficult to fill the via holes
with Zn even with a reflow process because the
blocking area (pinch-off) hinders the flow of molten
Zn into the via holes during the reflow process. The
electroplated pinch-off was eliminated by fixing the
current density and duration of the Zn electroplating
at 5 mA/cm 2 and 120 min, respectively, and by
uniformly electroplating the Zn layer over the Cu
layer as shown in Fig. 3b instead of forming a pinchoff
near the via mouth. The probability of the pinchoff
formation becomes lower when the density of the
electroplating current decreases due to the reduced
current crowding at the via mouth and the less
significant mass transport limitation toward the via
bottom. 7 In this case, Zn flowed into the via holes
smoothly during a reflow of Zn. However, the via
holes cannot be completely filled solely by means of
the electroplating/reflow process but only when a
filling pressure is applied during the reflow and
cooling steps of Zn.
Figure 4 clearly illustrates the filling pressure
effect on via-filling during a reflow of electroplated
Zn. Optical microscopy was used instead of SEM so
that the existence of voids in the vias could be
clearly observed. Without any filling pressure,
numerous voids are trapped in the Zn vias after the
Zn reflow process, as shown in Fig. 4a. On the other
hand, the application of 3 MPa of pressure during
the reflow process prevents the formation of voids in
the Zn vias, as illustrated in Fig. 4b. The trapping of
voids in the vias can be explained by a mechanism of
pore formation. 11,12 During the reflow process, the
liquid Zn flows into the via holes and the Zn vapor
acts as a barrier against the surrounding gases.
Nonetheless, the surrounding gases are diffused
into the liquid Zn during the cooling process
because, in accordance with the Clausius–Clapeyron
relation, there is a significant reduction in the vapor
pressure of Zn. The gases then accumulate in the Zn
vias, causing the entrapment of voids. However, the
internal pressure of the liquid Zn increases when
pressure is applied. This prevents the gases from
being diffused into the liquid Zn during the solidification
process and, as a result, no voids are
formed. 11,12 Note also that the pressure accelerates
the infiltration of Zn into the via holes.
Via-filling by means of the dipping method was
also examined and compared with the electroplating/reflow
process. For the dipping method, the
composition of the Sn-Zn vias can be easily controlled
just by changing the Sn-Zn bath composition.
However, pressure is also essential for ensuring the
vias are completely filled with a Sn-Zn alloy. The
effect of pressure on the Sn-Zn filling behavior was
also confirmed, as shown in Fig. 6, by varying the
filling pressure during the dipping process. The vias
remain unfilled when the applied pressure is 0 MPa
to 2 MPa (Fig. 5a–d) but, as shown in Fig. 5e, they
are completely filled (without voids) when the
applied pressure is 4 MPa. When a via specimen is
dipped into a molten Sn-Zn bath, the liquid Sn-Zn
covers the entire surface of the specimen but does
not flow into the via holes due to the surface tension
of the liquid Sn-Zn; hence, air is trapped in the via
holes. Without any filling pressure, the liquid Sn-Zn
is prevented from flowing into the via holes, as
shown in Fig. 5a. When the applied pressure is

Zinc and Tin-Zinc Via-Filling for the Formation of Through-Silicon Vias in a System-in-Package 689
Fig. 5. Effect of filling pressure of (a) 0 MPa, (b) 0.5 MPa, (c) 1 MPa, (d) 2 MPa, and (e) 4 MPa on the occurrence of voids in Sn-30Zn vias
formed by the dipping method.
Unfilled volume / initial volume ratio
1.0
0.8
0.6
0.4
0.2
0.0
0 1 2 3 4
Applied pressure (MPa)
Fig. 6. Unfilled volume ratio in the Sn-30Zn vias formed by the dipping
process with variation of the filling pressure.
increasedto2MPa,thereisanincreaseinthevolume
ratio of the filled Sn-Zn in the via holes but the via
holes are not completely filled (Fig. 5b–d). However,
as shown in Fig. 5e, the via holes are completely
filled with Sn-Zn when the pressure is 4 MPa. The
correlation between the pressure and the filling of
Sn-Zn is clearly demonstrated in Fig. 6, that is, the
unfilled volume ratio is reduced when the applied
pressure is increased during the via-filling process.
Cross-sectional SEM images of the vias filled with
Zn and Sn-Zn under 3 MPa are presented in Fig. 7a
and b. As shown in Fig. 7a, the vias are completely
filled with Zn and there are no intermetallic compounds
(IMCs) between the Zn and the seed Cu.
During the filling process, the 100-nm-thick Cu seed
layer was completely dissolved into the Zn liquid.
The calculated amount of dissolved Cu was about
0.05 wt.%, which is much less than the solubility of
Cu in Zn (about 2.8 wt.%); hence, no IMCs formed in
the Zn vias. In Fig. 7b, the via holes are also completely
filled with Sn-Zn (80 wt.%:20 wt.%). At room
temperature, large platelets of Zn precipitates are
dispersed in the Sn matrix due to the slight solubility
of Sn in Zn and vice versa. Most of the Zn
precipitation occurs at the wall of the vias, as shown
in Fig. 7b, possibly due to the heterogeneous nucleation
of Zn during the cooling process at the via wall
of high surface energy. As mentioned, the relative
quantities of Sn and Zn can be varied by controlling
the weight of the Sn and Zn elements in the molten
Sn-Zn bath. This type of control can yield desirable
via properties, particularly with regard to the melting
point and coefficient of thermal expansion, as
well as the thermal and electrical conductivities.
After the via-filling process, three-chip stacking
was conducted by flip-chip bonding of planar-type
Cu/Sn bumps at 250°C for 120 s under 100 N, as
shown in Fig. 8a. A nonconductive adhesive was
applied to each chip before the flip-chip bonding. As
illustrated in Fig. 8b, the chip-stacked interface was
composed of Cu 3 Sn/Cu 6 Sn 5 /Cu 3 Sn layers. In the
case of the Cu/Sn bump joints, the formation of
Kirkendall voids raises the issue of mechanical
reliability during isothermal aging treatment. The
addition of Zn to Sn reportedly suppresses the formation
of Kirkendall voids due to the accumulation
of Zn at the IMC/Cu interface and consequently
increases the reliability of the bump joints. 13 The
Sn-Zn bumps may improve the mechanical reliability
of the bump joints of the chip-stack specimens.
CONCLUSION
The use of electroplating/reflow and dipping
methods in Zn and Sn-Zn via-filling processes for
TSVs offers wider process windows for chip-stack
packages. The application of a current density of
5 mA/cm 2 for 120 min restrained the pinch-off near

690
Jee, Yu, Park, and Oh
Fig. 7. Cross-sectional SEM micrographs of (a) Zn and (b) Sn-20Zn vias filled by the dipping process with an applied filling pressure of 3 MPa.
specimens, chip stacking was successfully conducted
by using a flip-chip bonding process.
Fig. 8. Cross-sectional SEM micrographs of (a) a three-chip-stacked
specimen with Zn vias and (b) a Cu-Sn bump joint.
the via mouth during the electroplating of Zn,
enabling the electroplated Zn to flow into the via holes
during the subsequent reflow process. Via-filling
can be successfully achieved by dipping a via hole
specimen into a molten Sn-Zn bath. In both cases,
a pressure of 3 MPa or more should be applied
during the filling and cooling steps. With the Zn via
ACKNOWLEDGEMENT
This work was supported by the Center for Electronic
Packaging Materials (ERC) of MOST/KOSEF
(Grant #R11-2000-085-08001-0).
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