Carbon Nanomaterials for Next Generation Interconnects and ...

NSF-SRC-SIGDA-DAC Design Automation Summer School, July 25-26 2009, San Francisco, CA 

Carbon Nanomaterials for Next 

Generation Interconnects and Passives 

Prof. Kaustav Banerjee 

University of California, Santa Barbara 

kaustav@ece.ucsb.edu 

Kaustav Banerjee, UCSB KEYNOTE: 12 th IEEE Workshop on Signal Propagation on Interconnects (SPI), Avignon, France, May 15 th , 2008

Outline 

Part I: 

• Limitations of Copper Interconnects 

• Carbon Nanomaterials: : Basics 

• Circuit Elements of CNT/GNR 

• Fabrication and Integration of CNT/GNR 

Interconnects 

Part II: 

• Performance Evaluation of CNT/GNR Interconnects 

• Electro-thermal thermal Analysis of CNT Vias 

• High-Frequency Analysis of CNT Interconnects 

• Passives and Other Applications 

Kaustav Banerjee, Kaustav UC Santa Banerjee Barbara 

Design Design Automation Automation Summer Summer School, July School 25-26 Lecture, 2009, San July Francisco, 26 2009, CA San Francisco, CA

Part I 



Interconnects in ICs…. 

By volume, ICs have 

become “all wires”… 

SEM image of IBM’s six-level 

Cu interconnect technology 

Interconnects have become the dominant player in 

circuit timing and process complexity… 



End of the Road for Cu 

Future Interconnect Requirements: 2005 ITRS 

Red Areas: no known solutions! from 2014 onwards: J max > 1.06 x 10 7 A/cm2 



What is Wrong with Cu 

• Size effect on Cu resistivity 

MFP of Cu ~ 40 nm at room temperature 

Resistivity [μΩ-cm] 

5 

4 

3 

2 

1 

Intermediate Tier Wires 

Barrier Layer Effect 

At 300 K 

Surface Scattering 

Grain Boundary Scattering 

Background Scattering (ρ o ) 

Total 

0 

90 

65 

45 

32 

Technology Node [nm] 

22 


S. Im et al., IEEE TED, Dec. 2005 

Based on analytical models in 

Steinhogl et al., J. Appl. Phys., , 2005. 

Impact is worse for local wires and vias 

Increases wire delay: even in local wires 


Interconnect Temperature 

Cu Resistivity 

Current density 

Cu thermal conductivity 

Low-K dielectric 

ILD thermal conductivity 

Worst case temperature rise with respect 

to the junction temperature (85ºC) 

S. Im et al., TED, 2005 

Temperature rises significantly 

due to self-heating….. 



Current Carrying Capability of Cu 

• Electromigration Lifetime: strongly reduces with temperature 

• Limits maximum current carrying capacity…. 

Current Density (MA/cm 2 ) 

Maximum allowed J based on selfconsistent 

(EM+Self-heating) 

solutions… 

Significant deficit in current 

carrying capacity for local vias…. 

Increasing via size and/or number 

will be expensive…. 

N. Srivastava and K. Banerjee, JOM 2004. 



Reliability and Current Carrying 

Capacity of Carbon Nanotubes 

• Current density up to 10 10 

A/cm 2 without heatsink 

(not embedded in SiO 2 

) 

• Equivalent Au-, Cu-, Alwires 

deteriorate at 10 7 

A/cm 2 

B.Wei et al. APL 79, 1172 (2001) 

SWCNTs [M. Radosavljevic et al., PRB, 2001] and Graphene [K. S. Novoselov et al., Science, 

2004] show similar current carrying capacity… 



Outline 

Part I: 





Interconnect 



Forms of Carbon… 

allotropes 

3D: diamond graphite 

2D: graphene 

Carbon atom can 

form several 

distinct types of 

valence bonds…. 

1D: nanotube (CNT) nanoribbon (GNR) 

0D: fullerenes 



A bit of history…. 



Carbon Nanomaterials 



Carbon Based Interconnect Materials 

Roll-up 

Stack and 

Pattern 

Pattern 

Graphene 

Carbon Nanotubes 

Mono-layer Graphene 

Nano-Ribbon 

Multi-layer Graphene 

Nano-Ribbon 



TEM Images of CNTs 

5 shells 2 shells 7 shells 1 shell 

Some of Iijima’s first images of multi-walled CNTs…. 


SWCNT 

(Infineon) 


Images of Graphene 

SEM image of 

Graphene crystal 

A. K. Geim et al, 

Naturematerial, 2007 

Most of crystal’s faces are either Zigzag or armchair edges 

AFM image of Graphene Nanoribbon X. Li et al, Science, 2008 



CNT/GNR Crystal Structures 

Armchair CNT (3, 3) Zigzag CNT (5, 0) 

Zigzag GNR 

Armchair GNR 

CNT/GNR have different definitions, but share similar properties… 



Chirality of CNTs 

• Indices (n, m) represent 

the magnitude of vectors in 

the a 1 and a 2 direction 

• CNT’s circumference is 

determined by magnitude 

of the chiral vector C 

r h 

r r 

Ch 

= na1+ 

ma2 

• Diameter D is 

Ch 

3 

D = = a n + nm+ 

m 

c−c 

2 2 

π π 

• Roll-up direction (n, m), 

determines the chirality of 

CNTs 

• Metallic: n-m = 3i (i is an 

integer) 



Metallicity of CNT/GNR 

2π ⋅ i = C⋅k 

Periodic boundary condition 

quantizes the allowed k values 

If slices hit the apex of cone zero gap 

Otherwise Band gap 

Graphene bandstructure 

Similarly, GNR also has 

boundary condition 

π ⋅ i = 

w⋅k 

Armchair 

Zigzag 

Chiral 

CNT 

metallic 

n or m = 3i 

n-m=3i 

GNR 

N=3i-1 

metallic 

- 



Metallic Condition 

Reciprocal space 

C: the chiral vector 

(circumference) 

T: the translational 

vector 

C r : reciprocal vector of T 

T r : reciprocal vector of T 

K: Dirac point of Brillouin zone 

C r : Quantized due to circumferential 

boundary condition 

uuur 2n+ 

m 

XK = Cr 

3 

Hence, the condition for metallicity is 

(2n+m)=3i, or equivalently (n-m)=3i 



Band Structure of CNTs with 

Different Chirality 

10 

(n, m)=(7, 7) 

D=0.95 nm 

(n, m)=(9, 0) 

D=0.7 nm 

10 

(n, m)=(13, 0) 

D=1 nm 

5 

5 

0 

Energy (eV) 

Energy (eV) 

0 

-5 

-5 

-10 

-1 -0.5 0 0.5 1 

-10 

-1 -0.5 0 0.5 1 

K 

K 

Zero gap, metallic Zero gap, metallic Semiconducting 



Bandgap of CNT vs Diameter 

• Bandgap scales with 

diameter of the 

nanotube due to 

confinement 

~ 0.8eV/D 

• Additional small gaps 

due to curvature of 

the CNTs 

• Large diameter (>5 

nm) ) MWCNTs will 

have a vanishing gap 

@ 300K 

Kane et al., PRL, 1997 



Band Structure and Density of States 

(DOS) for Small Diameter (SWCNT) 

• DOS of SWCNT is very small 

F. Kreupl, et al., AMC, 2005 

• Doping has almost no influence on its DOS 



Band Structure and DOS for Large 

Diameter (MWCNT) 

• DOS of MWCNT is larger 


• Doping can shift Fermi energy and DOS easily 



Conducting Channel of CNTs 

• For SWCNT = 4 

– Lattice degeneracy (x2) 

– Spin degeneracy (x2) 

• For MWCNT (depends on diameter) 

N 

shell 

= 

= 

∑ 

subbands 

∑ 

f 

i 

1 

exp( E − E k T) + 1 

subbands i F B 

Can be approximated by: 

10 

5 

0 

-5 

-10 

-1 -0.5 0 0.5 1 

K 

(n, m)=(7, 7) 

SWCNT, D=0.95 nm 

N ( D) ≈ aD + b, D > 3nm 

shell 

a=0.0612 nm -1 , b=0.425 

Almost Linear with the diameters. 

∑ 

tot i i 

shells shells 

A. Naeemi, et al., IEEE EDL, 2006 

∑ 

N = N = a⋅ D + b 



Electron Mean Free Path (λ) of CNTs 

• Dependence of diameter 

– Metallic shells 

2 

3πψ 

λ = 2σ 

+ 9σ 

⋅ D 

2 2 

ε ψ 

– Semiconducting shells 

J. Jiang, et al., Phys. Rev. B, 2001 

v F 

λ = α 

⋅ D 

T 

Hence, λ is proportional to the diameter. 

X. Zhou, et al., Phys. Rev. Lett., 2005 

• Based on measurements, λ~1μm for D=1nm CNT 

J. Y. Park et al., NanoLetter, 2004. 

We can set λ ≈1000 D 



Band Structure of GNRs 

C. Xu et al., TED, 2009 

E (eV) 

N = 44 

w = 11 nm 

E (eV) 

0.12 eV 

N = 45 

w = 11 nm 

N = 3m −1 Metallic 

3ka 

Metallic ac-GNR 

N = 3m, 3m +1 Semiconducting 

3ka 

Semiconducting ac-GNR 

N = 26 


Always Metallic 

Small variation of N 

Negligible change in band structure 

E (eV) 

E 1 

E 0 

−E 1 

−E 2 

Design Design Automation Automation Summer Summer School, July School 25-26 Lecture, 2009, San July Francisco, 26 2009, CA San Francisco, CA 

E 2 

w = 11 nm 

ka 

zz-GNR

Thermal Transport 

• Quantized thermal conductance 

κ π κ B T h 

= 2 2 

0 

/3 

0 

• At room temperature 

– Electron contribution 

κel 

~4κ 

(4 conduction modes, bandgap ~ eV) 

– Phonon: A large number of modes (bandgap( 

~ meV) 

ka/π 


H. Li et al., TED, 2009 

Phonon dominates thermal transport! 

T. Yamamoto, PRL, 2004 



Basic Properties of Cu, CNT and GNR 

Cu 

SWCNT 

MWCNT 

Graphene or 

GNR 

Max current density 

(A/cm 2 ) 

10 7 

>1x10 9 

Radosavljevic, , et al., 

Phys. Rev. B, 2001 

>1x10 9 

Wei, et al., 

Appl. Phys. Let., 2001 

>1x10 8 

Novoselov, , et al., 

Science, 2001 

Melting point (K) 

1356 

3800 (graphite) 

Tensile strength 

(GPa) 

0.22 

22.2±2.2 

11-63 

Thermal conductivity 

(×10 3 W/m-K) 

0.385 

1.75-5.8 

5.8 

Hone, et al., 

Phys. Rev. B, 1999 

3.0 

Kim, et al., 

Phys. Rev. Let., , 2001 

~3.0-5.0 

Balandin, , et al., 

Nano Let., , 2008 

Temp. Coefficient of 

Resistance (10 -3 

/K) 

4 

1,000 

McEuen, , et al., 

Trans. Nano., 2002 

25,000 

Li, et al., 


~1,000 

Bolotin, , et al., 




Outline 

Part I: 





Interconnect 



CNT/GNR Resistances: R Q , R C and 

R S 

• R Q : Intrinsic quantum contact resistance - even for very 

short lengths with no scattering and perfect contacts 

= 

(lowest possible R—hence R 

need CNT-bundles or multi- 

layer GNRs) 

• R C : Imperfect parasitic contact resistance (can( 

be 

high…up to 100 KΩ) K 

• R S : length dependent scattering resistance 

(for Length >> MFP =λ) = 

h 

N2e 

N = number of conducting channels 

= 

h 

2 

2 

L 

2 

N e λ 



CNT/GNR Conductance Model 

Linear response Landauer formula 

2 

2q 

( ) ⎛ ∂f0 

⎞ 

Gn = τ 

n 

E ⎜ − ⎟ dE 

h 

∫ 

⎝ ∂E 

⎠ 

G n 

: Conductance of the n th conduction channel 

f 0 

(E): Fermi-Dirac distribution function 

τ n 

(E): Transmission coefficient 

If all channels are identical, it can be simplified as: 

G 

n 

2 

2q 

= ⋅M⋅τ 

h 

( ) 

M = ∑ ⎡1+ exp En −EF kBT ⎤ 

− 

⎣ ⎦ 

n 

τ = 1, if it is ballistic, otherwise… 

M: Total number of conducting channel 

τ: Effective transmission coefficient 

1 

Can be calculated from bandstructure 

H. Li et al., TED, vol. 56, no. 9. 2009 



CNT/GNR Conductance Model 

(contd.) 

( ) ⎡ 

τ 1 

n 

E = ⎢ + 

⎣ 

λ 

L 

CNT 

⎤ 

⎥ 

⎦ 

−1 

λ CNT : Mean free path (MFP) of CNT 

⎡ ⎛ 1 1 ⎞⎤ 

τ 

n 

( E) = ⎢1+ L⎜ 

+ ⎟⎥ 

⎣ ⎝ λD 

cosθ w cotθ 

⎠⎦ 

−1 

λ D 

: Mean free path corresponding to 

non-edge scattering mechanisms 




Comparison of Resistivity 

100 

Resistivity [ -cm] 

10 

Cu: W=14nm, =8.19 

Cu: W=22nm, =6.01 

Cu: W=32nm, =4.83 

A 

ρ = ( RQ 

+ RS) 

L 

1 


1 10 100 1000 

Length [ m] 


‣ Area of MWCNT is much larger than that of SWCNT 

• short length: MWCNTs have larger resistivity than SWCNTs 

‣ However, MWCNTs have longer MFP than SWCNTs 

• long length: R s 

is much smaller for MWCNTs, so that resistivity 

of MWCNT becomes comparable to SWCNT 


Resistance Comparison 


Resistance per micron [ m] 

Dielectric 

w 

Mono-layer GNRs 

Mono-layer GNRs 

Dielectric 

w 

Resistance per micron [ m] 

Graphene 

Layers 

Dielectric 

w 

Multi-layer GNRs 

Intercalation doped multi-layer GNRs 

0.815 nm 

Intercalation 

Layers 

0.335 nm 

• Ideal Multi-layer case SWCNT GNRs and DWCNT have similar resistance 

Neutral multi-layer GNRs 

• For GNR, intercalation doping and high specularity are needed 

C. Xu et al., TED, vol. 56, no. 8, 2009 

Stage 1 Stage 2 

Stage 3 

Graphene Layers 

Intercalation Layers (AsF 5 

) 



CNT/GNR Capacitance: C Q and C E 

Adding electron raises up the E F 

∫ 

F 

F 

2 

= eDE ( ) δV 

2 

δQ 

2e 

C = = ≈ 97 aF / 

{ δ } 

δQ = e dED( E) f( E −E ) −f[ E − ( E + e V)] 

Q 

δV 

hv 

F 

μm 

δQ 

2C 

2 

= 

Δ E = Δ E +ΔE 

ES 

F 

= 

δQ 

δQ 

+ 

2C 

2C 

2 2 

E 

Q 

1 1 1 

= + 

C C C 

E 

Q 

Electrostatic Capacitance, C E 

For single CNT: 

C CNT 

E 

= 

2πε 

⎛ 4y 

ln⎜ 

⎝ d 

⎞ 

⎟ 

⎠ 

~ aF / μm 

For other structures, it will depend on the geometry and may 

need numerical calculation. 



CNT Bundle Structure for 

Estimating C E 

GND2 

h=t 

CNT 

Bundle 

gnd 

left 

s=w 

h=t 

w 

s=w 

gnd 

right 

w 

t 

aF/um 

N. Srivastava et al., TNT, 2009 

GND1 

Inner CNTs are effectively 

screened from the surrounding 

interconnect geometry 



CNT Bundle Electrostatic 

Capacitance 

28 

nm 

14 nm 

36 

nm 

18 nm 

44 

nm 

N. Srivastava et al., TNT, 2009 

22 nm 



CNT/GNR Inductance: L K and L M 

E Current I 

eδV 

Magnetic inductance, L M 

For single CNT: 

d 

y 

k 

Small density of states cause large 

total kinetic energy: 

L ≈ 16 nH/ 

μm 

K 

Scaling by conducting channel number N 

SWCNT has 4 channels, hence: 

L ≈ 4 nH/ 

μm 

KSWCNT 

1 h 

ΔE = × × I 

2 

2 2evF 

2 

L CNT 

M 

= 

μ ⎛ 4y 

ln⎜ 

2π ⎝ d 

⎞ 

⎟ 

⎠ 

~ pH / μm 

L K 

is 3 orders larger than L M 

! 



Existence of L k 

• High-Frequency (20GHz) 

S-parameter 

measurements for both 

individual SWCNT and 

SWCNT bundle (L=2μm) 

• Shows L K of SWCNT is of 

order of nH/μm, 

which 

agrees with theoretical 

analysis 

• The inductance of CNT 

bundle scales with the 

number of CNTs 

Plombon et al., Appl. Phys. Let., 2007 

In order to analyze inductive effects in CNT interconnects, 

we need accurate inductance (including kinetic and 

magnetic) model for CNT bundles… 



Outline 

Part I: 


• Carbon Nanotubes: Basics 






CNT Interconnect Fabrication 

[Kreupl et. al., (Infineon) IEDM, 2004] 

[Sato et. al., (Fujitsu) IITC, 2006] 

[Awano et al., (Fujitsu) 2006] 

[Choi et. al., (Samsung) Nano Conf., 2006] 

[Nihei et. al., (Fujitsu) IITC, 2007] 



CNT Interconnect (via) Fabrication 

Catalytic CVD Growth 

nature does it for you….all you need is 3 ingredients 

1. Catalyst nanocluster: Fe, Ni or Co + a reducing gas 

2. Carbon containing compound (gas): CH4, C2H2, CH3CH2OH…. 

3. Energy (Temperature): 400-1400 0 C 

Substrate –catalyst interaction is also very important…. 

Courtesy: F. Kreupl, Infineon 



Fabrication Techniques & Challenges-I 

• Long throat catalytic deposition (via PVD) in high 

aspect ratio trenches 

Duesberg et al., Nanoletters, 2003 

nanotube 

Via definition 

by resist 


Via etch 

Long throat 

catalyst 

deposition 

lift-off 

Nanotube 

growth 

Challenges: i) sidewall deposition causes sidewall CNT growth---via filled but 

no electrical contact to the bottom! 

ii) catalyst thickness and nucleation depends strongly on surface 

condition after etch, results are irreproducible…. 


Fabrication Techniques & Challenges-II 

• Buried catalyst layer 

[Graham et. al., Diamond and Related Materials, 2004, 

Liebau et al., AIP P., Kirchberg, 2004] 

• Etching of via stops on top of 1-31 

3 nm thick catalyst layer 

Via definition 

by resist 

Via etch stop 

on catalyst 

Resist strip 

Nanotube 

growth 

Challenges: i) etch stop on thin catalyst layer is critical 

ii) Wafer/chip scale homogeneity not yet demonstrated 



Diameter-Controlled Nanoparticles 

Size distribution, 

Diameter: ~ 4 nm, 

δ: ~25% 

CMP: 

to cut-off the cap and make contact with inner shells… 


S. Sato et al., IITC, 2006 

M. Nihei et. al., IITC, 2007 


Alternative Process: Bottom up 

• Overcomes the need for etching high aspect ratio vias needed 

in future technologies 

• Can reliably grow MWCNT bundles 

Li et. al., APL, 2003 

Metal 

Deposition 

Catalyst 

Patterning 

PECVD 

Top Metal Layer 

Deposition 

CMP 

TEOS CVD 

Challenges: i) quality of CNTs is low and so is electrical conductivity 

ii) tilt for small diameter tubes is also considerable---subsequent 

litho step is difficult 



Process Improvements 

• Densification 

Z. Liu et. al., IITC, 2007] 

Increases the density of CNT 

bundle by 5~25 times. 

• Increase fraction of metallic NTs 

(a) Before and (b) after densification. 

Applying an electrical field makes metallic CNT and semiconducting 

CNTs to have different movements. Hence, increase the fraction of 

metallic… 

Krupke et. al., Science, 2003; Peng, J. Appl. Phys. 2006 

However, this method is difficult to combine with CNT interconnect 

fabrication… and even when they increase the fraction of metallic, the 

density of CNT is quite low… 



Low Temperature CNT Growth 

450 o C 400 o C 365 o C 

Growth temperature down to 365 0 C 

- the lowest reported for interconnect application. 

However, the lower the growth temperature, the worse it gets for CNT quality… 

A. Kawabata et. al., IITC, 2008 



CNT Wafer 

Y. Hayamizuet. al., Nature Nanotech., 2008 



Integration with Low-K Dielectric 

CNT Single Kelvin via 

grown at 400 0 C 

A. Kawabata et. al., IITC, 2008 

CNT via is robust under current high-density 

stress over long time….. 



CNT Interconnect Integration Issues 

• Process Advantages vis-à-vis Copper 

– Diffusivity into Si/dielectric is not a problem--- 

---no need for barrier 

– Bottom-up growth processes can eliminate the need for etching high 

aspect ratio vias 

– No “dishing” type effect…. 

• Key Issues: 

– Difficult to grow dense high-metallic fraction SWCNT bundles 

– Most interconnect processes so far employ MWCNTs which have 

been easier to grow-- 

--recently it has become possible to grow 

bundles of SWCNTs also by adding water or oxygen to increase 

activity (to 84%) of the growth catalyst [Futaba et al., J. Phys. Chem. B 

J. Phys. Chem. B, , 2006] 

– High temperatures involved in CNT growth—recently recently grown at 365 

0 

C (Fujitsu), but need better quality. 

– Metal-CNT 

contact resistance 


– Control over growth mode (substrate-catalyst interaction) 



Graphene Fabrication Methods and 

Implication for Interconnect Application 

1. Chemical vapor deposition 

-- Not single crystal; low electrical conductivity 

2. Thermal decomposition of single crystal SiC 

C. Berger, Science, 2006 

-- Requires high processing temperature 

3. Mechanical exfoliated from graphite, and deposited 

onto an insulating substrate J. C. Meyer, Nature, 2007 

-- Uncontrollable for massive fabrication 

4. Segregation, transferring and removing substrate 

Q. Yu, APL, 2008 

G. Aichmayr, IEEE Symp. VLSI Tech. 2007 

-- Seems OK, will be explained in the next slide 



GNR Interconnect Fabrication… 

Nickel Substrate 

Segregate 

Graphene 


Silicone film 

Graphene 


Transfer to desired 

substrate 

Desired substrate 

Silicone film 

Graphene 



Graphene 

Silicone film 


Remove Nickel 

Graphene 

Silicone film 


Pattern & 

make via 

contacts 

Graphene 

Silicone film 

Desired Substrate 

Pattern 

GNR wire 

GNR 

Silicone film 

Desired Substrate 


Implication from Q. Yu, APL, 2008 



Hybrid Graphene/CNT 


• Vertical via is based on CNTs and horizontal wire is based CNTs 

http://www.fujitsu.com/global/news/pr/archives/month/2008/20080303-01.html 



Part I: References (1) 

Limitations of Cu 

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of Copper Wires With Lateral Dimensions of 100 nm and Smaller”. 

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2719, 

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High Performance ICs.” 

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398. 

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for 

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206 

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low temperature process over a high-density current”. 

• Appl. . Phys. Lett., vol. 93, no. 11, pp. 113103, Nov. 2008 

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transferred to insulators” 

• Science Express Reports, 10.1126/science.1171245, May 2009 

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Colombo, R. S. Ruoff, “Large-Area Synthesis of High-Quality and Uniform Graphene Films on Copper Foils” 

• Appl. . Phys. Lett., vol. 89, pp. 143106, 2006 

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CNT Process Achievement and Improvement 

• Science, vol. 301, no. 5631, pp. 344-347, 347, 2003. 

R. Krupke, , F. Hennrich, , H. v. Lohneysen, , M. M. Kappes, “Separation of metallic from semiconducting single- 

walled carbon nanotubes,” 

• Physical Review Letters, vol. 95, 086601, 2005 

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nanotubes”. 

• IEICE Trans. Electron., vol. E89-C, pp. 1499-1503, 1503, Nov. 2006 

Y. Awano, “Carbon nanotube technologies for LSI via interconnects” 


203 

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Bundles for Interconnect Application”. 

• Nature Nanotechnology, vol. 3, pp. 289-295, 295, May 2008 

Y. Hayamizu, , T. Yamada, K. Mizuno, R. C. Davis, D. N. Futaba, M. Yumura, , and K. Hata, “Integrated three- 

dimensional microelectromechanical devices from processable carbon nanotube wafers,” 



Part II 



Outline 

Part I: 




• Fabrication and Integration of CNT/GNR Interconnects 

Part II: 

• Performance Evaluation of CNT/GNR 







Equivalent Circuit 

SWCNT and GNR 

H. Li et al., TED, vol. 56, no. 9, 

2009 

MWCNT (including DWCNT) 




Delay Comparison: Local 


H. Li et al., TED, vol. 56, no. 9, 2009 

Delay Ratio w.r.t Cu 

W=14 nm 

H = 28 nm 

• Ideal SWCNT and DWCNT are similar 

• MWCNT has better performance due to smaller capacitance 


– Some Mono-layer could have low delay due to much smaller capacitance 



Delay Comparison: Intermediate and 

Global 

1.4 

1.2 

Intermediate 

1.0 

0.8 

0.6 

0.4 

Global 

14 nm technology node 

• Almost all CNTs could outperform Cu 

100 1000 

Length of Interconnect [ m] 





Outline 

Part II: 







Expectation vs. Reality of CNT Vias 

Expectation 

Reality 

‣Ideally, ballistic transport 

‣High thermal conductivity 

• Isolated SWCNT 

>2000 W/mk (L=2.76μm) 

C. Yu et al., Nano Letter, 2005 

• Isolated MWCNT 

>3000 W/mk 

(L=2.5 μm, D=14 nm) 

P. Kim et al., PRL, 2001 

‣Interface effect 

‣Short length 

‣Bundle density 

‣ Reliability is a more important concern in CNT via 

‣ Need accurate electro-thermal analysis 

Provide guidelines to fabrication community 



Electrically Ballistic CNT Vias 

H. Li et al., IEDM, 2007 

‣For SWCNT: 

λ >300nm even in worst 

case (D = 0.4nm @110 o C). 

Local 

Global 

‣For MWCNT: 

λ will be longer than 

SWCNT due to large 

diameter. 

‣From ITRS, height of vias 

will always be smaller than λ. 

• Resistance of ballistic CNT 

R Q 

R = , length < λ 

N 

It’s safe to assume that CNT 

vias are electrically 

ballistic conductors 

N: Number of conducting channels 



CNT Via: Resistance 


CNT via can always be assumed to be electrically ballistic... 

‣ 

800 

With perfect contact, only 

600 smallest SWCNTs have 

comparable resistance to Cu 

400 

‣ With non-zero R mc 

, SWCNT 

200 resistance will be even larger than 

Cu 

Via Resistance [Ω] 

500 

450 

400 

15 

350 

10 

300 5 Diameter [nm] 

20 

SWCNT via 

MWCNT via 

R MWCNT Via 

> R SWCNT Via 

> R Cu Via 

(

Impact of Via Resistance on 

Interconnect Delay 

5 

4 

3 

32 nm 

22 nm 

14 nm 

Local 


Global 

2 

1 

0 

0 10 20 30 40 50 

R CNT 

/R Cu 

Local interconnect (M1) 

‣ Local via resistance has slight 

impact on interconnect 

performance (electrical latency) 

Global interconnect (buffered) 

‣ Global via resistance could 

have larger impact on 

performance 

If CNT resistance can be within an order of magnitude of Cu via 

resistance, the delay penalty is small…. 



Thermal Transport in CNT Vias: Is It 

Ballistic 

• Phonon mean free path ( (L o ) 

‣ L=2.76 μm, D=1 nm (SWCNT), T= 100-300 K, 

ballistic L o >2.76 μm 

C. Yu et al., Nano Letter, 2005 

‣ L=2.5 μm, D=14 nm (MWCNT), T= 10-300 K, 

estimated L o ~500 nm 

P. Kim, et al., PRL, 2001 

CNT vias ( 0 2π 

∂T 

n 

J. Wang and J. Wang, APL, 2006 

N. Mingo et al., PRL, 2005 

ω(q): phonon dispersion, f(ω,T) is Bose-Einstein distribution function 



Thermal Conductivity of CNT 

Thermal conductivity (K CNT 

) as a function of D, T and L 


‣ K CNT increases with temperature 

‣ Smaller diameter SWCNT has higher K CNT 

‣ For long length, K CNT >> K Cu 

‣ For short length (via case), K CNT ~ K Cu 



Electro-thermal Simulations 


Cu: 

T max 

occurs at M2 

SWCNT (D = 0.47nm): 

Perfect contact 

T max 

occurs at M2, ~ T max 

of Cu 


MWCNT (D =5 nm): 

Perfect contact 

T max 

>> T max 

of Cu 

- Contact is the bottleneck 

- Large Joule heating due to large 

electrical contact resistance 


Impact of Increasing Via Height 


Advantage of ballistic CNT: K CNT Via 

and R CNT Via 

remains the same for tall vias 

Max. Temperature [K] 

‣ T max 

of Cu via increases with 

height 

‣ T max 

of SWCNT via almost 

remains constant 

‣ Even with imperfect contact, 

SWCNT could be better than 

Cu for tall vias 

‣ MWCNT via is worse than Cu 

even at 300nm height 

Dense and small diameter SWCNT vias with good electrical and thermal 

contact are needed…..and would be better as tall vias 



Outline 

Part II: 







High-Frequency Effects in Cu 

Skin effect 

Skin depth: 

1 

δ = 

πμσ f 

Krauter et al., DAC, 1998 

• Resistance increases due 

to skin & proximity 

effects 

Z = R + j ω L 

Proximity effect 

• Current distribution is no 

longer uniform 

What will happen in CNT interconnects 



Magnetic Inductance of Individual CNT 

‣ Using Geometric Mean Distance (GMD) to calculate inductance. 

‣ GMD is valid if we assume current in each CNT to be uniform. 

• Self-inductance 

Arithmetic Mean Distance 

• Mutual inductance 


self μ0 ⎡ 2L 

AMD⎤ 

LCNT 

= L⋅ ln 1 

2π 

⎢ − + 

GMD L ⎥ 

⎣ 

⎦ 

ln GMD = ln D −lnξ 

out 

2 4 

lnζ = 0.1( a−bγ − cγ + dγ ), γ = Din 

/ D 

a = 2.51, b = 0.31, c = 3.81, d = 1.61 

2Dout 

AMD ≈ 

π 

out 

S 

L 

m 

μ 

2 2 

0 L L S S 

= ⋅L⋅ ⎢ln ⎜ + 1+ ⎟− 1+ + 

2 2 

2π 

⎡ 

⎢ 

⎣ 

⎛ 

⎜ 

⎝ 

S 

S 

⎞ 

⎟ 

⎠ 

L 

⎤ 

⎥ 

L⎥ 

⎦ 



Impedance of CNT Bundle 

• Impedance matrix 

[ Z ] 

matrix 

1 21 n1 

⎡ ZCNT jωLm L jωL 

⎤ 

m 

⎢ 21 2 n2 

⎥ 

⎢jωLm ZCNT L jωLm 

= ⎥ 

⎢ M M O M ⎥ 

⎢ 

⎥ 

n1 n2 

n 

⎢⎣jωLm jωLm L ZCNT 

⎥⎦ 

Z = jω( L + L ) + R 

i Self kinetic i 

CNT CNTi CNTi CNT 

i 

SWCNT, R = R (1 + L / λ), R = 6.5KΩ 

CNT Q Q 

∑ 

i 

MWCNT, R = 1/ 1/ R , R = R (1 + L / λ) / N , λ = 1000D 

CNT shell shell Q shell 

shell 

[ V ] = [ Zmatrix 

][ I ] ⇒ Effective Zbundle = Rtot + jωLto 


t 

‣ Each self-impedance (Z i CNT) includes R, L self , and L K 

‣ Effective value of total inductance and total resistance 

of CNT bundle can be calculated 



Understanding of Current Redistribution 

Impedance of each filament 

• 3D metal: no L K 

– low frequency, R (Z self ) dominates, Z 1 ~Z 2 

– high frequency, jωL becomes important 

Z >Z 

1 2 

Mutual Mutual 

Z 1 >Z 2 

Z=Z +Z 

Self 

mutual 

nonuniform current skin effect 

2 

1 

• CNT: has large L K 

Z =R+jωL +jωL 

Self self K 

L K >> L Mutual , 

Z 

Self 

>>Z 

Mutual 

1 

Z 1 ~ Z 2 

Negligible skin effect 

2 



High-Frequency Impedance of CNT 

Resistance [Ω] 

30 

25 

20 

15 

10 

5 

Cu wire 

SWCNT D=1nm, Fm=1 

MWCNT D=20nm 

MWCNT D=40nm 

Length = 500 μm 

Width=2μm, Height=1μm 

Equivalent d.c. 

Conductivity Model 

1 10 100 1000 

Frequency [GHz] 

Inductance [nH] 

0.68 

0.66 

0.64 

0.62 

0.60 

MWCNT D=40nm 

MWCNT D=20nm 

SWCNT D=1nm Fm=1 

Cu wire 

Equivalent d.c. 

Conductivity Model 



1 10 100 1000 



• SWCNT: resistance/inductance saturate at high frequencies 

• MWCNT: resistance/inductance negligible shift 

• Reduced skin effect in CNT interconnect! 



High-Frequency Behavior of CNT 

Bundle—From Maxwell’s Equations 


ur ur 

∇ 2 E = jωμσ 

E 

2 

2 2 

δ = ⋅ [( ωτ ) + 1] ⋅ ⎡ ( ωτ ) + 1−ωτ 

⎤ 

ωμσ 

⎣ 

⎦ 

0 

Skin Depth [ m] 

ωτ~1 

• CNT: skin depth saturates after 

certain frequencies 

• Saturation depends on the 

momentum relaxation time 

• MWCNT has largest skin depth 

and lowest saturation frequency 

ωτ

Outline 

Part II: 





– CNT Based Inductors and Capacitors 

– CNT Off-chip Applications 

– CNT NEMS 

– CNT ESD applications 

– System-level Applications 



CNT Based Inductor 

• Metal contact at each corner 

• Take advantage of high- 

frequency properties of CNT 

bundle 


S 

W 

Metal 

Contact 

CNT 

Bundle 

Dout 

• Ls & Rs: Using previous method 

– Ls: including kinetic and magnetic 

inductance 

– Rs: includes R Q, R S ,andR mc 

• Since the CNT bundle cross-sectino is 

very large (μm order), C Q is very large 

and can be neglected 

• C S , C ox and C sub is using distributed 

capacitance model 

eddy and R eddy are captured by complex 

image theory 

• L eddy 


Design Design Automation Automation Summer Summer School, July School 25-26 Lecture, 2009, San July Francisco, 26 2009, CA San Francisco, CA 

I 

I

Impact of Kinetic Inductance on Q-factor 

• Consider upper-bound of Q factor ωL tot /R 

– Has two component in CNT 

ωLtot 

ω 

Q = = ( L + L ) = Q + Q 

R R 

up bound m k mag kinetic 

Traditional Q factor 

ωLK _ Bundle Lk 

× L/ 

N 

Qkinetic 

= = ω 

R 

⎛ L 

Bundle 

⎞ 

RQ 

⎜1+ 

⎟ N 

⎝ λ ⎠ 

Lk 

1 λ ⋅ Lk 

= ω 

< ω⋅ 

R 1 1 

Q ⎛ ⎞ RQ 

⎜ + ⎟ 

⎝L 

λ ⎠ 

λ=1μm, L k =4nH/μm, R Q =6.5KΩ 

Q kinetic < 0.062 at 100 GHz 

Kinetic inductance itself has very little impact on Q… 


Q factor due to L K 

Q factor due to LK 

0.07 

0.06 

0.05 

0.04 

0.03 

0.02 

0.01 


10GHz 

50GHz 

100GHz 

0 

10 0 10 1 10 2 10 3 10 4 


Role of Kinetic Inductance 

• Although, L K itself has marginal impact on Q factor… 

– L K increases the total inductance 

– More importantly, L K reduces skin & proximity effects 

at high frequency in CNT interconnects 

– Prevents decrease of total inductance with frequency 

– Prevents increase of resistance with frequency 

• Very promising for high-frequency interconnect 

application 

– Inductor design: potential low loss, high-Q… 



Q Factor Comparison 


Quality Factor 

70 

60 

50 

40 

30 

20 

ρ sub 

= 10 Ω-cm 

Cu 

SWCNT Fm=1/3 

SWCNT Fm=1 

MWCNT D=10nm 

MWCNT D=20nm 

MWCNT D=40nm 

142% 

Resistivity [ -cm] 

D out =200 μm, N=4, 

W=10 μm, H=2 μm, S=1 μm 

10 

(a) 

0 

0.1 1 10 


• CNT can give better performance than Cu 

– MWCNT can obtain 2.4 times higher Q factor than that of Cu 

– Even for higher resistivity case (D=10 nm), still have higher Q 

– Indicating reduced skin effect has significant impact 



Q Factor Comparison (Ultra High-Frequency) 


Quality Factor 

100 

80 

60 

40 

ρ sub 

= 10 Ω-cm 

Cu 

SWCNT Fm=1/3 

SWCNT Fm=1 

MWCNT D=10nm 

MWCNT D=20nm 

MWCNT D=40nm 

60GHz 

231% 

20 

0 

1 10 100 


• Advantage of CNT is enhanced for ultra-high 

high-frequency 

applications 

• Maximum Q factor enhancement is 3.3 times! 



CNT Based Capacitor 

Expectation of CNT capacitor: 

• High density due to small form factor of CNTs 

• High aspect ratio, especially for DRAM applications 

• Lower electrode resistance 

• Higher Q factor 

• Higher switching speed 

Important concern: 

• Lower leakage current 



Fabricated MWCNT Based Capacitor 

6.5fF/μm 2 

10 μm 

1e -8 A/cm 2 

(ITRS 2014) 

J. E. Jang, et.al., ESSDERC, 2005 

Diameter: 70nm 

Height of MWCNT: 3.5um 

Insulator thickness: 65nm 


Can not match the ITRS requirement at 2014, 

need more efforts… 


CNT Based Capacitors 

Take advantage of bottom up approach to achieve high aspect ratio… 

210 nm 


20 nm 

480 nm 

Circular 

(a) Circular 

Height = 1 μm 

Square 

(Dense, d = 0.34 nm) 

Square 

(Sparse, d = 20 nm) 

20 nm 

Electrostatic capacitance 

density (fF/μm 2 ) 

31.76 

39.48 

30.25 

Total effective capacitance 

density (including C Q 

, 

fF/μm 2 ) 

30.65 

38.39 

28.99 

Much larger than ITRS requirement for 2014: 7 fF/μm 2 



CNT Off-chip Applications 

Some Concerns and Requirements 

• Form factor: 

– Number of I/O pads 

– Area of pads 

– Smaller form factor is required 

• Low parasitics: 

– Lower inductance 

– Lower noise 

• Good thermal properties 

– Heat dissipation 

• High predictability 

– Easier to model and design 

• High reliability 

– Electromigration 

– Thermal/Mechanical 



Example 1: Flip-chip Bumps 

T. Iwai et al., IEDM., 2005 (Fujitsu) 

12μm 

MWCNT, D~10 nm 



Example 2: TIM for Packaging 

K. Zhang et al., ICEPT., 2006 (HKUST) 


MWCNT, D= 20-30 nm 

Length ~ 50 μm 


Example 3: Chip Cooling K. Kordas et al., APL, 2007 (RPI) 

MWCNT, Length~1.2 mm, D= 10-90 nm 

CNT Heat Spreader, 1*1 mm 

N 2 gas flow 



CNT Transfer Tech. 

L. Zhu et al., Nano Lett., 2006; 

L. Zhu et al., MRSSP, 2007 

• High temperature CVD 

growth (@ 775 o C) 

• Open-ended 

ended CNTs 

• Low temperature 

bonding (@ 270 o C) 

• Substrate is Cu 

CNTs break along the 

axis rather than at the 

CNT-solder interface 

Open-ended CNTs 


Closed-ended CNTs 


CNT Vias in 3D-IC Applications 

CNT through-wafer via 

• High aspect ratio (>10) 

• Long length (>100 μm) 

Process steps: 

1 

2 

3 

4 

5 

Through holes in the top wafer 

Bonding layer is deposited onto 

top wafer 

Catalyst film is deposited onto the 

bottom layer 

Two wafers are bonded together 

Grow CNT via thermal CVD 

T. Xu et al., APL., 2007 



CNT NEMS…. 

CNT-based Relay 

H. Dadgour et al., IEDM, 2008 

Lee, et al. Appl. Phys. 2003 

• CNT NEMS can operate in GHz range due to very small mass 



ESD Metal Current Density 

C. Duvvury, IEDM., 2008 

• Failure current decreases with scaling 

• High current carrying capability material will be preferred 



Using CNT to Enhance Charge 

Dissipation 

• The rate of charge dissipation is governed by 

τ=ρε 

– ρ, , resistivity of material 

– ε, , permittivity of material 

• Applications in Polymer filling 

– By filling MWCNT, it will 

• ρ is small since MWCNT has good conductance 

• ε is small since the filling fraction could be small due to its high h 

aspect ratio 

– Desirable for fast charge dissipation 

• One of the largest bulk application of CNTs today 

– Company: Hyperison Catalysis International 

Hyperion Catalysis (www.fibrils.com) 



ESD Protection Using MWCNTs in 

Polymer 

Hyperion Catalysis 

(www.fibrils.com) 



CNT Interconnects: System-Level 

Applications 

CNT Interconnect Enhanced: 

• Memory (Cache) design 

• FPGA design 

• Network-on 

on-chip design 

• Multi-core processor design 

Note: it is important to use the correct physical 

and compact models for CNT/GNR, depending 

on the application…. 



Summary 

1.4 

1.2 

1.0 

0.8 

0.6 

0.4 

d-GNR (p =0.41) 

d-GNR (p=1) 

SWCNT ( Fm=1) 

SWCNT ( Fm=1/3) 

DWCNT (D=1.5nm) 

MWCNT (D=14nm) 

Lower 

latency 

for long 

wires 

Negligible 

skin 

effects 

Resistance [Ω] 

20 

10 

8 

6 

4 

Cu wire 

SWCNT D=1nm, Fm=1 

MWCNT D=20nm 

MWCNT D=40nm 



100 1000 

Length of Interconnect [ m] 

2 

1 10 100 1000 


S 

W 

Metal 

Contact 

CNT 

Bundle 

Dout 

Promising for passive devices 

Off-Chip and 

Through-Silicon 

Vias 



Part II: References (1) 

CNT Modeling 

IEEE Trans. Electron Device, vol. 56, no. 10, Oct. 2009. 

H. Li, and K. Banerjee, “High-frequency analysis of carbon nanotube interconnects and implications ions for on-chip 

inductor design,” 

IEEE Trans. Electron Devices, vol. 56, no. 9, Sep. 2009 



Physics, Status and Prospects” 

IEEE Trans. Electron Devices, vol. 56, no. 8, pp. 1567-1578 1578 Aug 2009. 

C. Xu, , H. Li, and K. Banerjee, “Modeling, Analysis and Design of Graphene Nano-Ribbon Interconnects” 

IEEE Trans. Nanotechnology, vol. 8, no. 4, pp. 542-559, 559, July, 2009. 

N. Srivastav, , H. Li, F. Kreupl, , and K. Banerjee, “On the Applicability of Single-Walled Carbon Nanotubes as VLSI 

Interconnects” 

IEEE Trans. Electron Device, pp. 1328-1337, 1337, June, 2008. 

H. Li, W. Y. Yin, K. Banerjee, and J. F. Mao, “Circuit modeling and performance analysis of multi-walled carbon 

nanotube interconnects” 

Tech. Dig. IEDM 2007, pp. 207-210. 

210. 

H Li, N. Srivastava, J. F. Mao, W. Y. Yin, and K. Banerjee, “Carbon nanotube vias: : a reality check” 

Proc. of DAC 2006, pp. 880-885. 

885. 

K. Banerjee and N. Srivastava, “Are carbon nanotubes the future of VLSI Interconnections” 


260. 

N. Srivastava, R. V. Joshi and K. Banerjee, “Carbon nanotube interconnects: implications for performance, power 

dissipation and thermal management” 

Proc. of ICCAD 2005, pp. 383-390. 

390. 

N. Srivastava and K. Banerjee, “Performance analysis of carbon nanotube interconnects for VLSI applicationa 

pplication” 

IEEE Trans. Nanotechnology, vol. 1, no. 3, pp. 129-144, 144, 2002. 

P. J. Burke, “Luttinger liquid theory as a model of the gigahertz electrical properties p 

of carbon 

nanotubes” 



Part II: References (2) 

CNT Applications 

IEEE Trans. Electron Devices, vol. 56, no. 9, Sep. 2009 



Physics, Status and Prospects”. 


260. 

T. Iwai et al., Thermal and Source Bumps utilizing CNTs for Flip-chip High Power Amplifiers 

• Proc. of ESSDERC, Grenoble, France, 2005 

J. E. Jang, S. N. Cha, Y. Choi, , D.-J. Kang, D. G. Hasko, , and G. A. J. Amaratunga, “Nanoscale 

capacitors based on 

metal-insulator 

insulator-carbon 

naontbue-metal structures”. 

• Nano Letters, vol. 6, no. 2, pp. 243-247, 247, 2006 

L. Zhu, Y. Sun, D. W. Hess, and C. P. Wong, “Well-aligned open-ended ended carbon nanotube architectures: an approach 

for device assembly”. 

• Mater. Res. Soc. Symp. . Proc., 0990-B10 

B10-01, 01, 2007 

L. Zhu, D. W. Hess, and C. P. Wong, “Assembly of fine-pitch carbon nanotube bundles for electrical interconnect 

applications”. 

• Proc. of 7th Intl. Conf. Elect. Pack. Tehc. . 2006 

K. Zhang and M. M. F. Yuen, “Heat spreader with aligned CNTs designed for thermal management of HB-LED 

packaging and microelectronic packaging”. 

• IEEE Trans. Comp. & Pack. Tech., pp. 92-100, March 2007 

T. Tong, Y. Zhao, L. Delzeit, , A. Kashani, , M. Meyyappan, , and A. Majumdar, “Dense vertically aligned multiwalled 

carbon nanotube arrays as thermal interface materials”. 

• Applied Physics Letters, vol. 90, 123105, 2007 

R. Vajtai, , K. Kordas, , G. Toth, , P. Moilanen, , M. Kumpumaki, , J. Vahakangas, , and A. Uusimaki, , and P. M. Ajayan, “Chip 

cooling with integrated carbon nanotube microfin architectures”. 

• Applied Physics Letters, vol. 91, 042108, 2007 

T. Xu, , Z. Wang, J. Miao, X. Chen, C. M. Tan, “Aligned carbon nanotubes for through-wafer interconnects”. 



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