Chi-Leung (David) Wong - Polaris - University of Illinois at Urbana ...

Professional Activities
Reviewer for the Proceedings of the IEEE. Special Issue on Program Generation, Optimization, and Platform Adaptation
Reviewer for the EuroPar Conference and the International Conference on Parallel Architectures and Compilation
Techniques (PACT)
Reviewer for the International Conference for High Performance Computing and Communications (SC’02)
Reviewer for the Workshop on Languages and Compilers for Parallel Computing (LCPC’02)
Reviewer for the Workshop on Compilers for Parallel Computers (CPC’03)
Member of ACM
Publications
Zehra Sura, Xing Fang, Chi-Leung Wong, Samuel P. Midkiff and David Padua Compiler Techniques for High Performance
Sequentially Consistent Java Programs, Symposium on Principles and Practice of Parallel Programming
(PPoPP), June, 2005
Zehra Sura, Chi-Leung Wong, Xing Fang, Jaejin Lee, S.P. Midkiff, and David Padua, ”Automatic Implementation of
Programming Language Consistency Models”, 15th Workshop on Languages and Compilers for Parallel Computing
(LCPC), July, 2002
Chi-Leung Wong, Zehra Sura, Xing Fang, Jaejin Lee, Samuel Midkiff, David Padua, ”The Pensieve Project: A
Compiler Infrastructure for Memory Models”, Midwest Society for Programming Languages and Systems Workshop
(MSPLS), Bloomington, Indiana, April 2002
Chi-Leung Wong, Anthony Bolmarcich, Samuel Midkiff, Peng Wu, ”ROMable code Generation for Java”. under
preparation
Chi-Leung Wong, ”Source to Source Translation from Fortran 95 to Java and Evaluation of Translated Programs”,
under preparation