LRDIMM - Powers up Transaction Processing - Inphi Corporation

The results discussed above reflect the speed advantage of LRDIMM over RDIMM for systems with equal amounts of
DRAM installed, 512GB in this case, with LRDIMM running at 1333 MT/s compared to 1066 MT/s for RDIMM. For
benchmarks like TPC-E, and real-world applications where the database size is significantly larger than the installed
memory, LRDIMM would provide an additional performance advantage by allowing a higher amount of memory to be
installed at the same operational frequency, reducing the required hard disk access time by resolving more database
queries in DRAM.
The TPC-E benchmark also rates the server systems tested based on cost (in US dollars) per transaction per second,
or $/tpsE. By this metric, the LRDIMM system fared very well, ranking as the 8th lowest in $/tpsE out of 55 different
systems reported on the TPC website even using IBM’s list price of $4,599 at the time of the test. However, the price
of 32GB LRDIMM is coming down quickly. For example, IBM is now listing the 32GB LRDIMM for $2,099. Using this
price, the $/tpsE is approximately $196 thereby significantly improving the cost efficiency of the overall server as shown
in Table 2.
LRDIMM Overview
Table 2: USD $/tpsE
The LRDIMM enables the performance improvement observed in these TPC-E benchmark results by isolating multiple
ranks of DRAM behind a memory buffer such as Inphi’s iMB02-GS02A, as shown in Figure 3. In a traditional RDIMM
module the data bus signals from the host connect through the DIMM connector directly to the DRAM, placing multiple
DRAM loads on every data bit for multi-rank modules, including the DRAM loads from adjacent RDIMM modules in the
same memory channel. If four-rank RDIMMs are installed in a channel with two DIMM slots, each data bit would see
eight electrical loads, limiting signal integrity and system performance at higher speeds.
In an LRDIMM module the data bus signals from the host connect through the DIMM connector to the memory buffer,
which re-drives the data bus to the DRAM on the front and back sides of the module. The memory buffer thus isolates
the DRAM from the host, and from the DRAM on any adjacent LRDIMM module on the same memory channel. For
a system with two DIMM slots per channel, the memory controller would see two electrical loads (the memory buffer
on each LRDIMM), compared to eight electrical loads in an RDIMM system (the four ranks of DRAM on each RDIMM).
This load reduction enables the memory data bus to operate at higher speeds with no loss of signal integrity, providing
system performance benefits in memory intensive applications such as online transaction processing.
The LRDIMM’s memory buffer also buffers the command, address and control signals from the memory controller,
similar to the way that the register on an RDIMM buffers those signals. In systems with three DIMM slots per channel
the memory buffer enables additional increases in memory capacity, overcoming the traditional limit of eight chip selects
per channel through a feature called Rank Multiplication, allowing the use of three four-rank LRDIMM modules in a single
channel. Eight-rank LRDIMMs are also possible, with several module vendors having announced 64GB 8Rx4 LRDIMMs.
Figure 3: LRDIMM
LRDIMM Powers up Transaction Processing 4