Q&A Institute <strong>for</strong> Technical In<strong>for</strong>matics www.ITI.TUGraz.at Thanks <strong>for</strong> your attention! Questions A. Krieg 2011-9-29 26
References Institute <strong>for</strong> Technical In<strong>for</strong>matics www.ITI.TUGraz.at [Arden2010] [Jenn1994] [Velanzco2001] [Rothbart2004] [Karlsson1995] [Bayar2008] [Kenterlis2006] [Kafka2008] [Sterpone2007] [Sonza2006] [Baraza2005] [Leveugle2000] [Grinschgl2011] [Pohl2010] [Pellegrini2010] [Bachmann2010] [Genser2009] [JIL2009] [CCEVS2005] W. Arden, M. Brillouët, P. Cogez, M. Graef, B. Huizing, R. Mahnkopf: More-than-Moore, ITRS 2010. E. Jenn, J. Arlat, M. Rimen, J. Ohlsson, and J. Karlsson, “<strong>Fault</strong> injection into vhdl models: the mefisto tool,” in Proc. Twenty-Fourth Int <strong>Fault</strong>-Tolerant Computing FTCS-24. Digest of Papers. Symp, 1994, pp. 66–75. R. Velazco, R. Leveugle, and O. Calvo, “Upset-like fault injection in vhdl descriptions: A method and preliminary results,” in Proc. IEEE Int Defect and <strong>Fault</strong> Tolerance in VLSI Systems Symp, 2001, pp. 259–267. K. Rothbart, U. Neffe, C. Steger, R. Weiss, E. Rieger, and A. Muehlberger, “High level fault injection <strong>for</strong> attack simulation in smart cards,” in Proc. 13th Asian Test Symp, 2004, pp. 118–121. J. Karlsson and P. Folkesson, “Application of three physical fault injection techniques to the experimental assessment of the mars architecture.” IEEE Computer Society Press, 1995, pp. 267–287. S. Bayar and A. Yurdakul, “Self-reconfiguration on spartan-iii fpgas with compressed partial bitstreams via a parallel configuration access port (cpcap) core,” in Proc. Ph.D. Research in Microelectronics and Electronics PRIME 2008, 2008, pp. 137–140. P. Kenterlis, N. Kranitis, A. Paschalis, D. Gizopoulos, and M. Psarakis, “A low-cost seu fault emulation plat<strong>for</strong>m <strong>for</strong> sram-based fpgas,” in Proc. 12th IEEE Int. On-Line <strong>Testing</strong> Symp. IOLTS 2006, 2006. L. Kafka, “Analysis of applicability of partial runtime reconfiguration in fault emulator in xilinx fpgas,” in DDECS ’08: Proceedings of the 2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems. Washington, DC, USA: IEEE Computer Society, 2008, pp. 1–4. L. Sterpone and M. Violante, “A new partial reconfiguration-based fault-injection system to evaluate seu effects in sram-based fpgas,” Nuclear Science, IEEE Transactions on, vol. 54, no. 4, pp. 965 –970, 2007. M. Sonza Reorda, L. Sterpone, M. Violante, M. Portela-Garcia, C. Lopez-Ongil, and L. Entrena, “<strong>Fault</strong> injection-based reliability evaluation of sopcs,” in Proc. Eleventh IEEE European Test Symp. ETS ’06, 2006, pp. 75–82. J. C. Baraza, J. Gracia, D. Gil, and P. J. Gil, “Improvement of fault injection techniques based on vhdl code modification,” in Proc. Tenth IEEE Int. High-Level Design Validation and Test Workshop, 2005, pp. 19–26. R. Leveugle, “<strong>Fault</strong> injection in vhdl descriptions and emulation,” in Proc. IEEE Int Defect and <strong>Fault</strong> Tolerance in VLSI Systems Symp, 2000, pp. 414–419. J. Grinschgl, A. Krieg, C. Steger, R. Weiss, H. Bock, and J. Haid, “Modular fault injector <strong>for</strong> multiple fault dependability and security evaluations,” in DSD 2011, In Press. C. Pohl, R. Fuest, and M. Porrmann, “vmagic – automatic code generation <strong>for</strong> vhdl,” newsletter edacentrum, vol. 2, pp. 7–10, Jul. 2010. A. Pellegrini, V. Bertacco, and T. Austin, “<strong>Fault</strong>-based attack of rsa authentication,” in Proc. Design, Automation & Test in Europe Conf. & Exhibition (DATE), 2010, pp. 855–860. C. Bachmann, A. Genser, C. Steger, R. Weiss, and J. Haid, “Automated Power Characterization <strong>for</strong> Run-Time Power <strong>Emulation</strong> of SoC Designs,” in DSD 2010, 2010, pp. 587–594. A. Genser, C. Bachmann, J. Haid, C. Steger, and R. Weiss, “An emulation-based real-time power profiling unit <strong>for</strong> embedded software,” in SAMOS 2009, 2009, pp. 67–73. Joint Interpretation Library, “Application of <strong>Attack</strong> Potential to Smartcards,”, 2009,online available on https://www.bsi.bund.de National In<strong>for</strong>mation Assurance Partnership Common Criteria Evaluation and Validation Scheme, “Common Criteria Evaluation and Validation Scheme Validation Report”, 2005, online available onhttp://www.commoncriteriaportal.org/files/epfiles/st_vid10023-vr.pdf A. Krieg 2011-9-29 27