Automatized Fault Attack Emulation for Penetration Testing

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Automatized Fault Attack Emulation for
Penetration Testing
Johannes Grinschgl 1 , Thomas Aichinger 3 , Armin Krieg 1 ,
Christian Steger 1 , Reinhold Weiss 1 ,
Holger Bock 2 , Josef Haid 2
1
Institute for Technical Informatics, Graz University of Technology, Austria
2
Infineon Technologies Austria AG, Design Center Graz, Austria
3
Austria Card GmbH, Austria
12th International Common Criteria Conference
Kuala Lumpur, Malaysia, September 29, 2011
A. Krieg 2011-9-29
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Agenda
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• Motivation
• Introduction
• Related work
• Automatized Fault Attack Emulation
• Impact on Certification Flow
• Conclusion
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Motivation (1/3)
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• Increasing complexity of SoC
− More-than-Moore [Arden2010]
− Increasing test duration
• Increasing security and
dependability requirements
− High costs
− Loss of trust
− Loss of life
SOC Consumer Portable Design Complexity Trends
(Source: ITRS - 2010 Update, "System Drivers“)
• Increasing number of known fault attacks
− Increasing knowledge of attackers
− Better attack tools
− Cheaper analysis equipment
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Motivation (2/3)
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• Common criteria certification
− Time consuming
− Expensive
− Penetration tests very late in
development phase
• Fault detection during certification
− Longer time to market
− Reevaluation
• Test coverage of penetration tests
• Efficiency evaluation of new
security features
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Motivation (3/3)
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• How to solve this problem
• Target:
− Reduction of deficits during design phase
− Early evaluation of security features
− Support of very large test pattern sets
− Open sample evaluation support
− SW test without HW security features
− (HW test without SW security features)
• Solution:
Automatized Fault
Attack Emulation
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Agenda
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• Motivation
• Introduction
• Related work
• Automatized Fault Attack Emulation
• Impact on Certification Flow
• Conclusion
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Introduction (1/2)
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• Emulation
− Mapping of smart card
functionality to FPGA
− Emulation resembles very
accurately the behavior of
the final device
− Extendibility in respect to
fault emulation
− Real-time emulation
performance
− On-line debugging
− On-line register and memory
examination
− Standard SW development
tool
Easy-to-use Rapid FPGA Prototyping Platform,
Tanto2-FPGA system, http://www.hitex.com
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Introduction (2/2)
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• POWER-MODES 1 vision: Flexible and Fast Fault Emulator
− Whole system evaluation for fault attack vulnerability
− Software
− Hardware
− Operating system
− Saboteur-based attack method
− Automatized VHDL code base adaptation
− Automatized result evaluation
− Austria Card ACOS operating system
1
“POWer EmulatoR and MOdel based DEpendability and Security evaluation platform”, funded by the Austrian Federal
Ministry for Transport, Innovation, and Technology under the FIT-IT contract FFG 825749. Project Partners: Infineon
Technologies Austria AG and Austria Card
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Agenda
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• Motivation
• Introduction
• Related work
• Automatized Fault Attack Emulation
• Impact on Certification Flow
• Conclusion
A. Krieg 2011-9-29
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Related Work (1/2)
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• Fault injection mechanisms
− Simulation [Jenn1994, Velanzco2001, Rothbart2004]
• Slow
• Flexible
− Physical test [Karlsson1995]
• Late in design phase
• Expensive
− Emulation [Bayar2008, Kenterlis2006, Kafka2008, Sterpone2007, Sonza2006, Baraza2005,
Leveugle2000]
• Fast
• Low-cost compared to physical tests
• Compromise between cost and flexibility
• Early in design phase
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Related Work (2/2)
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• Fault emulation methods
− Partial reconfiguration [Bayar2008, Kenterlis2006, Kafka2008, Sterpone2007,
Sonza2006]
• Runtime adaptation of LUTs
• Requires specialized FPGA devices
− Mutants
• VHDL modification to modules [Baraza2005, Leveugle2000]
• Requires pre-modified modules for every fault scenario
− Saboteur
• VHDL modification into signal lines [Baraza2005, Leveugle2000]
• Very flexible if supported by automatized placement
• Common Criteria Certification Process [JIL2009], [CCEVS2005]
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Agenda
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• Motivation
• Introduction
• Related work
• Automatized Fault Attack Emulation
• Impact on Certification Flow
• Conclusion
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Autom. Fault Attack Emulation (1/5)
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• Host PC
− Fault injection flow control
• Attack Database
− Storage of different attack scenarios
• Fault injection controller
− Saboteur
Management
• Saboteurs
− Single-bit type
− Bus type
− Port type
• Saboteur interface
− Saboteur FI controller connection
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Autom. Fault Attack Emulation (2/5)
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• What are saboteurs
− Modules which can disturb signals
− Placed between signal source and sink
• Advantages
− Definable detailed attack
− Full control over the signal
− Flexibility
− Applicable to Security and
Dependability Evaluations
• Attack patterns
− Specification of fault location
− Mapping of physical to logical location
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Autom. Fault Attack Emulation (3/5)
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• Fault emulation
initialization
−
−
−
Attack time
Attack type
Memory address
• Attack scenario
• Result evaluation
−
−
Output
Memory
• Report generation
• Repeat until all
addresses and points in
time are tested
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Autom. Fault Attack Emulation (4/5)
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• Attack on security relevant regions
− Memory regions
− Time
− Calculation example
• Some 100 Addresses
• 20-50ms for one command
• ~1ms is interesting
• ~1M Attack Scenarios
• 1sec per attack
• 11,6 Days
− Long time tests
• Attack granularity
refinement
• Information gain for
real-chip testing
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Autom. Fault Attack Emulation (5/5)
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• Power emulation
[Bachmann2010]
−
−
−
−
Automatized control
signal extraction
Control signal
weighting
Accumulation
Characterization using
gate level simulations
and physical tests
• Information extraction
from the power profile
• Emulate power
information available to
attacker
−
Average error below
10%
Power [normalized]
1
Equipment
0.8
0.6
0.4
0.2
P
estimated
∑
= c * x[
t]
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Time [normalized]
[Genser2009]
i
i
Reference
Estimated
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Agenda
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• Motivation
• Introduction
• Related work
• Automatized Fault Attack Emulation
• Impact on Certification Flow
• Conclusion
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Impact on Certification Flow (1/3)
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Impact on smart card embedded SW development
• SW evaluation without activated HW security features
− Evaluation of SW security implementation
− Automated verification of SW countermeasure implementation
and test replication using HW with enabled security features
− Testing of security relevant code is difficult (practical
experience)
• Coding guideline verification
− E.g. SW handling of memory manipulations
− E.g. Detection of program counter manipulations
• Replicable penetration test
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Impact on Certification Flow (2/3)
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Impact on certification (penetration tests)
• Advantages for the lab
− Gain information for physical attacks
• Attack time
• Attack region (RAM, Core, …)
• No blocking of expensive laboratory equipment
• Enabling of parallel test scenarios
• Certain HW security features can be deactivated
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Impact on Certification Flow (3/3)
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• Use the emulator as open sample/ sample with known secrets
• Freely configurable hardware
− Internal values can be read out and manipulated
• Registers
• Memory
• Program counter
− Hardware security features can be deactivated
• Memory encryption
• Fault detection mechanisms
− Manipulation of critical signals
• Fault detection mechanisms
• Crypto calculation
• Freely definable software load
− Debugging is possible
− Get memory location of critical code
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Agenda
Institute for Technical Informatics
www.ITI.TUGraz.at
• Motivation
• Introduction
• Related work
• Automatized Fault Attack Emulation
• Impact on Certification Flow
• Conclusion
A. Krieg 2011-9-29
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Conclusion (1/3)
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• SW development view
− Test security features
− Verification of coding guideline
− Allow to debug SW
• Open sample approach
− Specific deactivation of HW security features
− Allow to test SW on the HW
− Allow to manipulate HW features
• Run-time power estimation
− Extract interesting time slots
• E.g. Cryptographic calculations
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Conclusion (2/3)
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• Provide information for real chip certification
− Attack time
− Attack region
• RAM, Core, Crypto, …
• Speed-up of security evaluation
− Simple tests can already be performed during SW development
− Provide information for the real tests
− Test counter measures
− Detailed attack result evaluation by memory analysis
• Enabling of complex fault attack scenarios
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Conclusion (3/3)
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• Future Work
− More detailed result evaluation
− Multiple FPGA configurations for parallel emulation
− Automatic increase of test granularity at critical regions
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Q&A
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Thanks for your attention!
Questions
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References
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[Arden2010]
[Jenn1994]
[Velanzco2001]
[Rothbart2004]
[Karlsson1995]
[Bayar2008]
[Kenterlis2006]
[Kafka2008]
[Sterpone2007]
[Sonza2006]
[Baraza2005]
[Leveugle2000]
[Grinschgl2011]
[Pohl2010]
[Pellegrini2010]
[Bachmann2010]
[Genser2009]
[JIL2009]
[CCEVS2005]
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