PSL â Property Specification Language - OCP-IP

OCP PSL Package 

Copyright © 2002-2006 Nokia Corporation. This file is subject to the 

terms and conditions included in the license.txt file [located at the 

root level of this directory/included in set of files to which this file 

belongs] (the "License Terms"); You may not use this file except in 

compliance with the License Terms." 

1 © 2005 Nokia OCP PSL Package Introduction.ppt / 2006-05-12 / S.M

Content 

ABV – Assertion-Based Verification 

PSL – Property Specification Language 

Motivation, Requirements & Content 

Verification Flow 

Installation & Integration 

Known Problems and Limitations 

Present & Future 

Conclusions 



• The purpose is to convert functional features of a specification into explicit 

hardware properties 

• An assertion can be considered as an implementation of a property 

• Several languages are available for implementation (e.g. PSL, SystemVerilog, 

the e language, OpenVera, …) 

• Assertions describe the behaviour of logic over time 

• Assertions can be compiled and simulated as HDL descriptions 

• Fully automatic verification method 

• Increased visibility & simplified debugging 

• The target is to improve both verification quality and efficiency! 



ALU ALU ALU 

Test Bench 

OCP 

Register IF 

Register IF 

ALU ALU ALU 

It is very difficult to backpropagate 

bugs of internal 

components! 

Bugs of an interconnection 

might lead to a complete 

verification nightmare! 

ALU ALU ALU 

FSM 

Assertions trigger 

immediately and bring 

bugs closer to their source! 



• Hardware property (not verification) language! 

• Utilized to implement assertions (not test benches)! 

• The purpose is to complement the traditional methodologies 

• Consistent, simple, and powerful language 

• Declarative and structural syntax 

• Very low learning threshold 

• Four (4) different layers enable sustainable verification environments 

• VHDL and Verilog flavors are provided 

• Widely accepted standard from Accellera and IEEE 



Boolean expressions i.e. a state of the DUV 

property EXAMPLE is 

never {a = ‘1’ and b = ‘1’}; 

Sequential expressions i.e. a sequence of states of the DUV 

property EXAMPLE is 

always {a = ‘0’ and b = ‘0’} |-> -- Precondition 

{c = ‘0’ and d = ‘0’; -- Consequence 

c = ‘1’ and d = ‘1’ [*2]; 

c = ‘0’ and d = ‘0’}; 

Both legal and illegal states or sequences of states can be determined! 



“No ‘X’ or ‘Z’ on the master addr (MAddr) during the request phase” 

property OCPPSL_MADDR_ISUNKNOWN is 

never {MCmd /= OCP_IDLE and isunknown(MAddr)}; 

“The master address (MAddr) must remain stable during the request phase” 

property OCPPSL_MADDR_STABLE is 

always {MCmd /= OCP_IDLE} |-> 

{{SCmdAccept = ‘1’} | 

{[*1];SCmdAccept = ‘0’ and stable(MAddr) [*]; 

SCmdAccept = ‘1’ and stable(MAddr)}}! 

abort(MReset_n = RESET_ACTIVE); 


Motivation 

• Since the number of intellectual property (IP) cores tends to increase, it has 

become vital to verify interconnections 

• VHDL or Verilog monitors are not cost-effective 

• Verification languages (e.g. the e language and OpenVera) have been available, 

but no widely accepted standards 

• Tool dependent monitors are out of the question 

• Ad-hoc methods have been utilized 

• Verification quality has been found more or less inadequate. 

• Sustainability has been found insufficient 

• There is a clear demand for new kind of verification packages! 


Requirements 

• Verifies the compatibility of the interconnection with the OCP 2.1 

• Implementation based on open standards 

• Compatible with the existing design and verification flow 

• Can be configured according to the DUV 

• Can be installed with minimal efforts without access to the source 

• No previous knowledge is required 

• Only a VHDL simulator is required 

• Cost-effective in terms of maintenance and support 

• Completely reusable 


Content 

• 242 assertions divided to six (6) groups 

• Basic signals 55 

• Simple extensions 24 

• Burst extensions 109 

• Tag extensions 15 

• Thread extensions 16 

• Sideband signals 23 

• 92 coverage points divided to three (3) groups 

• Basic signals 19 

• Simple extensions 9 

• Burst extensions 64 


Verification Flow 

Design 

RTL 

Test cases 

YES 

NO 

Violations? 

Simulate 

RTL 

NO 

Coverage 

YES 

READY 

Complete? 


Simulation Performance 

• Exhaustive testing in a verification environment 

• 6,340 independent requests 

• 75 burst sequences containing 19,020 requests 

• The CPU time when assertions disabled 132.83s 

• The CPU time when assertions enabled 143.42s 

• The performance penalty equals to 8.0% 

• Very moderate, because the worst-case scenario was applied 

• Note that results might vary between different simulators 


Installation 

• The package consists of templates and must be modified according to the DUV 

• The user must … 

• set the parameters of the interconnection 

• set the entity and architecture pair of verification units 

• replace the names of the signals 

• Remove assertions and sequences that contain unconnected signals 

• Note! The following signals must be determined: 

• Clk, MReset_n 

• MCmd, MAddr, MData 

• SCmdAccept, SResp, SData 

• Otherwise auxiliary signals tied to default value must be implemented. 


Integration 


Master 


Slave 


Slave 

OCP 2.1 Interconnection 

Violations? 

Error msg 

PSL 

Assertions 


Known Problems and Limitations 

• The support for the memory locks and reservation tags of the lazy 

synchronization is missing 

• The support of the tag and thread extensions is very limited 

• The current release does not operate correctly if there are pending transactions 

from multiple tags or threads 


Conclusions 

• The package increases both verification quality and efficiency 

• Straightforward installation and integration 

• Fully automatic verification method 

• Increased visibility & simplified debugging 

• Very moderate performance penalty (max 8.0%)

PSL â Property Specification Language - OCP-IP

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