Chapter 3 Testability Measure.pdf
Chapter 3 Testability Measure.pdf
Chapter 3 Testability Measure.pdf
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RTL <strong>Testability</strong> Analysis - Example<br />
Design for <strong>Testability</strong><br />
The probability-based 0-controllability of each output l,<br />
denoted by C0(l), in the n-bit ripple-carry adder is 1- C1(l).<br />
O(l, s i ) is defined as the probability that a signal change on<br />
l will result in a signal change on s i .<br />
Since O(a i , s i ) = O(b i , s i ) = O(c i , s i ) = O(s i )<br />
where i=0, 1, ... , n -1<br />
<strong>Testability</strong> Analysis to guide the DFT design<br />
Ad hoc DFT<br />
» Effects are local and not systematic<br />
» Not methodical<br />
» Difficult to predict<br />
A structured DFT<br />
» Easily incorporated and budgeted<br />
» Yield the desired results<br />
» Easy to automate<br />
P.L.Lai, VLSI Testing 2010 <strong>Chapter</strong> 3-29<br />
P.L.Lai, VLSI Testing 2010 <strong>Chapter</strong> 3-30
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