Chapter 3 Testability Measure.pdf

VLSI Testing 

( 積體電路測試 ) 

Chapter 3 

Testability Measure 

Testability Measures 

SCOAP Algorithm 

An Example 

Test Points in Hardware 

Outline 

Ping-Liang Lai ( 賴秉樑 ) 

Department of Electronic Engineering, Notional Chin-Yi University of Technology 

P.L.Lai, VLSI Testing 2010 Chapter 3-2 

Attempt to Assess Testability 

Test pattern generation requires: 

Controllability: controlling a point in the circuit from the primary inputs 

Observability: observing the results at primary output 

For examples, controlling the output of a multi-input AND gate to 1 

requires the control of all its inputs to 1, whereas for an OR gate, it is 

sufficient only one of the inputs to 1 

1 

1 

1 

1 

Assessing the controllability of this point and its observability 

can be helpful in determining the ease or difficulty of its 

“testability”. (also important to DFT) 

Hence the notion of Testability Measures (TM) 

0 

0 

1 

1 

Testability Measures (1/3) 

Three measures for combinational and another three 

for sequential circuits 

Combinational TM (major illustration in here) 

CC0: Combinational Controllability to 0 

CC1: Combinational Controllability to 1 

CO : Combinational Observability 

Sequential TM 

SC0: Sequential Controllability to 0 

SC1: Sequential Controllability to 1 

SO : Sequential Observability 


P.L.Lai, VLSI Testing 2010 Chapter 3-4



Testability measures used to get approximate measure of: 

Difficulty of setting internal circuit lines to 0 or 1 by setting primary 

circuit inputs 

Difficulty of observing internal circuit lines by observing primary 

outputs 

This knowledge can be used to: 

Provided analysis of difficulty of testing internal circuit parts, might 

require redesigning or addition of special testing hardware 

Provides guidance for algorithms performing test pattern generation, 

avoid using hard-to-control lines 

Provides an estimation of fault coverage 

Provides an estimation of test vector length 

Controllability: difficulty in setting a particular circuit node to 0 or 1 

Observability: difficulty of observing the state of a logic signal 


 

 

Testability analysis attributes: 

Involves circuit topology analysis, but no test vectors 

It has linear complexity, otherwise it is pointless and one might as well 

use automatic test pattern generation (ATPG) algorithms 

The origin of testability measures is in control theory. Several 

algorithms have been proposed: 

Rutman 1972: first definition of controllability 

Goldstein 1979: SCOAP 

 

 

 

» First definition of observability 

» First elegant formulation 

» First efficient algorithm to compute controllability and observability 

Parker and McCluskey 1975: definition of probabilistic controllability 

Brglez 1984: COP 

» First probabilistic measures 

Seth, Pan and Agrawal 1985: PREDICT 

» First exact probabilistic measures 


Testability Analysis - SCOAP 

SCOAP Controllability (1/2) 

Goldstein's algorithm: SCOAP 

We will focus mainly on combinational circuits 

 

Controllabilities: set Primary Input (PI) controllabilities to 1, progress 

from PIs to Primary Outputs (POs), add 1 to account for logic depth 

General rules for setting controllabilities 

 

If only one input sets gate output: 

» Output controllability = min (input controllabilites) + 1 

If all inputs set gate output: 

» Output controllability = sum (input controllabilities) + 1 

If gate output is determined by multiple input sets, e.g., XOR: 

» Output controllability = min(controllabilities of input sets) + 1 

CC0(a), CC1(a) 

CC0(b), CC1(b) 

a 

b 

a 

b 

a 

b 

a 

b 

a 

b 

a 

b 

z 

z 

z 

z 

z 

z 

CC0(z)=min{(CC0(a), CC0(b)}+1 

CC1(z)=CC1(a)+CC1(b)+1 

CC0(z)=CC0(a)+CC0(b)+1 


CC0(z)=min{(CC0(a)+CC0(b), CC1(a)+CC1(b)}+1 

CC1(z)= min{(CC1(a)+CC0(b), CC0(a)+CC1(b)}+1 

CC0(z)=CC1(a)+CC1(b)+1 



CC1(z)=CC0(a)+CC0(b)+1 

CC0(z)=min{(CC1(a)+CC0(b), CC0(a)+CC1(b)}+1 

CC1(z)= min{(CC0(a)+CC0(b), CC1(a)+CC1(b)}+1 

a 

z 

CC0(z)=CC1(a)+1 

CC1(z)=CC0(a)+1 



SCOAP Controllability (2/2) 

SCOAP Observability (1/2) 

 

Combinational Controllability Calculation Rules 

 

Observabilities: after controllabilities have been computed, set PO observabilities to 

0, progress from POs to PIs, add 1 to account for logic depth 

0-controllability 

(Primary input, output, branch) 



 

The difficulty of observing a designated input to a gate is the sum of 

The output observability 

Primary Input 1 1 

 

 

The difficulty of setting all other inputs to non-dominant values 

And 1 for the logic depth 

AND min {input 0-controllabilities} + 1 Σ(input 1-controllabilities) + 1 

OR Σ(input 0-controllabilities) + 1 min {input 1-controllabilities} + 1 

NOT Input 1-controllability + 1 Input 0-controllability + 1 

CC0(a), CC1(a) 

CC0(b), CC1(b) 

CO(a) 

CO(b) 

CO(a)=CO(z)+CC1(b)+1 

CO(b)=CO(z)+CC1(a)+1 

NAND Σ(input 1-controllabilities) + 1 min {input 0-controllabilities} + 1 

NOR min {input 1-controllabilities} + 1 Σ(input 0-controllabilities) + 1 



BUFFER Input 0-controllability + 1 Input 1-controllability + 1 

XOR 

min {CC1(a)+CC1(b), CC0(a)+CC0(b)} 

+ 1 

min {CC1(a)+CC0(b), 

CC0(a)+CC1(b)} + 1 

CO(a)=CO(z)+min{(CC0(b), CC1(b)}+1 

CO(b)=CO(z)+min{(CC0(a), CC1(a)}+1 

XNOR 

min {CC1(a)+CC0(b), CC0(a)+CC1(b)} 

+ 1 

min {CC1(a)+CC1(b), 

CC0(a)+CC0(b)} + 1 

Branch Stem 0-controllability Stem 1-controllability 





SCOAP Observability (2/2) 

An Example of Combinational Circuit (1/3) 

Combinational Controllability Observability Rules 

Observability 

(Primary output, input, stem) 

Primary Output 0 

AND / NAND Σ(output observability, 1-controllabilities of other inputs) + 1 

OR / NOR Σ(output observability, 0-controllabilities of other inputs) + 1 

A 

B 

G1 

G2 

H 

F 

G4 

Y 

NOT / BUFFER Output observability + 1 

XOR / XNOR 

Stem 

a: Σ(output observability, min {CC0(b), CC1(b)}) + 1 

b: Σ(output observability, min {CC0(a), CC1(a)}) + 1 

min {branch observabilities} 

C 

G3 

G 

G5 

Z 

a, b: inputs of an XOR or XNOR gate 





First, calculate the TM for the nodes on the 

second level, F, H, and G 

1.CC1(F)=CC1(A)+CC1(B)+CC1(C)+1=4 

2.CC0(F)=min{CC0(A), CC0(B), CC0(C)}+1=2 

3.CC1(H)=min{CC0(A), CC0(B)}+1=2 

4.CC0(H)=CC1(A)+CC1(B)+1=3 

5.CC1(G)=CC0(C)+1=2 

6.CC0(G)=CC1(C)+1=2 

These TM values are then used in calculating 

the primary output controllability 

7.CC1(Y)=min{CC1(F), CC1(H)}+1=3 

8.CC0(Y)=CC0(F)+CC0(H)+1=6 

9.CC1(Z)=min{CC0(H), CC0(G)}+1=3 

10.CC0(Z)=CC1(H)+CC1(G)+1=5 

A 

B 

C 

G1 

G2 

G3 

H 

F 

G 

G4 

G5 

Y 

Z 

The observability of a node indicates the 

effort needed to observe the logic value on 

the node at a primary output 

For second level, 

11.CO Y (F)=CO(Y)+CCO(H)+1=5 

12.CO Z (G)=CO(Z)+CC1(H)+1=4 

13.CO Y (H)=CO(Y)+CC0(F)+1=4 

14.CO Z (H)=CO(Z)+CC1(G)+1=5 

For primary inputs, 

15. CO Z (C)=CO Z (G)+1=[CO(Z)+CC1(H)+1]+1 =5 

(line C) 

16. CO Y (C)=CO Y (F)+CC1(A)+CC1(B)+1 

=[CO(Y)+CC0(H)+1]+CC1(A)+CC1(B)+1=8 

(line C) 

17.CO YH (A)=CO Y (H)+CC1(B)+1=6 

18.CO Z (A)=CO Z (H)+CC1(G)+1=8 

A 

B 

C 

CC1(F)=4 

CC0(F)=2 

CC1(H)=2 

CC0(H)=3 

CC1(G)=2 

CC0(G)=2 

CC1(Y)=3 

CC0(Y)=6 

CC1(Z)=3 

CC0(Z)=5 

G1 

G2 

G3 

H 

F 

G 

G4 

G5 

Y 

Z 



SCOAP for Sequential Circuit (1/5) 

Sequential controllability and observability calculation 

The combinational and sequential 

controllability measures of signal d: 

CC0(d)=min{CC0(a), CC0(b)}+1 

SC0(d)=min{SC0(a), SC0(b)} 

CC1(d)=CC1(a)+CC1(b)+1 

SC1(d)=SC1(a)+SC1(b) 


The combinational and sequential controllability and 

observability measures of q: 

 

 

 

 

CC0(q)=min{CC0(d)+CC0(CK)+CC1(CK)+CC0(r), CC1(r)+CC0(CK)} 

SC0(q)=min{SC0(d)+SC0(CK)+SC1(CK)+SC0(r)+1, SC1(r)+SC0(CK)} 

CC1(q)=CC1(d)+CC0(CK)+CC1(CK)+CC0(r) 

SC1(q)=SC1(d)+SC0(CK)+SC1(CK)+SC0(r)+1 

SCOAP sequential circuit example 




The data input d can be observed at q by holding the reset 

signal r at 0 and applying a rising clock edge to CK: 

 

 

CO(d)=CO(q)+CC0(CK)+CC1(CK)+CC0(r) 

SO(d)=SO(q)+SC0(CK)+SC1(CK)+SC0(r)+1 

Signal r can be observed by first setting q to 1, and then 

holding CK at the inactive state 0: 


Two ways to indirectly observe the clock signal CK at q: 

Set q to 1, r to 0, d to 0, and apply a rising clock edge at CK 

Set both q and r to 0, d to 1, and apply a rising clock edge at CK 

CO(CK)=CO(q)+CC0(CK)+CC1(CK)+CC0(r)+min{CC0(d)+CC1(q), 

CC1(d)+CC0(q)} 

SO(CK)=SO(q)+SC0(CK)+SC1(CK)+SC0(r)+min{SC0(d)+SC1(q), 

SC1(d)+SC0(q)}+1 

 

 

CO(r)=CO(q)+CC1(q)+CC0(CK) 

SO(r)=SO(q)+SC1(q)+SC0(CK) 




The combinational and sequential observability measures for 

both inputs a and b: 

 

 

 

 

CO(a)=CO(d)+CC1(b)+1 

SO(a)=SO(d)+SC1(b) 

CO(b)=CO(d)+CC1(a)+1 

SO(b)=SO(d)+SC1(a) 

Probability-Based Testability Analysis 

Used to analyze the random testability of the circuit 

 

 

 

C0(s): probability-based 0-controllability of s 

C1(s): probability-based 1-controllability of s 

O(s): probability-based observability of s 

Range between 0 and 1 

C0(s) + C1(s) = 1 




Probability-based controllability calculation rules 


Probability-based controllability calculation rules 





Primary Input p 0 p 1 =1–p 0 

AND 1 – (output 1-controllability) Π (input 1-controllabilities) 

OR Π (input 0-controllabilities) 1 – (output 0-controllability) 

NOT Input 1-controllability Input 0-controllability 

NAND Π (input 1-controllabilities) 1 – (output 0-controllability) 

NOR 1 – (output 1-controllability) Π (input 0-controllabilities) 

BUFFER Input 0-controllability Input 1-controllability 

XOR 1 – 1-controllabilty Σ (C1(a) × C0(b), C0(a) ×C1(b)) 

XNOR 1 – 1-controllability Σ (C0(a) × C0(b), C1(a) ×C1(b)) 

Primary 

Output 

AND / NAND 

OR / NOR 

NOT / 

BUFFER 

XOR / XNOR 

Stem 

Observability 

(Primary output, input, stem) 

1 

Π (output observability, 1-controllabilities of other inputs) 

Π (output observability, 0-controllabilities of other inputs) 

Output observability 

a: Π (output observability, max {0-controllability of b, 1-controllability of b}) 

b: Π (output observability, max {0-controllability of a, 1-controllability of a}) 

max {branch observabilities} 

Branch Stem 0-controllability Stem 1-controllability 

a, b: inputs of an XOR or XNOR gate 




Difference between SCOAP testability measures and 

probability-based testability measures of a 3-input AND gate 

1/1/3 

1/1/3 

1/1/3 

2/4/0 

0.5/0.5/0.25 

0.5/0.5/0.25 

0.5/0.5/0.25 

0.875/0.125/1 

Simulation-Based Testability Analysis 

Supplement to static or topology-based testability analysis 

Performed through statistical sampling 

Guide testability enhancement in test generation or logic 

BIST 

Generate more accurate estimates 

Require a long simulation time 

(a) SCOAP combinational measures 

(b) Probability-based measures 

 

v1/v2/v3 represents the signal’s 0-controllability (v1), 1- controllability 

(v2), and observability (v3) 



RTL Testability Analysis 

RTL Testability Analysis 

Disadvantages of Gate-Level Testability Analysis 

 

 

 

 

Costly in term of area overhead 

Possible performance degradation 

Require many DFT iterations 

Long test development time 

Advantages of RTL Testability Analysis 

 

 

 

 

Improve data path testability 

Improve the random pattern testability of a scanbased logic BIST 

circuit 

Lead to more accurate results 

» The number of reconvergent fanouts is much less 

Become more time efficient 

» Much simpler than an equivalent gate-level model 



RTL Testability Analysis - Example 


 

Ripple-carry adder composed of n full-adders 




Design for Testability 

The probability-based 0-controllability of each output l, 

denoted by C0(l), in the n-bit ripple-carry adder is 1- C1(l). 

O(l, s i ) is defined as the probability that a signal change on 

l will result in a signal change on s i . 

Since O(a i , s i ) = O(b i , s i ) = O(c i , s i ) = O(s i ) 

where i=0, 1, ... , n -1 

Testability Analysis to guide the DFT design 

Ad hoc DFT 

» Effects are local and not systematic 

» Not methodical 

» Difficult to predict 

A structured DFT 

» Easily incorporated and budgeted 

» Yield the desired results 

» Easy to automate

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