DEPFET Active Pixel Sensors for SuperBelle PXD - Belle II - KEK

1st Open SuperKEKB Collaboration Meeting, KEK, Dezember 2008 Ladislav Andricek, MPI fuer Physik, HLL 1 

DEPFET Active Pixel Sensors 

for SuperBelle PXD 

- Status Report- 

Ladislav Andricek for the DEPFET Collaboration (www.depfet.org)


Starting Point: The DEPFET ILC VTX Project 

10 groups from Germany, Spain, and Czech Republic ≈40-50 people working on the project 

new groups for SuperBelle: Japan, Hawaii, Poland, Austria 

See DEPFET Backup Document at www.depfet.org


DEPFET Principle 

DEpleted P-channel FET 

J. Kemmer & G. Lutz, 1987 

Drain 

Gate 

Source 

• fully depleted sensitive volume, charge collection by drift 

• internal amplification q-I conversion: 0.5 nA/e, scales with gate length and bias current 

• Charge collection in "off" state, read out on demand


An Array of DEPFETs 

Row wise read-out ("rolling shutter") 

• select row with external gate, read current, 

clear DEPFET, read current again 

the difference is the signal 

• only one row active low power consumption 

• two different auxiliary ASICs needed 

gate 

off 

on 

off 

off 

V GATE, ON 

V GATE, OFF 

DEPFET- matrix 

I DRAIN 

n x m 

pixel 

drain 

0 suppression 

off 

reset 

off 

off 

V CLEAR, ON 

reset 

V CLEAR, OFF 

V CLEAR-Control 

output

DEPFETs for the ILC: Achievements and Status 

DEPFETs for the ILC VXD 

 

 

Prototype System with DEPFETs (450µm), CURO and Switcher 

many test beams @ CERN and DESY: 

S/N≈140 @ 450 µm goal S/N ≈ 20-40 @ 50 µm 

 

sample-clear-sample 320 ns goal 50 ns 

s.p. res. with 24 µm pixels: 1.3 µm @ 450 µm 

goal ≈ 4 µm @ 50 µm 

 

Thinning technology established, thickness can be adjusted to the 

needs of the experiment (~20 µm … ~100 µm), 

design goal 0.11 % X 0 

 

radiation tolerance tested with single pixel structures up to 

1 Mrad and ~10 12 n eq /cm 2 

In this talk: 

• Towards SuperBelle… 

• New irradiation of DEPFETs to higher TIDs 

• Consequences ... 

1st Open SuperKEKB Collaboration Meeting, KEK, Dezember 2008 Ladislav Andricek, MPI fuer Physik, HLL 5


The DEPFET Ladder for SuperBelle PXD 

Some important numbers for the baseline layout: 

sensitive region : 1.15x7.25 cm 2 (L1), 1.15x9.26 cm 2 (L2) 

(subject to optimization) 

read-out time : 100kHz frame rate, 80ns for 4 rows 

material budget : 0.15% X0 (incl. frame, chips, bumps) 

power/module : DEPFETs ~ 0.5 W 

Switcher ~ 0.2 W 

DCD ~ 3 W on each ladder end


DEPFET Pixel Cell for SuperBelle 

DEPFETs from ILC to SuperKEKB: 

-: the principle is of course the same 

-: technology to a large extent also 

-: but the cell size is much larger!!! 

24x24µm 2 50x75µm 2 

keep W and L small (maintain clear and g q 

) 

re-design drain and source region to keep 

Drain 

Gate 

Source 

charge collection time short (


Capacitively Coupled Common Clear Gate 

Gate 

poly2 

std.: clocked clear gate 

Clear 

n+ implant 

Clear Gate 

Gate 

ILC: common clear gate 

Clear 

Clear Gate 

Gate 

fast and safe clear: 

cap. coupled clear gate 

Clear 

Clear Gate 

109 Cd spectrum (22keV, 6000 e - ) 

taken with 128x64 PXD5 matrix


Internal amplification g q 

g 

q 

= 

dI 

D 

dQ 

μ 

= − 

L 

p 

( V 

2 GS 

−Vth 

) 

(neglecting short channel effects) 

PXD5: single pixel measurement 

S.Rummel 

As long as noise is dominated by r/o chip S/N linear with g q 

Our conservative assumption is g q 

≈ 500 pA/e-, but even 1nA/e- seems within reach!


Two DEPFET runs for SuperBelle 

First run PXD6: 2009 

Siltronic, FZ, DSP, , t=450µm, 400Ω.cm, Phosphorous 

-: first DEPFET run on SOI wafers!! 

-: 6 SOI and 2 std. Hi-Res Wafer 

-: top wafer (front side) technology like PXD5 

-: new technology: thinning and BS process 

-: Aim: - find optimal design 

- optimize technology and yield 

- provide devices for all-silicon module 

End Spring 2010 

hydrophilic bond 

at Tracit/Soitec 

230 nm thermal oxide 

Siltronic, FZ, DSP, , t=450µm, 400Ω.cm, Phosphorous 

structured Boron implant, through BOX, 90 keV, 5e14 - 1e15 cm-2 

alignment marks in BOX: 60nm step 

top layer: 50 µm 

DSP 

after bonding, grinding and double sided polishing 

≈420 µm 

SuperBelle Production PXD7: Start 2011 

-: With improved technology 

-: 20 Wafer? (depends on yield of PXD6) 

End Spring 2012 

preliminary wafer floor plan for PXD6


Just as a Reminder: Thinning Technology 

a) oxidation and back side implant 

of top wafer 

Top Wafer 

c) process passivation 

Handle Wafer 

open backside passivation 

b) wafer bonding and 

grinding/polishing of top wafer 

d) anisotropic deep etching opens "windows" 

in handle wafer


Irradiations - Devices and setup 

S.Rummel 

-: PXD5, Wafer 90, 8x12 mini-matrix, 32x24 µm 2 

-: irradiation with X-rays photons in Karlsruhe, ~150krad/h, Emax=60keV 

-: entire matrix biased in "off" during irradiation, periodically cleared 

-: four pixels selected to measure basic characteristics throughout irradiation 

0 V 

-0.5V 

4V 

20kHz 6V/18V 

-5V 

Bulk: 

Back side: 

10V 

180V


Irradiations - First period: Results 

60 

Co 

irradiation 

after 7.9 Mrad 

Vt: 0-13V after 5 days RT annealing 

and 

~1V V t 

variation of identical DEPFETs at same 

TID! 

7.9Mrad 

5 days ann. 

at RT 

1Mrad 

pre-irrad


Irradiations - First period: Spectroscopic Performance 

S.Rummel 

S.Rummel 

non-irradiated 

V thresh ≈-0.2V 

time cont. shaping τ=10 μs 

Noise ENC=2.1 e - (rms) 

at T>23 degC 

Noise ENC=4.6 e - (rms) 

at T>23 degC 

7.9 Mrad, 10keV X-rays 

V thresh ≈-13.0V, 

time cont. shaping τ=10 μs


Irradiations - First period: noise vs. shaping time 

8kTg 

1 

ENC = 

+ 

m 

2 

α + 2πa 

f 

Ctot 

qI 

Leakτ 

2 

3gq 

τ 

Therm. noise 1/f I L 

(‏unirradiated -: Leakage current in the pixel @ RT ~40 fA ( 10-22fA 

-: Noise increase due to 1/f noise which is independent of bandwidth 

-: noise increase due to radiation is not factor 2 but only 3 e - ENC


Irradiations - First period: threshold dispersion 

-: 4 DEPFETS ∆Vt≈1V after 8 Mrad is an issue!! 

-: 8x12 DEPFETs on mini-matrix, so re-bond and measure them all for higher statistic 

But then ... due a misunderstanding ... accidentally(!!!) the structure was annealed for 1/2h @ 110°C 

But on the other hand, we now know that the dispersion is not the final state and maybe 

even room temperature annealing will lead to the same results. 

Anyway, the conclusion is: Nice try, but do another irradiation!!!!


Irradiations - Second Period 

-: PXD5, Wafer 90, 8x12 mini-matrix, 32x24 µm 2 

-: irradiation with X-rays photons in Karlsruhe, ~185krad/h, Emax=60keV 

-: entire matrix biased in "off" during irradiation, periodically cleared 

-: gate off voltage and common clear gate voltage was stepwise adapted to 

radiation induced threshold voltage shift 

-: 16 pixels selected to measure basic characteristics throughout irradiation 

0 V 

-0.5 -17 V 

4V -22V 

20kHz 6V/18V 

-5V 

Bulk: 

Back side: 

10V 

180V


Irradiations - Second Period: Results 

-: No saturation visible with adaptive gate off 

parameter 

-: Below 0V gate off voltage higher damage 

-: Shift ~10V higher than with constant bias!!! 

-: Dispersion is still there!! 

-: Annealing at RT (10 days) ∆Vt≈16.5 +/- 0.8 V 

only Gate shown here; Clear Gate behaves similar!


Reasons I - Radiation Effects 

≈ 200nm Gate Dielectrics 

1. e/h pair generation (~17eV/pair in SiO 2 

) 

2. e/h pair recombination (“charge yield”) 

-rad. Source 

- electric field in oxide 

3. e and h transport 

-e: ~ps…ns 

-h: ~ms…s 

4. hole trapping 

- precursor density technology 

5. interface trap formation 

- precursor density technology 

1. 

2. 

3. 

4. 

5.


Reasons II - Field Dependence, MOS-C irradiations 

-V FB 

(V) 

25 

20 

15 

10 

flat band voltage 

positive oxide charge 

Dose=1 Mrad 

d ox 

=86nm 

b. c. 

6.00E+012 

5.00E+012 

4.00E+012 

3.00E+012 

Nox (cm-2 ) 

Region a.: 

Field minimal, DEPFET in "OFF" state, no channel, 

region under gate depleted and floating 

Region b.: 

small negative voltage at gate, DEPFET "ON", 

charges in SiO2 separated higher charge yield 

2.00E+012 

5 

a. 

Q.Wei 

-10 -5 0 5 10 15 

1.00E+012 

Region c.: 

positive voltage on gate, e- drift do poly gate, 

holes trapped at interface, not possible in DEPFET! 

V g 

(V) 

But "channel" close to the Source is not completely floating!! 

adaption of Gate-off voltage to negative values during irradiation increases the field there 

Gate "OFF" close to the Source is then in Region b. 

larger threshold voltage shift, if one tries to keep (V Gate-On 

-V Gate-Off 

) constant 

in the experiment


Consequences 

1. Threshold dispersion after uniform irradiations: 

-: not that critical at the Gate, the resulting spread in the Drain currents (+/-20% after RT annealing) 

is manageable by the front end electronics 

-: the effects at the Clear Gate have still to be evaluated... 

2. Higher threshold shift when going to negative Gate-Off voltages: 

-: keep the Gate-Off voltage close to 0 new Switcher4 will have up to 50V range! 

-: the penalty is probably higher power consumption and longer rise times 

So, there are work-arounds, but the best would be to take advantage of having the 

freedom to the tailor the technology in order to minimize the radiation induced 

threshold voltage shift. 

The radiation tolerance of the DEPFET was sufficient for the ILC, but it needs more 

effort for SuperKEKB!

Consequences - Improve Technology 

-: thinner oxide smaller shift but lower internal amplification g q 

-: But: g q 

~ sqrt(t ox 

) , can be compensated with higher currents and/or shorter gate length 

(see slide 9) 

-: optimized gate dielectrics 

35 

MOS - 86nm Oxi 

MOS - 100nm Oxi 

Flat Band Voltage Shift 

1 

Flat band voltage shift vs. radiation dose 

MNOS - 86nm Oxi & 10nm Nitride 

30 



V gate 

=0V 

25 

TID: 1Mrad 

0,75 

20 

Vfb (V 

Vfb (V 

0,5 

15 

10 

0,25 

5 

Irrad. to higher TID under way 

0 

-10 -5 0 5 10 15 

Vg (V) 

0 

0 250 500 750 1000 

Radiation dose (krad) 

Q.Wei 

Smaller (simpler) DEPFET technology test run planned in parallel to PXD6 production 

DEPFETs with thinner and optimized gate dielectrics in the final run! 



Summary 

-: Preparations for the SuperBelle DEPFET production are well underway, designs are being 

finalized. Processing starts after the Christmas break! 

-: ASIC and System design for the SuperBelle environment has started. 

(report at the next collaboration meeting) 

-: Radiation tolerance of the DEPFET remains to be an issue! 

performance after 8 Mrad okay!! Negligible reverse current after irrad. and only 3 e- (rms) 

noise increase. 

there is considerable annealing at room temperature: 10V and 70% of the total spread 

disappeared after 10 days at RT. 

but still, for a robust system design, we would need to reduce both the absolute 

threshold voltage shift and the dispersion 

-: First irradiation up to 1Mrad with thinner and optimized Gate dielectrics show the 

feasibility of this approach. A parallel development is planned 2009. 

With the given time scale for the project, we urgently need for the optimization and system design 

reliable numbers (with reasonable safety factors) for: 

-: radiation environment, both ionizing and NIEL parts 

-: how (in-)homogeneous is the irradiation over a ladder? 

-: operating temperature of the sensors (critical in case of NIEL damage)

Backup slides follow…. 



A new r/o chip - DCD 

DCD: Drain Current Digitizer 

Test chip DCD2: 6X12 channels 

(Uni Heidelberg) 

-: improved input cascode (regulated) and current memory cells 

-: integrated 8bit current based ADC per channel, 12.5 MHz sampling rate 

-: designed for 40 pF load at the input (5cm Drain line), 12 µm r/o pitch 

-: f/e noise: 34nA@40pF, 17nA@10pF, add 37nA for memory cells 

50nA@40pF at 40pF with g q =500pA/e 100 e- ENC in total 

-: layout for bump bonding, rad. hard design 

-: power consumption per channel 3.6 mW (measured) 

-: digital hit processing done with 2nd chip/FPGA


Switcher III 

-: Radiation hard (AMS 0.35 µm, layout) 

-: up to 10V swing ( stacked transistors) 

-: Power: 53 mW per chip (128 chn.) at 20 MHz 

-: Fast settling ( 600kRad! 

-: Full chip produced and functional 

9V distributed over 3 transistors 

with 3V -> rad hard. technology 

possible


50x75 µm 2 pixel IP Resolution at SuperBelle 

DEPFET: 

"DSSD": 

Simulation of SVD LOI layout 

Stand alone tracking, single tracks, no background 

L1 1.3 cm (50µm x 75µm) 

L2 1.6 cm (50µm x 75µm) 

thickness: 50µm, 0.14% X 0 , noise 100e 

L3/L4/L5/L6 with 50µmx75µm 

thickness 300µm, noise 1600e 

beam pipe: r=1cm (Be with 10µm Au layer) 

Substantial improvement over Belle SVD2! 

very preliminary 

-: factor 0.5 @ high momentum 

-: factor 0.25 @ below 0.5 GeV/c and large theta 

Solid lines: Belles SVD2, symbols: DEPFET sBelle


Subtreshold current Interface trap density 1/f noise 

s D1 

(mV/dec) 

10 -18 

10 -17 Id=75uA 

proton 

mos10 

mos2 

mos4 

mos5 

s D2 

(mV/dec) 

1x10 -19 

60 Co 

1x10 -20 

60 Co irradiation 

Si (A^2/Hz) 

1x10 -21 

10 -22 

1x10 -23 

neutron 

non-irrad 

1x10 -24 

10 -25 

ΔN 

it 

= 

Cox 

⋅( 

s 

kT ⋅ln(10) 

− s 

D2 D1 

) 

10 -26 

1 10 100 1k 10k 100k 

Frequency 

irradiation TID / NIEL fluence ∆s (mV/dec) ∆N it 

(cm -2·eV-1 ) 

gamma 60 Co 913 krad / ~ 0 88 1.6·10 11 

neutron ~ 0 / 2.4x10 11 n/cm 2 ~ 0 ~ 0 

proton 283krad / 3x10 12 n/cm 2 230 4.2·10 11 

Lit: ~ 10 12 -10 13 cm -2·eV -1 for 200nm gate oxide


Possible New Layout… 

LOI layout 

DEPFET layout 

Layer 1 Layer 2 Layer 1 Layer 2 

R min 

/cm 1.3 1.6 1.3 1.8 

N 12 12 8 12 

Width/cm (sensitive) 0.85 1.00 1.15 1.15 

Width/cm (geometrical) 1.05 1.20 1.35 1.35 

R max 

/cm 1.41 1.72 1.45 1.95 

L min 

/cm 7.05 8.61 7.25 9.76 

L real 

/cm 7.1 8.6 7.3 9.8 

why?? 

-: less modules in L1 

-: less material, connectors, services.. 

-: greater lever arm 

-: only 12 150mm wafers for the full PXD!!

DEPFET Active Pixel Sensors for SuperBelle PXD - Belle II - KEK

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