AMSV Newsletter 2011

Journal Papers in 2011
• PUI-IN MAK, R.P.MARTINS, “A 0.46mm 2 4-dB NF Unified Receiver Front-End for Full-Band Mobile TV in 65nm CMOS”,
IEEE Journal of Solid-State Circuits, vol. 46, No.9, pp.1970-1984, September 2011.
• ZUSHU YAN, PUI-IN MAK, R.P.MARTINS, “Double recycling technique for folded-cascode OTA”, Analog Integrated
Circuits and Signal Processing, Springer, 28 August 2011.
• ZUSHU YAN, PUI-IN MAK, R.P.MARTINS, “Two-Stage Operational Amplifiers: Power-and-Area-Efficient Frequency
Compensation for Driving a Wide Range of Capacitive Load”, IEEE CAS Magazine, vol. 11, No.1, pp.26-42, 1st Quarter
2011.
IEEE Conferences – 26 Papers (25 in 2011)
ISSCC 2012, San Francisco, USA, February 2012
1. “A 0.016mm 2 144μW Three-Stage Amplifier Capable of Driving 1-to-15nF Capacitive Load with >0.95MHz GBW”
RFIT 2011, Beijing, China, December
2. “Design Techniques for Nanometer Wideband Power-Efficient CMOS ADCs”
ISOCC 2011, Jeju, South-Korea, November
3. “Hybrid Loopfilter Sigma-Delta Modulator With NTF Zero Compensation”
A-SSCC 2011, Jeju, South-Korea, November
4. “A Reconfigurable Low-Noise Dynamic Comparator with Offset Calibration in 90nm CMOS”
5. “A 35 fJ 10b 160 MS/s Pipelined-SAR ADC with Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation”
(Award - Top Asia)
6. “A 5-bit 500MS/s Comparator-Strengthening Binary-Search ADC”
PRIMEASIA 2011, Macao, China, October
7. “A Double Active-Decoupling Technique for Reducing Package Effects in a Cognitive-Radio Balun-LNA” (Award - Gold
Leaf)
8. “A Novel Digital Predistortion Technique for Class-E PA with Delay Mismatch Estimation” (Award - Silver Leaf)
9. “A Nonlinearity Digital Background Calibration Algorithm for 2.5bit/stage Pipelined ADCs with Opamp sharing
Architecture” (Award - Bronze Leaf)
10. “NTF Zero Compensation Technique for Passive Sigma-Delta Modulator”
11. “A FPGA-Based Power Electronics Controller for Hybrid Active Power Filters”
12. “A Time-Efficient Dither-Injection Scheme for Pipeline SAR ADC”
ESSCIRC 2011, Helsinki, Finland, September
13. “A 7-bit 300-MS/s Subranging ADC with Embedded Threshold & Gain-Loss Calibration”
EMBC 2011, Boston, Massachusetts, USA, August
14. “An Ultra-Low-Power Filtering Technique for Biomedical Applications”
MWSCAS 2011, Seoul, South-Korea, August
15. “A Dual-VCO-Based Quantizer with Highly Improved Linearity and Enlarged Dynamic Range”
16. “Multi-Merged-Switched Redundant Capacitive DACs for 2b/cycle SAR ADC”
17. “Noise Shaping Implementation in Two-Step/SAR ADC Architectures Based on Delayed Quantization Error”
18. “A Charge Pump Based Timing-Skew Calibration for Time-Interleaved ADC”
19. “Clock-Jitter Sensitivity Reduction in CT Sigma-Delta Modulators Using Voltage-Crossing Detection DAC”
20. “A Passive Excess-Loop-Delay Compensation Technique for Gm-C Based Continuous-Time Sigma-Delta Modulators”
ICIEA 2011, Beijing, China, June
21. “FPGA-based Decoupled Double Synchronous Reference Frame PLL for Active Power Filters”
ISCAS 2011, Rio de Janeiro, Brazil, May
22. “A Single-to-Differential LNA Topology with Robust Output Gain-Phase Balancing against Balun Imbalance”
23. “A High-Voltage-Enabled Recycling Folded Cascode Opamp for Nanoscale CMOS Technologies”
EUROCON 2011, Lisbon, Portugal, April
24. “A Linearity-Improved Ultra-Wideband Balun-LNA for Cognitive Radio”
ISSCC 2011, San Francisco, USA, February
25. “A 0.024mm 2 8-bit 400 MS/s SAR ADC with 2-bit/Cycle and Resistive DAC in 65 nm CMOS" (Silk-Road Award)
26. “A 0.46mm 2 4dB-NF Unified Receiver Front-End for Full-Band Mobile TV in 65nm CMOS”
State Key Laboratory of Analog and Mixed-Signal VLSI / UM
http://www.fst.umac.mo/en/lab/ans_vlsi/