AMSV Newsletter 2011

State Key Laboratory of
Analog and Mixed-Signal VLSI
State Key Lab of Analog and Mixed-Signal VLSI (SKL AMS-VLSI)
Newsletter
Motto: “Locally, from (World) Quality towards (National) Quantity”
座 右 銘 : 立 足 本 土 人 才 培 養 , 以 世 界 級 質 量 創 建 國 家 級 規 模
Year 1
No. 1
2011 Milestones
December 2011
Inauguration of the State Key Laboratory on 25 January 2011
Left: Dr. Chui Sai On, Chief Executive of Macao SAR, and other guests unveil the plaques of the 2 State Key Labs.
Right: Prof. Rui Martins, VR (Research) University of Macau, Director of SKL AMS-VLSI, speaks at the ceremony.
Group photo of the State Key Laboratory of Analog and Mixed-Signal VLSI

“Chip Olympics” – 58 th International Solid-State Circuits Conference - ISSCC 2011
The 58 th IEEE International Solid-State Circuits Conference – ISSCC 2011 held between February 20 and 23, in San
Francisco, USA, is the flagship conference of the Solid-State Circuits Society (SSCS), one of the largest of the 40
societies of IEEE (Institute of Electrical and
Electronics Engineers), and at the forefront of the
current Information Age Revolution.
UM (through SKL AMS-VLSI) was this year
positioned as the 15 th in the world among 46
universities that were able to publish there, 5th in
Asia and 1 st in China with 2 chips selected for
presentation and entitled: “A 0.46mm 2 4dB-NF Unified Receiver Front-End for Full-Band Mobile TV in 65nm CMOS” (left),
and “A 0.024mm 2 8-bit 400 MS/s SAR ADC with 2-bit/Cycle and Resistive DAC in 65 nm CMOS” [Silk Road Award for
Region 10 – Asia, Australia, the Pacific.] (right)
Important Events
Two PhD Oral Defenses on
Microelectronics held on 22-July 2011
Title: High Speed Power / Area
Optimized Multi-Bit / Cycle SAR
ADCs (Silk Road Award ISSCC2011)
Candidate: He-Gong Wei (Abner)
Title: Circuit Techniques for
High-Performance SAR Type
ADCs (Award ASSCC2011,TopAsia)
Candidate: Yan Zhu (Julia)
State Key Lab of AMS-VLSI / Science Series
22-23 July 2011
1 st Distinguished Lectures, PhD Oral Defenses
& Lab Workshop
Prof. Ian A. Galton, IEEE Fellow, Univ. of California, San
Diego, USA
• Mismatch-Shaping Techniques for
Delta-Sigma Data Converters
• Digital Background Calibration in
Pipelined ADCs
PhD Oral Defenses on Microelectronics
Prof. Bram Nauta, IEEE Fellow, Univ. of Twente, The
Netherlands
• Ultra low-power & Wideband
High-speed Nyquist AD Converter
• RF Circuit Techniques in
Nanometer CMOS
Prof. Boris Murmann, Stanford Univ.,
San Francisco, USA
• Analysis and Design of
Switched-Capacitor Circuits
• Design of Pipelined A/D Converters
• Digitally Assisted Data Converter
Design
First Distinguished Lectures, PhD Oral Defenses & Lab Workshop on 22 and 23 July 2011

Second Class Award of The State Scientific and Technological Progress Award
[China National Award]
Second Class Award of The State Scientific and Technological Progress Award to be received by Prof. Seng-Pan U,
Prof. Pui-In Mak and Dr. Sai-Weng Sin for their contribution in microelectronics research. The State Science and
Technology Prizes ( 國 家 科 學 技 術 獎 勵 ) is the highest honor in China in science and technology, in order to recognize
citizens and organizations that have made remarkable contributions to scientific and technological progress, and to
promote the development of science and technology.
PhD Student Ranks No. 1 at the Student Design Contest in A-SSCC 2011
Three PhD students Ms. Zhu Yan (Julia), Mr. Chan Chi Hang and Mr. Wong Si Seng, led by Dr. Sin Sai Weng, Prof. U
Seng Pan and Prof. Rui Martins, have developed three advanced nanometer analog-to-digital converter and comparator
chips that were all accepted by the IEEE Asian Solid-State Circuits Conference (A-SSCC), known as “Asia’s Chip
Olympics”. One of the relevant papers also won the student design contest, ranking No. 1, ahead of Korea Advanced
Institute of Science and Technology (KAIST) and Tokyo Institute of Technology (TIT). Macao was the only region to
achieve a paper acceptance rate of 100% at this year’s A-SSCC, with all the papers from UM.
Left: SKL AMS-VLSI onsite demonstration at this year’s A-SSCC for the paper award design contest attracts many world-renowned experts
Right: Announcement of the Awardees with PhD student Julia ranking No. 1 in Asia, with UM ahead of KAIST & TIT at the student design contest.
A-SSCC is Asia’s most prestigious conference in the field of integrated circuits and provides a platform for top institutions
from the industry and the academia (most from Asia, but also many from Europe and the U.S.) to showcase their latest
technological achievements. This year’s conference was held in Jeju, South Korea.
US Patents Granted in 2011
• PUI-IN MAK, SENG-PAN U, R.P.MARTINS, DC-Offset Canceled Programmable Gain Array for Low-Voltage
Wireless LAN System and Method Using the Same, US Patent No. 7,948,309, from May 24, 2011.
• PUI-IN MAK, SENG-PAN U, R.P.MARTINS, Two-step Channel Selection for Wireless Transmitter Front-Ends, US
Patent No. 8,019,290 B2, from September 13, 2011.
Books
• PUI-IN MAK, R.P.MARTINS, High-/Mixed-Voltage Analog and RF Circuit Techniques for Nanoscale CMOS,
Springer - USA, to appear in January 2012.
• SAI-WENG SIN, SENG-PAN U, R.P.MARTINS, Generalized Low-Voltage Circuit Design Techniques for Very
High-Speed Time-Interleaved Pipelined ADC, Springer - Analog Circuits and Signal Processing, ISBN
978-90-481-9709-5, Dordrecht, The Netherlands: Springer, January 2011.

Journal Papers in 2011
• PUI-IN MAK, R.P.MARTINS, “A 0.46mm 2 4-dB NF Unified Receiver Front-End for Full-Band Mobile TV in 65nm CMOS”,
IEEE Journal of Solid-State Circuits, vol. 46, No.9, pp.1970-1984, September 2011.
• ZUSHU YAN, PUI-IN MAK, R.P.MARTINS, “Double recycling technique for folded-cascode OTA”, Analog Integrated
Circuits and Signal Processing, Springer, 28 August 2011.
• ZUSHU YAN, PUI-IN MAK, R.P.MARTINS, “Two-Stage Operational Amplifiers: Power-and-Area-Efficient Frequency
Compensation for Driving a Wide Range of Capacitive Load”, IEEE CAS Magazine, vol. 11, No.1, pp.26-42, 1st Quarter
2011.
IEEE Conferences – 26 Papers (25 in 2011)
ISSCC 2012, San Francisco, USA, February 2012
1. “A 0.016mm 2 144μW Three-Stage Amplifier Capable of Driving 1-to-15nF Capacitive Load with >0.95MHz GBW”
RFIT 2011, Beijing, China, December
2. “Design Techniques for Nanometer Wideband Power-Efficient CMOS ADCs”
ISOCC 2011, Jeju, South-Korea, November
3. “Hybrid Loopfilter Sigma-Delta Modulator With NTF Zero Compensation”
A-SSCC 2011, Jeju, South-Korea, November
4. “A Reconfigurable Low-Noise Dynamic Comparator with Offset Calibration in 90nm CMOS”
5. “A 35 fJ 10b 160 MS/s Pipelined-SAR ADC with Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation”
(Award - Top Asia)
6. “A 5-bit 500MS/s Comparator-Strengthening Binary-Search ADC”
PRIMEASIA 2011, Macao, China, October
7. “A Double Active-Decoupling Technique for Reducing Package Effects in a Cognitive-Radio Balun-LNA” (Award - Gold
Leaf)
8. “A Novel Digital Predistortion Technique for Class-E PA with Delay Mismatch Estimation” (Award - Silver Leaf)
9. “A Nonlinearity Digital Background Calibration Algorithm for 2.5bit/stage Pipelined ADCs with Opamp sharing
Architecture” (Award - Bronze Leaf)
10. “NTF Zero Compensation Technique for Passive Sigma-Delta Modulator”
11. “A FPGA-Based Power Electronics Controller for Hybrid Active Power Filters”
12. “A Time-Efficient Dither-Injection Scheme for Pipeline SAR ADC”
ESSCIRC 2011, Helsinki, Finland, September
13. “A 7-bit 300-MS/s Subranging ADC with Embedded Threshold & Gain-Loss Calibration”
EMBC 2011, Boston, Massachusetts, USA, August
14. “An Ultra-Low-Power Filtering Technique for Biomedical Applications”
MWSCAS 2011, Seoul, South-Korea, August
15. “A Dual-VCO-Based Quantizer with Highly Improved Linearity and Enlarged Dynamic Range”
16. “Multi-Merged-Switched Redundant Capacitive DACs for 2b/cycle SAR ADC”
17. “Noise Shaping Implementation in Two-Step/SAR ADC Architectures Based on Delayed Quantization Error”
18. “A Charge Pump Based Timing-Skew Calibration for Time-Interleaved ADC”
19. “Clock-Jitter Sensitivity Reduction in CT Sigma-Delta Modulators Using Voltage-Crossing Detection DAC”
20. “A Passive Excess-Loop-Delay Compensation Technique for Gm-C Based Continuous-Time Sigma-Delta Modulators”
ICIEA 2011, Beijing, China, June
21. “FPGA-based Decoupled Double Synchronous Reference Frame PLL for Active Power Filters”
ISCAS 2011, Rio de Janeiro, Brazil, May
22. “A Single-to-Differential LNA Topology with Robust Output Gain-Phase Balancing against Balun Imbalance”
23. “A High-Voltage-Enabled Recycling Folded Cascode Opamp for Nanoscale CMOS Technologies”
EUROCON 2011, Lisbon, Portugal, April
24. “A Linearity-Improved Ultra-Wideband Balun-LNA for Cognitive Radio”
ISSCC 2011, San Francisco, USA, February
25. “A 0.024mm 2 8-bit 400 MS/s SAR ADC with 2-bit/Cycle and Resistive DAC in 65 nm CMOS" (Silk-Road Award)
26. “A 0.46mm 2 4dB-NF Unified Receiver Front-End for Full-Band Mobile TV in 65nm CMOS”
State Key Laboratory of Analog and Mixed-Signal VLSI / UM
http://www.fst.umac.mo/en/lab/ans_vlsi/