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1.26 MILLISECONDS
The time by which the length of a day is estimated
to have been shortened by the recent earthquake
in Chile, which at 8.8 on the Richter scale ranks as the seventh strongest quake ever recorded.
Chipmakers Bet on
a Stacked Deck
Three-dimensional packaging promises
smaller, smarter gadgets
Imagine that your favorite
aunt lies sick on the other
side of town. Rather than
brave the highways to visit
her, you move her into your
apartment building and just
ride the elevator up.
Chipmakers are applying
the same strategy to get
around the biggest speed
bump in microelectronics—
the distance between dies.
Instead of wiring chips to one
another in two dimensions,
in which the input/output
plugs are spaced some
200 micrometers apart,
engineers plan to link them
in a 3-D stack, using copper
interconnects 10 μm apart—
vertically. The interconnects,
called through-silicon vias
14 NA • IEEE SPECTRUM • APRIL 2010
(TSVs), might be said to
resemble elevator shafts.
The hope is that TSVs
will enable the industry
to keep increasing the
capabilities of smartphones
and other gadgets while
making them tinier, even
as transistor densities rise
at ever more sluggish rates,
says Pol Marchal, a principal
scientist of 3-D integration at
European microelectronics
R&D center Imec.
To be sure, there are still a
few problems. At February’s
IEEE International Solid-
State Circuits Conference,
Imec engineers presented
some key design challenges
that must be overcome before
TSVs can be widely used.
VERTICALLY CHALLENGED:
Copper “vias” connect silicon
dies stacked in a deck.
IMAGE: IMEC
The first challenge is size.
The handful of products that
now contain TSVs—such
as some image sensors and
dynamic RAM stacks—use
relatively hefty chunks of
metal, typically about 100 μm
wide. But that’s not good for
integrating disparate devices,
such as logic and memory,
because the TSVs themselves
take up too much real estate.
However, Imec’s work has
demonstrated that you
can make TSVs 5 μm wide,
which allows for squeezing
more TSVs—and more
transistors—on each layer.
Another challenge is the
mechanical stress you get
during the cooling stage
of processing, when the
copper TSVs contract faster
than their silicon bedding
does. That stress can hinder
transistor performance.
Depending on a device’s
application, designers will
have to take into account
how much stress a system
can handle and how far
apart the TSVs should be
to reduce the stress in the
silicon, Marchal says.
One problem in buildings
is that as they get taller, they
require so many elevator
shafts that there’s no more
interior room for anything
else. For stacked chips,
too, there are height limits,
particularly for consumer
devices where the whole
package must be minute.
For these applications, the
stack height is limited to
300 μm, or about 3 or 4 tiers,
Marchal says. Stacks could
grow to 16 tiers before
hitting reliability barriers or
delivering power unevenly
throughout the stack.
Also, the proximity of
TSVs to transistors on the
chip can alter performance
values, such as threshold
voltage and drive current.
Designers will therefore
have to introduce “keep out”
areas where there are no
devices. For instance, in a
digital-to-analog converter
made using the common
65-nanometer lithography
process, each analog
component must sit tens of
micrometers from a via to
avoid reducing performance
more than 0.05 percent,
which is essential in a
highly accurate converter.
So 3-D chip designers will
have to carefully balance the
cost of the altered architecture
that TSVs require with the
benefit of tighter integration.
Otherwise, chips with TSVs
might turn out to be just as
costly in terms of wasted
space or poor performance
as the multiple 2-D chips
they are about to replace.
Nevertheless, Marchal
says, “the industry pull for
this technology is big,” and
TSVs should be common
in chips by 2012 or 2013.
In the meantime, Imec is
working with electronic
design automation firms
to model trade-offs among
performance, efficiency, and a
compact 3-D floor plan.
—Anne-Marie Corley
A version of this article ran
online in February 2010.
__________
SPECTRUM.IEEE.ORG
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