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ANNEXURE TO TENDER NO.DPS/MRPU/IGCAR/COMP/5235/TPT ...

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<strong>ANNEXURE</strong> <strong>TO</strong> <strong>TENDER</strong> <strong>NO</strong>.<strong>DPS</strong>/<strong>MRPU</strong>/<strong>IGCAR</strong>/<strong>COMP</strong>/<strong>5235</strong>/<strong>TPT</strong>-1178<br />

1. Description of the ITEM :<br />

i) HyperLynx Signal Integrity, Power Integrity,<br />

Thermal Analysis and DRC for EMI/EMC Tool<br />

with workstation for running EDA Tools - 1 Set.<br />

2. Detailed SPECIFICATIONS and Quantity :<br />

Specification for HyperLynx SI, PI, Thermal Analysis & DRC<br />

for EMI/EMC Tool - 1 No.<br />

Hyperlynx Signal Integrity (SI)<br />

HyperLynx SI tool should address high-speed PCB problems through-out the design cycle, beginning<br />

at the earliest architectural stages and moving through post-layout verification. This tool should support<br />

the following features:-<br />

Pre-Layout Analysis<br />

• To predict and eliminate signal integrity problems early by allowing proactive constrain routing,<br />

plan stackups and optimize clock, critical signal topologies and terminations prior to layout.<br />

• To facilitate intuitive drag-and-drop transmission-line modeling, complex interconnects, including<br />

ICs, traces, vias, cables, connectors and passive components of design layout.<br />

• Integrated 2D and 3D field solvers for accurate modeling and solution space exploration.<br />

• To facilitate simulation using industry-standard IBIS Models, generic models and models from<br />

databook information.<br />

• To allow editing IBIS models including a heirarchical, automated syntax.<br />

• To instantiate HSPICE, ELDO, IBIS-AMI, AMS, S-parameter and IBIS models.<br />

• Design kits for PCI Express, DDR2, and PCI-X with timing analysis.<br />

• To predict serial interface bit error rates (BER), worst-case bit sequences and eye diagrams using<br />

HyperLynx FastEye.<br />

Post-Layout Verification<br />

• To allow signal integrity and timing analysis at three important stages: following part placement in<br />

PCB layout system, after critical net routing and after detailed routing of an entire board.<br />

• To facilitate interactive analysis that takes next level batch simulation to automatically scan large<br />

number of nets on an entire PCB, flagging SI and EMC hot spots.<br />

• To allow inserting new termination components on-the-fly, enabling real-time analysis.<br />

• To predict crosstalk waveforms for any trace topology and IC placement, showing specific crosssections<br />

violating crosstalk thresholds.<br />

• To support multi-board analysis, including support for EBD models and connector models.<br />

• To do verification of DDR, DDR2, and DDR3 memory systems, including timing analysis.<br />

• To support sweeping parameters, loss modeling, enhanced via modeling, eye diagram, multiboard<br />

analysis, waveform analyzer, SPICE/S-parameter simulation/HL SI SPICE/ADMS, s-<br />

parameter generation, SPICE writer, surface roughness, fast eye & statistical curves, integrated<br />

3D via modeling, models for Eldo & VHDL-AMS, IBIS-AMI simulation/sweeps, 3D geometry<br />

extraction to HL 3DEM and SI & plane co-simulation.<br />

HyperLynx Power Integrity (PI)<br />

HyperLynx PI tool should address power distribution problems early in the board design & layout<br />

stage. This tool should support the following features:-<br />

IR Drop Analysis<br />

• To identify issues such as excessive voltage drop, high current densities, excessive via currents<br />

and disconnected power.


• To facilitate simulation results to be viewed in graphical and report format.<br />

• To support 3D power viewer, stackup editor/field solver, dc drop analysis, thermal/dc drop cosimulation,<br />

decoupling analysis, decoupling acceleration, plane noise analysis.<br />

• To enable to read board data into HyperLynx layout analysis environment.<br />

• To support to analyze DC behavior per net or across the whole board.<br />

• To support to export to pre-layout environment to do what-if analysis on changing copper islands<br />

and adding vias.<br />

Power Distribution Network (PDN) Analysis<br />

• To support to optimize impedance of power distribution network (PDN) in pre- or post-layout<br />

modes.<br />

• To support to analyze propagation of noise on the planes<br />

• To allow what-if analysis for board outlines, plane voids and adding copper on plane.<br />

• To perform noise analysis to visualize the decoupling strategy<br />

• To allow placement & mounting of capacitors on planes.<br />

Model Extraction<br />

• To support to model vias in the multigigabit domain including entire bypassing network of the<br />

board.<br />

• To support to extract portable PDN models as S-parameters, Z-parameters or Y-parameters<br />

HyperLynx Thermal<br />

HyperLynx Thermal tool should support to simulate board temperatures, component and junction<br />

temperatures as well as component temperature constraint violations. This tool should support the<br />

following features:-<br />

• To support 3D modeling of complex flow and thermal fields based on heat conduction, convection<br />

and radiation effect.<br />

• To find temperature profile & gradient of PCB.<br />

• To support enclosure modeling, board/layer copper modeling, heat sink, heat pipe, screw.<br />

• To facilitate to import and analyze single-sided, double-sided, and multilayer boards with irregular<br />

shapes, and reference-plane discontinuities.<br />

• To support to model effects of gravity, air pressure, flow directions and PCBs in a sealed<br />

compartment—with or without a heat exchanger—or in an open system with forced convection.<br />

• To support solution oriented analysis for industries like avionics & space, computer &<br />

instrumentation, telecom & industrial controls, automotive and power supplies.<br />

• Provision to create component models from component datasheet.<br />

HyperLynx DRC<br />

HyperLynx DRC tool should address design rule checking for issues with EMI/EMC, signal integrity<br />

and power integrity. This tool should support the following features:-<br />

• To check 19 standard design rules (DRCs) for items such as traces crossing splits, reference<br />

plane changes, shielding and via checks on PCB board that can cause issues with EMI/EMC,<br />

signal integrity (SI), and power integrity (PI).<br />

• To support custom rule creation including a script debugger with geometry visualization.<br />

• To support script writing and debugging environment built into the GUI that should allow to set<br />

break points, walk through the script step by step and add variables to a watch list.<br />

• To support results viewing, parameterized rule control, custom rule analysis & authoring and rule<br />

debugging<br />

Training : Technical training on Signal Integrity, Power Integrity, Thermal Analysis & DRC<br />

Tool shall be provided to <strong>IGCAR</strong> engineers. Specialized training on any of the above<br />

modules shall be quoted separately.<br />

Acceptance Criteria : The above tool specifications shall be tested & demonstrated against<br />

<strong>IGCAR</strong> designed PCB layout files.<br />

License : Single user node lock perpetual to run on Windows 7 or XP.


Specification of Workstation for running EDA Tools - 4 Nos.<br />

i) Processor : Intel Quad Core i7 3820QM or better<br />

ii)<br />

iii)<br />

iv)<br />

Clock Speed : 2.7 GHz or better<br />

Cache Memory : 8 MB L3 or higher<br />

Memory : 16 GB DDR3 upgradable up to 32 GB<br />

v) Hard Disk : Two 1TB 7200 RPM SATA2 (3Gbps)<br />

vi)<br />

vii)<br />

Graphics card with 1 GB dedicated on-board graphics memory (Nvidia or equivalent)<br />

Key Board : USB Keyboard<br />

viii) Mouse : Optical Mouse<br />

ix)<br />

Display : 22” HDMi widescreen LED monitor (Samsung/LG/DELL or equivalent)<br />

x) Optical Drive : DVD +/-R/W<br />

xi)<br />

xii)<br />

Network Interface : 10/100/1000M bit Ethernet LAN<br />

I/O Ports : 1xParallel/1xSerial/6xUSB Ports<br />

xiii) Audio : Audio In, Out and MIC with multimedia kit<br />

xiv) Casing : Good housing for PC with provision for heat removal<br />

xv)<br />

OS : Genuine Windows 7 professional, Media Kit, genuine licenses & manuals (firewall<br />

enabled and all security updates and patches and fixes up-to-date)<br />

xvi) Other S/W : Latest version of Microsoft Office Professional edition<br />

xvii) Anti Virus : Anti Virus software should be installed with licenses<br />

xviii) Warranty : 1 years comprehensive on-site manufacturer authorized warranty<br />

<strong>NO</strong>TE:<br />

- After publishing the tender, if there is any change in specification, it will be published as<br />

corrigendum in the <strong>MRPU</strong> portal.<br />

- Remarks column shall be utilized only for filing up non financial aspects such as make, packing<br />

etc…,<br />

- Aspects having an implication on the price shall be given in the column provided for the same<br />

and not in the remarks column.<br />

- Scanned copy of the quotation should not be uploaded separately.<br />

- Technical details/ catalogues/drawings etc, if any, shall be uploaded separately.<br />

- Breakup Cost of the Tool & Workstation should be quoted separately in the online ‘Price Bid<br />

Alternate Offer’ form<br />

- Accessories, Spares, Breakup costs etc. if any, shall be quoted online in the ‘Price Bid Alternate<br />

Offer’ form only.

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