A Hardware Implementation of Genetic Algorithm for Extraction of ...

, No. CAS2000-131, DSP2000-189, CS2000-151, pp. 29-36, March, 2001.
FPGA
980-8579 05
(Genetic Algorithm: GA) GA
(GAP) GA
GA GAP GA
GA GA
GAP GA
GAP
350 GA
, , FPGA, GA
A Hardware Implementation of Genetic Algorithm for Extraction of Disconnected
Closed Loops Using FPGAs
Ryoichi KOBAYASHI, Masahide ABE and Masayuki KAWAMATA
Department of Electronic Engineering,
Graduate School of Engineering, Tohoku University
Aoba-yama 05, Sendai, 980-8579, Japan
Abstract This paper proposes the Genetic Algorithm Processor (GAP) specified for the disconnected closedloop
extraction problem, and evaluates its performance. This extraction problem is one of the typical GA applications
in which the fitness evaluation requires considerably computation time and the length of chromosomes is
variable. The GAP is suitable for such a GA application. This paper also constitutes the distributed parallel GA
that reduces the computation time and improves the performance of a search. Experimental results show that the
execution speed of a GAP is more than 350 times faster than the software-based GA. Experimental results also
show that the speed of computation is approximately proportional to the number of GAPs.
Key words
extraction of disconnected closed loops, genetic algorithm, FPGA, GA hardware

, No. CAS2000-131, DSP2000-189, CS2000-151, pp. 29-36, March, 2001.
1
(Genetic Algorithm: GA)
1975 Holland GA
GA
GA
[1–4]GA
GA
GA
GA
GA
(1) GA
(2)
(3)
GA
[5–7] GA
(GA Processor: GAP) FPGA
GAP
GA
GA
GA
GAP
GA GA
2 GA
3
4 GAP FPGA
5 GA
6
2 GA
2.1
GA
GA
Step 1.
Step 2.
Step 3. 2
Step 4.
Step 5.
Step 6.
Step 2
2.2
2
2
1
2
2 2
GA
[5–7]
[5]
[5]
GA

, No. CAS2000-131, DSP2000-189, CS2000-151, pp. 29-36, March, 2001.
3
2
4
O
x o
, y )
(
o
5
1
1
0
6
0
1:
3:
2
1
3
0
4
5
6
2:
2.2.1
3
O(x o ,y o )
O O
x O
θ
2.2.2
4
2.2.1
1
4:
0
M M 4
0, 1, 3, 5, 6
2.2.3
[5]
[5]
2.2.4
[5]
D = 1 N
N−1
∑
i=0
d i (1)
N d i
( 4 )

, No. CAS2000-131, DSP2000-189, CS2000-151, pp. 29-36, March, 2001.
2
3
4
d 1
1
5
d 0
0
6
5:
D
1: GAP
2 n (n =1, 2, 3, ···, 11)
36, 37, ···, 512
16
0, 1, ···, 4095
0/255, 1/255, ···, 255/255
0/255, 1/255, ···, 255/255
0/8191, 1/8191, ···, 255/8191
1, 2, ···,16
GA
GA
2
256 256
3 GA
3.1
GAP( 1 )
GA
GA GA
GA
GA
()
()
GAP GA
1 GAP
GAP 2
GA
GA
GA
6 GAP
GA
GAP
6: GAP
3.2
3.3 GA
3.3.1
GA
GAP

, No. CAS2000-131, DSP2000-189, CS2000-151, pp. 29-36, March, 2001.
Pc
>
reg
MUX
MUX
7:
4
2, 6, 5, 6
Step 1
(
)
Step 2
3.3.2
16
1
3.3.3
7
P c
P c
GAP 1
0 1 50%
3.3.4
8 1
P m
8:
P m
P m
3.3.5
2 (1)
d i
GA
GAP
3.3.6
3.4
GA
GAP
3.5 (RNG)
GAP
[8] 46
Rule90 : s(i) + = s(i − 1) ⊕ s(i + 1) (2)

, No. CAS2000-131, DSP2000-189, CS2000-151, pp. 29-36, March, 2001.
Rule150 : s(i) + = s(i − 1) ⊕ s(i) ⊕ s(i + 1) (3)
0
3.6
1
2:
16 32 64 128
Slice 1070 1269 1288 1319
BRAM 5 6 10 18
[ns] 24.53 24.47 26.22 27.65
[MHz] 40.78 40.87 38.14 36.17
(Soft)[s] 13.8 29.7 62.6 130.0
(Hard)[s] 0.040 0.079 0.168 0.354
Soft/Hard 346 376 372 367
4
4.1
(HDL)
Verilog-HDL
2,438 Avant!
Polaris Synplicity
Synplify
Xilinx
Xilinx Virtex XCV1000-
6
4.2
GAP Virtex XCV1000-6
2
GA 800
(Pentium II 400MHzC
)
Slice BRAM
Xilinx
Slice FPGA
BRAM
Soft/Hard
GAP
GAP
350
5 GAP
5.1
GAP GA [9]
GA
GA
9: Ring GA
10: 8 GA
GA
9
GA (1)
GAP1 (2) GAP
GA

, No. CAS2000-131, DSP2000-189, CS2000-151, pp. 29-36, March, 2001.
11: 8 GA
14:
2
(1)
12:
(2)
5.2
3 (128 )
GAP
800
()
14
8 8
GAP
1
13:
10 8
11 8
12 13
5.3
3
GA

, No. CAS2000-131, DSP2000-189, CS2000-151, pp. 29-36, March, 2001.
3: GA
1 2 4 8
Slice 1319 2566 5050 9832
BRAM 18 19 21 25
[ns] 27.645 28.111 27.815 25.782
[MHz] 36.173 35.573 35.952 38.787
[s] 0.3540 0.1804 0.0897 0.0420
1.0000 1.9616 3.9470 8.4383
[1] S. D. Scott and S. Seth, “HGA: A hardware-based
genetic algorithm,” Proc. ACM/SIGDA, 3rd Int’l
Symposium on FPGA, pp. 53–59, 1995.
[2] B. C. H. Turton and T. Arslan, “A parallel genetic
VLSI architecture for combinatorial real-time
application - disc scheduling,” Proc. Genetic Algorithms
in Engineering Systems : Innovations and
Applications, pp. 493–500, 1995.
[3] , , , , , , “
,” , vol. 35, no. 11,
pp. 1496–1504, 1999.
[4] , , , , , , “
LSI
,” , vol. 41, no. 6,
pp. 1766–1775, June 2000.
[5] , “ GA
,” , vol. 26, no. 5,
pp. 591–598, 1997.
15:
15 () 1, 2
4, 8
6
GA
GA (1)
(2) (3)
GA
GAP
1
GAP
350
GA
GAP
GA
[6] , , , “
,” 15
, pp. 563–568, 2000.
[7] M. Abe, T. Shimada and M. Kawamata, “Extraction
of outlines with acute-angle corners using
genetic algorithm based on factors for perceptive
grouping,” Proceedings of IEEE International
Symposium on Intelligent Signal Processing and
Communication Systems, pp. 557–560, Dec. 1999.
[8] P. D. Hortensius, H. C. Card and R. D. McLeod,
“Parallel random number generation for VLSI using
cellular automata,” IEEE Trans. Comput,
vol. 38, pp. 1466–1473, Oct. 1989.
[9] R. Tanese, “Distributed genetic agorithms,” Proceedings
of the Third International Conference on
Genetic Algorithms, pp. 434–439, June 1989.