Optimization and implementation of a multi-level buck converter for ...

International Workshop on Power Supply On Chip
September 22nd - 24th, 2008, Cork, Ireland
Optimization and implementation of a multi-level buck converter
for standard CMOS on-chip integration
Vahid Yousefzadeh,
Toru Takayama
Dragan Maksimović
Colorado Power Electronics Center
ECE Department, 425 UCB
University of Colorado
Boulder, CO 80309-0425
maksimov@colorado.edu
Gerard Villar
Eduard Alarcón
Dept. of Electronic Engineering
Technical University of Catalunya
Campus Nord UPC – Building C4
08034 Barcelona, Spain
ealarcon@eel.upc.edu

Outline
• Introduction and motivation
• Series-connected multiphase multilevel buck converter
– Ideal topology. Amplifier and regulator operation
– Self-driven low-floating-capacitor PFM-operated 3-level converter
• Design-space optimization
• Mixed-signal implementation in 0.25µm TSMC CMOS
– Air-core bondingwire-based inductor, tapered buffer and transistor design
– Inductor current zero-crossing detection circuit
• Conclusions

Outline
• Introduction and motivation
• Series-connected multiphase multilevel buck converter
– Ideal topology. Amplifier and regulator operation
– Self-driven low-floating-capacitor PFM-operated 3-level converter
• Design-space optimization
• Mixed-signal implementation in 0.25µm TSMC CMOS
– Air-core bondingwire-based inductor, tapered buffer and transistor design
– Inductor current zero-crossing detection circuit
• Conclusions

3-Level (2-cell) Buck Converter
• 3-level (2-cell) converter
has been proposed for high
voltage inverters [Meynard
et al., 1992]
•“g 1 -g 2 ” & “g 3 -g 4 ” are
complementary switches
• g 1 and g 3 have the same
duty cycle
• V C = ½ V in
g 1
g 3
V SW
V C V in V in -V CV in V C
(D > 0.5)
T s
V in
V in /2
0 T s /2
t
• Objective:
Investigate potential for
lower ripple/ higher
efficiency / lower reactive
component size / higher
bandwidth realization of
DC-DC converter

Ripple comparison of 3-level and buck converter with same f s , L, C
Inductor current ripple i
1
0.8
0.6
0.4
0.2
Switching Ripple in the 3-Level Buck Converter
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Duty cycle D
4 times smaller peak inductor
current ripple
1
∆imax_
n = ∆i
2
n −1
i 2
i 3
( )
max_ 2
Output voltage ripple v (mV)
120
100
80
60
40
20
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
8 times smaller peak capacitor
voltage ripple
1
∆vmax_
n = ∆v
3 max_ 2
n −1
( )
Ripple results similar to two-phase converter, but with a single, smaller inductor

3-Level (2-cell) Buck Converter
Comparison of 3-level and buck converter
• For ∆v max
= 12 mV, f s_3
= 200 kHz, f s_2
= 560 kHz ⇒ η 2
= 0.83 and η 3
= 0.92
⇒ improved efficiency
• Same f s
, ∆v o
∆i L
⇒ L 3
= 0.25L 2
, C 3
=
0.5C 2
⇒ reduced area
Example application to
switching power amplifier

Two-Tone Signal Generation Using a
3-Level and a Buck Converter
A two-tone signal generated with a three-level and a buck
converter.
Switching frequency, f s = 1MHz, f sig = 100kHz, f o = 550kHz, Q = 1

Experimental Envelope Tracking Waveforms
V out
Frequency spectrum
V out
of V out
Frequency spectrum
of V out
Harmonic components
of rectified sinusoid
Switching harmonics
Harmonic components
of rectified sinusoid
Switching harmonics
Standard buck converter
3-level buck converter
• Standard buck and 3-level buck compared for the same open-loop
bandwidth and the same switching frequency
• Modulation: rectified sine-wave at f m = 20 kHz
• 30dB lower switching-frequency harmonic in the 3-level converter

Flying capacitor voltage control
g 1
sample
sample
V SW
+
_
g 3
V SW
V in -V C
V C
V in -V C
V C
0 T s /2
t
• Digital (verilog) controller
implementation using FPGA
T s
• x and y are sampled at
V sw = V C or
V sw = V in - V C
V in
V in /2
C x
g 3
g 4
g 1
+
V C
V in -
g 2
g 1 =d(t)
g 3 =d(t)+ d
y
x
V in /2 - V q /2
V SW
+
_
V in /2 + V q /2

Experimental waveforms for
flying capacitor voltage control
V sw
g 1
V in
-V c
V c
Uncontrolled
capacitor C x
voltage
V in
-V c
V c
D < 0.5
g 3
D > 0.5
V sw
g 1
V in
-V c
V c
Controlled
capacitor C x
voltage
V in
-V c
V c
g 3
D > 0.5
D < 0.5

Outline
• Introduction and motivation
• Series-connected multiphase multilevel buck converter
– Ideal topology. Amplifier and regulator operation
– Self-driven low-floating-capacitor PFM-operated 3-level converter
• Design-space optimization
• Mixed-signal implementation in 0.25µm TSMC CMOS
– Air-core bondingwire-based inductor, tapered buffer and transistor design
– Inductor current zero-crossing detection circuit
• Conclusions

3-level self-driving PFM low-Cx buck converter
Low-C x resonant 3-level buck converter in DCM. Self-driving transistor-level topology
Self-driving scheme to interconnect power transistors and drivers, which
reduces the voltage across the power MOSFETs gate dielectric.

3-level self-driving PFM low-Cx buck converter
• Use of core transistors to implement the power MOSFETs
• Use of core transistors to implement power drivers of P 2 & N 2
• Reduces the power consumption of the power drivers
37 MHz switching frequency
26 nH inductance
Driver supply voltage and vgs for all power MOSFETs,
Cadence transistor-level simulations.

3-level self-driving PFM low-Cx buck converter
Output voltage ripple as a function of V o , for
the 3-level (C x sweep) and the classical
(dotted line) Buck converters.
L=35nH
C o
=30nF
f s
=25MHz
V bat
=3.6V
V o
=1V
I o
=100mA
Control signal-to-output voltage transfer
function comparison between the 3-level (C x
sweep) and the classical (dotted line) Buck
converters.
Representative waveforms corresponding to a DCM
operated 3-level Buck converter, duty cycle below 50%

Outline
• Introduction and motivation
• Series-connected multiphase multilevel buck converter
– Ideal topology. Amplifier and regulator operation
– Self-driven low-floating-capacitor PFM-operated 3-level converter
• Design-space optimization
• Mixed-signal implementation in 0.25µm TSMC CMOS
– Air-core bondingwire-based inductor, tapered buffer and transistor design
– Inductor current zero-crossing detection circuit
• Conclusions

Circuit topology considerations
Optimized design space exploration (II)
1) Model each performance index (ripple,
efficiency and area) as a function of design
parameters: inductor, capacitor and
switching frequency
+
i in
+
V in
-
iL
R W +R C L
Q 2
Q 1
T s =1/f s
d(t)
C
i out
+
V out
-
R
D=T on /T s
∆v
o
=
VoDT
RC
s
=
VoD
RCf
s
=
T on
)
A priori parameters and assumptions are application-oriented:
topology, V in , V out , and the target IC technology parameters.
Output voltage ripple
f
∆v
o
( L,
C,
fs
)
Efficiency
Occupied area
Vin
I
L
− PL
−DC
− PL
−core
− PQ
−all
η =
=
V I
in
L
f
η
( L,
C,
f
s
Area = AC
+ AL
+ 2AQ
= farea
( L,
C,
fs
)

Circuit topology considerations
Optimized design space exploration (III)
2) Define a merit figure encompassing the
performance indexes to be maximized or
minimized
Output
voltage
ripple
f
L
C
f
C
L
generic merit figure
Γ(
x
x ) =
∏
i
∏
β f
γ i
i
1,...,
n
γ j
β
j
f
j
j
i
( x
( x
1,...,
1,...,
Boost converter case example merit figure
x
x
n
n
)
)
Efficiency
Occupied
area
∆v o
η
A
f
L
L
f
C
C
f
f
C
C
L
L
fη
( L,
C,
fs
)
Γ( L,
C,
fs)
=
2
f ( L,
C,
f ) ⋅ f ( L,
C,
f
A
s
∆v
Note that the area dependence is square-weighted
so as to solve the ill-conditioned solution of
∆vo→∞ when A→0.
o
s
)
Merit
figure
Γ
f
L
f s
={1MHz,100MHz}, L={10nH,1uH}, C={10pF,10nF}
C
f
C
L

Circuit topology considerations
Optimized design space exploration (IV)
Design example for a standard 0.35 µm CMOS technology
3) Obtain optimum point within
design space (L,C, f s
) as regards
efficiency, occupied area,
functionality
V out
(V)
I L
(A)
Specs: ∆ vo
=0.1 V i out
=0.4 A
Optimization result: L= 30 nH, C= , f s = 50 MHz
+
i L
i in 0.82 Ω 30 nH
2.5 V
W=3352 µm
L=0.35 µm
k core=221⋅10 -11
δ L=0.04 H/m 2 W=3352 µm
L=0.35 µm
W=2500 µm
L=2500 µm
i out
+
3.3 V
- 16.5Ω

Optimized design space exploration
3-level converter design example for a standard 0.25 µm CMOS technology
Design space exploration of a CMOS-compatible 3-level
converter: 70% efficiency, 5mm 2 silicon and f s =37 MHz

Outline
• Introduction and motivation
• Series-connected multiphase multilevel buck converter
– Ideal topology. Amplifier and regulator operation
– Self-driven low-floating-capacitor PFM-operated 3-level converter
• Design-space optimization
• Mixed-signal implementation in 0.25µm TSMC CMOS
– Air-core bondingwire-based inductor, tapered buffer and transistor design
– Inductor current zero-crossing detection circuit
• Conclusions

Bondwire triangular spiral inductors in standard CMOS
•Area underneath inductor is usable for capacitors and power MOSFETs

Power MOSFETs
Complete loss optimization of on-chip CMOS synchronous rectifier
W P = 3092µm
W N = 2913µm power
drivers with 7.59 and 7.48 tapering factors
Overall losses 37.1mW
Breakdown of loss distribution, corresponding
the optimized design of power MOSFETs and
their associated drivers.

Power MOSFET gate drive design
Additional degree of freedom: impact of W p
upon efficiency and delay
Q i
and Q e1
variation as a function of the PMOS channel
width of the minimum inverter (W n
= 0.3µm)
t fri
and t fre1
parameter variation
Total energy losses as a function of the number of inverters n and the
minimum inverter PMOS channel width W p
. The area includes all the
designs constrainted to a propagation delay lower than 1.15 ns.

iL=0 detection circuit. Event detection
i L >0
i L

iL=0 detection circuit. Circuit for time adjustment. Inductor current observer

iL=0 detection circuit Mixed-signal implementation in 0.25µm CMOS
i L >0
N 1
N 2
7.9
i L

Time-domain performance of iL=0 detection circuit
Before adjustment
After iL=0 adjustment
7.10

Complete integrated 3-level CMOS switching power converter
P 1
2630 µm
2370
µm
P 2
N 1
N2 7.17

Full-transistor-level circuit results (I)
7.19

Full-transistor-level circuit results (II)
7.20

Full-transistor-level circuit results (III)
7.21

Experimental results

Outline
• Introduction and motivation
• Series-connected multiphase multilevel buck converter
– Ideal topology. Amplifier and regulator operation
– Self-driven low-floating-capacitor PFM-operated 3-level converter
• Design-space optimization
• Mixed-signal implementation in 0.25µm TSMC CMOS
– Air-core bondingwire-based inductor, tapered buffer and transistor design
– Inductor current zero-crossing detection circuit
• Conclusions

Conclusions
• Three-level converter results in favorable trade-offs in terms of decreasing the switching ripples,
decreasing the switching frequency, reducing the size of the filter elements, increasing the
converter open-loop bandwidth, or increasing the converter efficiency.
• The 3-level converter with low-Cx, self-biased drivers and operating in DCM/PFM has been
presented as a candidate for DC-DC converter integration
• The use of the self-driving scheme to supply the drivers allows the use of thin-oxide transistors
which increases the performance of the switches.
• Design optimization results in the 3-level converter outperforming the Buck converter.
Future research lines
• Linear-assisted scheme for multilevel converters
• Explore extending the approach to more intermediate levels
• Use different modulations (e.g. asynchronous sigma delta)
• Applying time optimal control