D/AVE 2D Data Sheet - TES Electronic Solutions

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Approved TD-240201SH DS 2.3 AVALON Toplevel TES is offering the D/AVE IP as an ALTERA® SOPC-Builder ready component. IRQ IRQ Slave Bus Config./Status Interface AVALON Slave Bus Adaptor AVALON R/W Slave Signals Master Bus Display List Interface AVALON Master Bus Adaptor AVALON Read Master Signals Master Bus Texture/RLE Interface AVALON Master Bus Adaptor AVALON Read Master Signals Master Bus Framebuffer Read Interface Master Bus Framebuffer Write Interface AVALON Master Bus Adaptor AVALON R/W Master Signals Image 2-3 AVALON Toplevel The component can be configured to use a single master interface instead of the configuration shown above. The Avalon ‘Burstcount’ mode can be used or not. External bus width as well as cache sizes are configurable. The AVALON specific signal description is not part of this document. Title D/AVE 2D Data Sheet Version 2.9 Date 2012-08-01 Sign Number TD-240201SH DS Author Christian Sehnke Page 12/42
Approved TD-240201SH DS 2.4 AMBA Toplevel TES is offering a configurable ARM AHB/APB interface for D/AVE. IRQ IRQ Slave Bus Config./Status Interface AMBA APB Slave Bus Adaptor AMBA APB R/W Slave Signals Master Bus Display List Interface AMBA AHB Master Bus Adaptor AMBA AHB Read Master Signals Master Bus Texture/RLE Interface AMBA AHB Master Bus Adaptor AMBA AHB Read Master Signals Master Bus Framebuffer Read Interface Master Bus Framebuffer Write Interface AMBA AHB Master Bus Adaptor AMBA AHB R/W Master Signals Image 2-4 AMBA Toplevel Configurable features are: - Three vs. single AHB master interface - Data width of AHB interface - Support locked transfers - Supported transfer sizes: Cache on: WORD (depending on bus width) Cache off: WORD, HALFWORD, BYTE (depending on frame buffer format) The AHB master bus adaptor implements the AHB interface with the following constraints: - No BUSY cycles generated - No wrapping bursts or incrementing bursts of unspecified length performed - No SPLIT and RETRY responses supported, ERROR responses generate interrupts - Narrow writes on wide bus (in case the cache is disabled) - Use of locking mode can be enabled. The complete AMBA specific signal description is not part of this document. Title D/AVE 2D Data Sheet Version 2.9 Date 2012-08-01 Sign Number TD-240201SH DS Author Christian Sehnke Page 13/42
Page 1 and 2: D/AVE 2D Data Sheet Look ´n´ Feel
Page 3 and 4: Approved TD-240201SH DS 8.2 TEXTURE
Page 5 and 6: Approved TD-240201SH DS 1. INTRODUC
Page 7 and 8: Approved TD-240201SH DS 2. SIGNAL D
Page 9 and 10: Approved TD-240201SH DS 2.2.1 Gener
Page 11: Approved TD-240201SH DS 2.2.6 Frame
Page 15 and 16: Approved TD-240201SH DS 3.2 Configu
Page 17 and 18: Approved TD-240201SH DS 3.7 2D Rend
Page 19 and 20: Approved TD-240201SH DS 3.7.3.2 Ble
Page 21 and 22: Approved TD-240201SH DS 4. REGISTER
Page 23 and 24: Approved TD-240201SH DS D2C_BSI 11
Page 25 and 26: Approved TD-240201SH DS Name Bits D
Page 27 and 28: Approved TD-240201SH DS COLOR1_GREE
Page 29 and 30: Approved TD-240201SH DS 4.4.2 D2_ T
Page 31 and 32: Approved TD-240201SH DS 4.5 Misc. R
Page 33 and 34: Approved TD-240201SH DS 24 = frameb
Page 35 and 36: Approved TD-240201SH DS 6. OPERATIO
Page 37 and 38: Approved TD-240201SH DS 7.5 Memory
Page 39 and 40: Approved TD-240201SH DS 7.7 Driver
Page 41 and 42: Approved TD-240201SH DS IMAGES Imag

D/AVE 2D Data Sheet - TES Electronic Solutions

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