Impact of RTN on Vmin elevation of 6-T bitcell designs

<strong>Impact</strong> <strong>of</strong> <strong>RTN</strong> on Vmin elevation <strong>of</strong> 6-T bitcell designs
Sudha Thiruvengadam, SengOon Toh, Huong An, Stephen Kosonocky, Keith Kasprak, Jason Mulig
The impact <strong>of</strong> <strong>RTN</strong> (Random Telegraph Noise) on 6T SRAM
array designs is described. <strong>RTN</strong> is due to the switching noise
caused by the capture and emission <strong>of</strong> charge carriers in the
gate oxide traps. This leads to the modulation <strong>of</strong> threshold
voltage (∆Vth) or drain current (∆Ids) across the device [1].
Since ∆Vth is inversely proportional to the area <strong>of</strong> the device,
small SRAM devices are seriously impacted by <strong>RTN</strong>. The
2011 edition <strong>of</strong> the „International Technology roadmap for
Semiconductors‟ describes <strong>RTN</strong> as having a greater reliability
impact on smaller devices than BTI [2].
time for which <strong>RTN</strong> has an impact (order <strong>of</strong> ms). As shown in
Fig 2b, the traps stay occupied for > 10 ms.
While <strong>RTN</strong> and BTI are both due to charge trapping, <strong>RTN</strong> is
mainly due to hole trapping and has shorter stress times (< 1
sec) while BTI is due to interface traps and has a longer stress
time. [3]. Design margin for <strong>RTN</strong> should not be simply added,
because it is already partially accounted for within the design
margin for BTI degradation.
Literature shows that the threshold voltage could be
modulated by as much as 200mv as a result <strong>of</strong> overlapped
<strong>RTN</strong>s as shown in Fig 1. In an SRAM cell, the beta ratio is
critical for stability. Any change in the threshold voltage
affects the beta ratio and hence, the stability <strong>of</strong> the bitcell.
SRAM device widths scale by almost 50% from one process
node to the next, and therefore the impact <strong>of</strong> <strong>RTN</strong> increases
with scaling. Tega et al. analyzed the impact <strong>of</strong> <strong>RTN</strong> on n-fets
and p-fets and showed that the ∆Vth fluctuation is greater in
p-fets [4]. The authors reason that the scattering coefficient <strong>of</strong>
p-fets is greater than that <strong>of</strong> n-fets by an order. Mobility <strong>of</strong>
charge carriers is limited by the scattering coefficient.
Furthermore, the cross-section <strong>of</strong> hole traps is greater than that
<strong>of</strong> electron traps so that the chances <strong>of</strong> overlapped <strong>RTN</strong>s are
greater in p-fets.
Agostinelli et al. have shown that SRAM Vmin (minimum
operating voltage) is non-deterministic as a result <strong>of</strong> <strong>RTN</strong> [5].
In this paper, we identify the patterns that expose the worstcase
Vmin deterioration due to <strong>RTN</strong>. Since <strong>RTN</strong> is a
stochastic process with large time constants, a large number <strong>of</strong>
datasets are needed to identify the impact <strong>of</strong> it. We use
measurement data from approximately 40 units to determine
the Vmin elevation due to <strong>RTN</strong>.
Fig 2 Time duration <strong>of</strong> <strong>RTN</strong> effects[5]
Fig 3 <strong>Impact</strong> <strong>of</strong> <strong>RTN</strong> on isolated writes (insert nops between write 1
and final write2)
In order to determine the impact <strong>of</strong> <strong>RTN</strong> on writes, we
considered two cases – in one case, the cell was kept idle for 1
second (determines the impact <strong>of</strong> <strong>RTN</strong> on PU only) followed
by a single write. In the second case, after holding the cell in
idle mode for 1 second, writes <strong>of</strong> opposite value were made to
the cell (determines impact <strong>of</strong> <strong>RTN</strong> on PG and PU). In the
write-after write case, we tried a number <strong>of</strong> different options –
write 0, write 1 (and vv), write 0 (x times), and write 1 (x
times) where x varied from 2 to 256.
Let us determine the impact <strong>of</strong> keeping the cell idle (NOPs)
for multiple seconds. Say, node CL is high and CH is low.
Initial conditions are such that trap occupancy is forced in
PU1 degrading its Vt and a „0‟ is easily written to the bitcell.
We follow this up with subsequent NOPs for one second or so.
In this case, the pass-gate is not active. Over the period <strong>of</strong> 1
second, trap occupancy has been forced into PU2 since node
CL is low causing its Vt to degrade and allowing a write <strong>of</strong> a
„1‟ to the bitcell. Fig 3 summarizes the different trap states.
Fig 1 <strong>Impact</strong> <strong>of</strong> <strong>RTN</strong> on threshold voltage τ e and τ c (emission and
capture times) are random and follow exponential distributions[4]
In a typical SRAM cell, even when the bitcell is not being
accessed, one set <strong>of</strong> pullup and pulldown devices remain on.
Measurement techniques need to simulate the condition that
one set <strong>of</strong> devices has been on for a long time[6]. So, the gate
current is pulsed a second before measuring the drain current
on the device. This process is repeated fifty times so as to
measure the average drain current and determine the length <strong>of</strong>
Fig 4a and 4b outline the patterns that highlight the impact <strong>of</strong> <strong>RTN</strong>
on writes

Next, we determine the impact <strong>of</strong> <strong>RTN</strong> when we follow the
multiple NOPs with a write-after-write pattern to the bitcell.
Initial conditions are such that node “CH” is high and “CL” is
low. PU2 has trap occupancy forced into it causing the Vt to
be degraded thus allowing a write <strong>of</strong> a “0” (pulling CH low).
When we do multiple write <strong>of</strong> „0s‟ to the bitcell PU1 is
constantly exercised. Trap vacancy in PU1 improves its
threshold voltage so that writing a “0” on node CL is much
harder and could even fail. Finally, although the PG
transistors are only turned on for a short duration during
SRAM cell access, sequential pulses on PG1 during writeafter-write
access are sufficient to force trap occupancy in
PG1 and degrade Twrite <strong>of</strong> the final operation. Fig 4
describes the isolated write and write-after-write patterns and
the test algorithm used.
Isolated
Write
T hold
T write
Preset A Hold Write A
boundary]. The Vmin in the other cases was lower than it was
for the write-after-write. It is commonly accepted that traps
causing transistor degradation due to <strong>RTN</strong> have a time
constant within 1 sec while those due to BTI have a much
longer time constant. Since all the test patterns we applied are
for 1 sec or less, the effects we are characterizing are solely
due to <strong>RTN</strong>.
Fig 6a and 6b outline the basic patterns to determine the
cause <strong>of</strong> the Vmin failure
Write
After
Write
T hold T relax T write
Preset A Hold Write A Write A
Fig 4c and 4d Patterns used to test impact <strong>of</strong> <strong>RTN</strong> on writes to the
bitcell
The Vmin <strong>of</strong> a bitcell is the minimum operating voltage at
which reads and writes occur. Due to <strong>RTN</strong>, we would observe
elevated Vmins following a write-after-write operation.
Successive WL pulses degrade reads and writes while read
stability (ADM) improves as shown in Fig 5.
Fig 5 <strong>Impact</strong> <strong>of</strong> <strong>RTN</strong> on write after write
In order to test the impact <strong>of</strong> these patterns on the Vmin <strong>of</strong> the
bitcell, we selected 40 units from 32nm silicon that had Vmin
failures due to SRAMs. These units had elevated Vmin at 0C
versus 95C indicating that writes were the problem (Fig 9).
BIST algorithms were run to identify the cause <strong>of</strong> Vmin
failures. A march algorithm consists <strong>of</strong> march lines, where
each march line is comprised <strong>of</strong> read, write, or read/write
combination called march elements. Each march line is
denoted with a ^ or v to represent the address direction. A
march line is run to completion at each address before moving
to the next address. When all addresses in the specified macro
have been tested, BIST will proceed to the next march line.
The BIST algorithms used to identify the units with write
Vmin fails are described in Fig 6.
There are a number <strong>of</strong> patterns in our test suite that
specifically look for issues that cause elevated Vmin, say
marginal bits due to elevated contact resistance, higher IR
drop, etc. For <strong>RTN</strong> we looked at trap characteristics and
applied test vectors within a short period which is within the
range <strong>of</strong> <strong>RTN</strong> trap time constant [1 second being the
Fig 7 Addressing mode used for <strong>RTN</strong>
Fig 7 shows an example <strong>of</strong> a 4-bit address used in an array
with 4 rows and 4 columns per data bit slice (2 data bits
shown). The effective addressing achieved by fast column and
Fast Row is listed in Table 4.62. In fast column, the rows are
held while traversing the columns. In fast row mode, the
columns are held while traversing the rows. BIST testcases
normally use fast-column addressing but that leads to passgates
being turned on for the non-selected columns. In order
to avoid that, fast-row addressing was used which we felt gave
a more accurate picture <strong>of</strong> the impact due to <strong>RTN</strong>.
Fig 8 shows the shmoo (normalized voltage versus frequency)
plots for two <strong>of</strong> the units where we can observe that the <strong>RTN</strong>
patterns have elevated Vmin. We can also see that the writeafter-write
case has the highest Vmin.
1.60
1.56
1.52
1.48
1.44
1.40
1.36
1.32
1.28
1.24
1.20
1.16
1.12
1.08
1.04
1.00
VDD
Isolated
Write -5C
200
800
200
WAW
-5C
800
Writeability
-5C
200
Frequency (MHz)
800
Readability
-5C
200
800

1.60
1.56
1.52
1.48
1.44
1.40
1.36
1.32
1.28
1.24
1.20
1.16
1.12
1.08
1.04
1.00
VDD
Isolated
Write -5C
200
800
200
WAW
-5C
800
Writeability
-5C
Readability
-5C
Frequency (MHz)
Fig 8 <strong>Impact</strong> <strong>of</strong> <strong>RTN</strong> patterns on write Vmin (20-60mv elevation) for
2 units out <strong>of</strong> the 40 tested (ISO implies isolated write, waw implies
write-after-write)
The tests were repeated at both -5C and 71C. The write-afterwrite
pattern showed an elevated Vmin at both temperatures
as shown in Fig 9.
200
800
200
800
1.750
1.625
1.500
1.375
1.250
1.125
1.000
Fig 10 <strong>Impact</strong> <strong>of</strong> <strong>RTN</strong> on Vmin for 40 units (average) at 200Mhz
In summary, we were able to successfully identify the <strong>RTN</strong>
testcases that impact the write Vmin <strong>of</strong> bitcells . By applying
these testcases to actual silicon, we were also able to show
that <strong>RTN</strong> causes write Vmins to be elevated by 20-60mv for
write-after-write operations.
REFERENCES
[1] S.O. Toh et al., in IEDM Tech. Dig., pp. 767-770, 2009.
[2] International Technology roadmap for
Semiconductors, 2011 Edition
[3] T. Grasser et al, in IEDM Tech. Dig., pp. 729-732, 2009.
[4] N. Tega et al, in IEDM Tech. Dig , pp. 491-494 ,2006
[5] M. Agostinelli et al, in IEDM Tech Dig, pp. 655-658, 2005
[6] S.O.Toh et al.,in Symp. VLSI Tech., pp. 204-205, 2011
ACKNOWLEDGEMENTS
The authors are grateful to Aaron Grenat, Andrew Kegel and
other managers for allowing this research to conclude
successfully.
1.750
1.625
1.500
1.375
1.250
1.125
1.000
Fig 9 <strong>Impact</strong> <strong>of</strong> <strong>RTN</strong> tests on write Vmin at hot and cold for the
above two units
Fig 10 shows the average elevation in Vmin due to writeafter-write
on the 40 units tested.