Dual-Output

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Fault Modeling • Assume a stochastic single fault model At most one fault occurring at a time A fault with identical random distribution for each SRAM bit • The criticality of a SRAM bit Combination of observability and signal probability Measured by the percentage of input vectors that cause observable output errors if a fault occurs in this SRAM bit. • The fault rate of a full-chip is the percentage of input vectors that cause observable output errors assuming the single fault. Fault rate is the average criticality of all SRAM bits
Two Atomic Operators in FT by DO LUTs Criticality of LUT A can be reduced Encoding at the fanout LUT ` (a) Original LUTs Duplication of a LUT (b) LUTs after duplication and encoding • The criticality of LUT A can be reduced after duplication and encoding • A duplication and a encoding needs one unused pin, respectively.
Page 1 and 2: Fault-Tolerant Resynthesis for Dual
Page 3 and 4: The Need for Light-Weight Fault-Tol
Page 5 and 6: Dual-Output (DO) LUTs in Modern FPG
Page 7: Potential of the Optimization using
Page 11 and 12: FMD Impact on SRAM Criticality Dupl
Page 13 and 14: FMD Impact on SRAM Criticality (con
Page 15 and 16: Partial Masking-based Duplication (
Page 17 and 18: Experimental CAD Flows
Page 19 and 20: MTTF & Performance Overhead
Page 21: Thank you! Electronic Design Automa

Dual-Output

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