Packet Processing to support 40 /100GE Line Rates - Ethernet ...

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Queuing and De-Queuing– This memory is dividedinto separate queueswith independent writeports– A single read port hasaccess to all queues• FPGA / ASIC: Multi-ported memory must beconstructed out of dual ported memories• Similar principle for a single write port to multipleread ports20© 2013 Tabula, Inc.
Broadcasting– A single write portprovides access to thebuffer for the input data– Independent ReadPorts have access to allof the data• FPGA / ASIC: Multi-ported memory must beconstructed out of dual ported memories© 2013 Tabula, Inc.21
Page 2 and 3: Agenda• Current Challenges• App
Page 4 and 5: Ethernet Stack: ProcessingChallenge
Page 6 and 7: Device Elements for PacketProcessin
Page 8 and 9: Performance Bottlenecks areEVERYWHE
Page 10 and 11: Application Requirements• Perform
Page 12 and 13: Tabula Solutions for 100GE PacketPr
Page 14 and 15: 100GE - 12x10GE Layer2 BridgeSanta
Page 16 and 17: Ternary Search EngineSanta Clara, C
Page 18 and 19: Spacetime Addresses TheInterconnect
Page 22 and 23: Data Selection / IndexingMemoryLogi
Page 24 and 25: Tabula Tools: Stylus®ASIC / ASSP /
Page 26 and 27: SummarySanta Clara, CA USA April201
Page 28 and 29: Want To Learn MoreSanta Clara, CA U
Page 30: QuestionsSanta Clara, CA USA April2

Packet Processing to support 40 /100GE Line Rates - Ethernet ...

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