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FFBalance power and timing in both clock and datafor better global solution.G. Shklover, ISPD '12 4

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FFBalance power and timing in both clock and datafor better global solution.G. Shklover, ISPD '12 4

Proposed by C. Chen et alExploits the nature of timing constraints toreduce complexityEfficient, suitable for industrial design flows(standard library with Vt/sizing).G. Shklover, ISPD '12 5

Page 1 and 2: Gregory ShkloverBen EmanuelIntel Co
Page 3: MethodologyClassStructureMethodsSke
Page 8 and 9: , , , → ,clkdFFq,, , , ,∈
Page 10 and 11: InitializeMultipliersSize GatesDyna
Page 12 and 13: Gate sizing: Solution merge: Le
Page 14 and 15: ...Exponentialnumber ofsolutionsk-S
Page 16: Total Slack Leakage ClkDPwr Total P
Page 19 and 20: G. Shklover, ISPD '12 19
Page 21 and 22: ?-20psFF+80psObjectivepowerG. Shklo
Page 23: G. Shklover, ISPD '12 23

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