Power Reduction Techniques for LDPC Decoders

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION SYSTEMS 7Control pins300ExtrapolatedMeasured1500ExtrapolatedMeasured3 mm44inputpins660VNUs&176CNUs44outputpinsMax. Frequency (MHz)250200150100Power (mW) (@ max. frequency)10005003 mm500.6 0.8 1 1.2V dd(V)00.6 0.8 1 1.2V dd(V)Fig. 13.Decoder die photo.Power (mW) (300 MHz, 1.2V)Fig. 14.16001200800400No early terminationWith early termination02 3 4 5 6 7 8Eb/No (dB)Decoder power consumption vs. input SNR.this value is already available from the sign-calculation blockinside the CNUs (Fig. 6).IV. RESULTSFig. 13 shows the die photo of the implemented decoder.The decoder performs 15 decoding iterations per frame as itwas shown in Fig. 8(b) that performing more than 12 iterationsresults in a negligible BER enhancement. It occupies 7.3 mm 2core area and operates at maximum frequency of 300 MHzwith a 1.2-V core supply voltage which results in a 3.3 Gbpstotal throughput. Since the code rate is 0.74, this correspondsto an information throughput of 2.44 Gbps. The measuredBER performance of the decoder matches bit-true simulations.The BER curve is practically identical to the BER graph inFig. 8(b) for I M = 16.The total decoder power consumption is shown in Fig. 14as a function of input SNR at 300 MHz with 1.2-V supplyvoltage. The solid line in this graph is directly obtained frommeasurements. It was observed that approximately 20% of thetotal power dissipation is due to the clock tree. It was alsoFig. 15. Effect of supply voltage scaling on maximum frequency and powerconsumption.observed that only less than 1.4 mW (i.e., 0.1% of the totalpower consumption) is due to leakage current. The graph inFig. 14 also shows that in contrast to the fully-parallel LDPCdecoder in [11], the power consumption is relatively flat for theSNR values of interest in this work. This is mostly becauseof the bit-serial message-passing and the block interleavingarchitecture which tend to maintain high switching activityindependent of the input SNR.The power consumption resulting from early termination asproposed in this work is shown by the dotted line in Fig. 14.Since early termination logic was not included in the fabricatedprototype, we have calculated the P D ′ data points on the dottedline from the P D data points on the solid line usingP ′ D = (1 + γ)(p c + α(1 − p c ))P D ,where γ accounts for the overhead of the early terminationlogic, p c is the fraction of dynamic power attributable to theclock tree, and α is the ratio of active iterations similar tothe values plotted in Fig. 10(b). This expression accounts forthe fact that early termination does not decrease the dynamicpower in the clock tree. As explained in Section III, γ for thereported decoder is estimated to be less than 0.006. As alsomentioned, our measurements show that p c is approximately0.2. The figure shows that early termination reduces the powerconsumption by between 58% and 66% in the practical SNRrange of interest between Eb/No=4 dB and Eb/No=5.5 dB.Fig. 15 shows the effect of supply-voltage scaling on themeasured maximum frequency and the total power dissipationat that frequency. The dotted lines are the predicted valuesbased on the MOS square-law equation with V t = 0.3V .It can be seen that the measured results closely follow thepredicted results both for maximum frequency and for thepower consumption.Table I summarizes the characteristics of the fabricateddecoder. In Table II the results from other LDPC decodersreported in literature are listed. The decoder architecture in