Advantages of FPGA-Based Multiprocessor Systems in Industrial ...

This paper argues and shows that FPGAs can at leastrelieve some of the design problems discussed above. To thisend, Section II briefly surveys the possibilities andadvantages of those FPGAs. A short introduction to thesimple and easy use of soft-core processors will be given.As Section III describes, FPGAs today have grown in sizesuch that they can even realize one or even several custommadeprocessor cores.In order to show the potential benefits, Section IVdescribes an industrial case study in the area of cutting-edgeoffset printing. Since the entire system has been grownduring several years, it exhibits some limitations, which alsohinder future developments. In order to expand to newfrontiers, this section also proposes a new architecture, whichis based on a multiprocessor platform.Section V reports on a prototypical implementation, whichcan be seen as a proof-of-concept. The section also discussesthe required resource consumption as well as other technicaldetails. Finally Section V and VI finish this paper with acritical discussion and the conclusion respectively.II. BACKGROUND ON FPGASFirst commercial FPGA’s were released by XILINX in themiddle of the 80’s of the last century. At those times, deviceswere small, slow, and quite expensive. The first XILINXdevice XC2064 had 1200 gates. Today, FPGA’s offermillions of system gates and operate at a speed of up to300 MHz. Since the price of currently available FPGAs startsbelow 10 US$, many manufactures use them even for endproducts, such as mobile phones, network solutions, andmultimedia devices.Even factory automation applications might profit from thegood performance-to-cost 2 ratio of modern FPGAs. Here,FPGAs are of particular interest, because a small number ofproduction systems require significant development efforts.Using FPGAs in the design process has the following threedistict advantages. First, most FPGA-vendors support thedesign and development process by providing powerful andeasy-to-use electronic design tools (EDA), excellentdocumentation, and personal support. Second, demonstrationexamples do not involve high manufacturing costs as wouldbe usual with ASICs. Third, modifications and adjustmentscan be implemented at any stage of the design process andeven “in the field”. Advanced systems extent the latter pointeven further in that they allow the dynamic reconfigurationof the running hardware. Such systems are subject of currentresearch efforts, also known as dynamically reconfigurablehardware [10]. This approach receives recent attention,because it allows for multiply re-using valuable resources.FPGAs have grown in size that much that they allow forthe soft-implementation of processor cores, which might alsobe a DSP-core. Thus, a design challenge is to decide, which2 In this context, “cost” refers not only to the actual FPGA but also torequired tools, design efforts, maintenance, etc.parts of the system, i.e., functionalities, are to beimplemented directly in hardware gates or processed bysoftware, which runs inside the FPGAs soft core. State-ofthe-artEDA-tools, such as ALTERA's system-on-aprogrammable-chip(SOPC) Builder and XILINX’Embedded Development Kit (EDK), simplify this parallelhardware-software co-design process dramatically. This isaccomplished by automatically recognizing all hardwarecomponents and providing software access methods forthem. Also, the development tools solve the address andresource management automatically on the fly (see alsoSection IV.C).Furthermore, the developer can resort to many ready-tousecomponents, also called intellectual properties (IP), suchas network-Interfaces, video controllers, memory controllers,and so forth. The usage of IP-cores reduces the developmentefforts and thus may help reduce costs.III. SOFT-CORES AND MULTIPROCESSOR SYSTEMSAs mentioned above, FPGAs offer the possibility ofincorporating soft-cores. Soft-core processors can beconsidered as equivalents to a microcontroller or “computeron a chip”. They combine a CPU, peripherals, and memoryon a single chip. They also provide access beyond the actualFPGA chip through integrated standard or custom-madeinterfaces. Some available reduced instruction set computer(RISC) architectures are [3, 4, 5]:1. NIOS and NIOS II CPUs from ALTERA ,2. LEON2 and LEON3 CPUs from Gaisler Research,3. and the Microblaze CPU from XILINX.Some of the currently available FPGAs allow for therealization of several processors simultaneously. As is wellknown, multiprocessor systems are a proper method toincrease system performance and to concentrate processingelements in one FPGA. Since multiprocessor systems aresupported by the EDA tools, the system generation can becompleted within a couple of days. Generally, most vendorssupport multiprocessor systems by providing dedicatedhardware constructs, such as mutexes, to synchronizedaccesses to shared resources. For a general introduction tomultiprocessor systems, the interested reader is referred tothe pertinent literature [7].IV. INDUSTRIAL CASE STUDYThis section presents an industrial case study. Thisincludes a description of the existing system, the discussionof the problems and goals, and the presentation of aprototypical implementation.A. The Existing SystemIn 1993, basysPrint Ltd. introduced a technology calledComputer To conventional Plate (CTcP) for the exposure

of printing plates for the offset printing process [12]. Adistinct feature of the CTcP technology is that it allows forusing ultraviolet-light-sensitive printing plates, which, incomparison to laser light exposition used by most othercompetitors, results in significant cost reductions because oflower acquisition and disposal charges. Fig. 1 shows anexample of a CTcP solution available from basysPrint.synchronizes the image updating with the exposure head’smovement. The PC transfers the appropriate image data via aLAN-connection to the exposure head prior to the imaging ofeach stripe. In addition the control-PC also has to handlevarious other control signals. For the system’s functionality,it is very important to ensure a precise coordination of headmovements and data timings, because even a singlemalfunction spoils the entire plate.exposure headbearingprinting plateplate holderterminalFig. 1: A CTcP system, called UV-SetterControl-PCLAN Trigger-Card Interbuswire drag chainmotorX-axisencoderX-axisfocusadjustmentcontrolmotorY-axisencoderX-axiscoolercontrolimage processingsystemCTRLInterfacelightningcontrolLANInterfaceThe very first version of the CTcP process exposed theprinting plate in a so-called step-and-repeat mode. The imagewas divided into tiles, which were transferred and processedseparately. A tile consists of up to 1280 by 1024 pixels. Eachtile covers an area of approximately 4 cm². It might beimportant to note that the processing, i.e., exposing theprinting plate, of each tile requires the exact compliance ofpre-defined exposure times. After a tile is finished, theexposure head advances to the next position. During themovement of the exposure head, no information istransferred to the plate, thus increasing the time required toexpose the whole plate. Due to this disadvantage, basysPrintdeveloped a continuous exposing process, called scrollingmode. This process divides an image into adjacent stripes,with each consisting of an entire row of the aforementionedtiles. Furthermore, when processing a stripe, the exposurehead is moving with constant speed.Due to cost reasons, the new system architecture isrealized by several modifications and add-ons of the oldarchitecture. In other words, the current system architectureis the result of a rather evolutionary development process.Such an evolutionary development process is the regularcase, but clearly results in some limitations, which arediscussed in detail in Section IV.B.Fig. 2 presents a simplified schematic of the electricalcontrol system. All grey-shaded elements symbolizecomponents, which are moving over the plate’s surfaceduring the image processing procedure. The two motorsmove the exposure head, also called image processingsystem, to the desired position. The two encoders feed theinformation about the current position back to the triggercard,which is installed in the control PC. The trigger-cardFig. 2: Schematic of a printing plate processing systemB. Problems and GoalsThe current system architecture suffers from the followingfour limitations. First of all, it employs a large number ofelectrical wires for transmitting all the required data, such asimage data, motor positioning information, signals for focusadjustment, as well as various other control signals. Thesewires are embedded in a drag chain (connection betweenfixed body parts and the moving exposure head). From amechanical engineering point of view, the large number ofwires is a severe problem, because the drag chain requires asubstantial amount of the machine’s rare space. The usage ofa second exposure head makes this situation even worse,since it requires an additional set of transfer and controlwires.The second issue is given by the spatial distribution of datasources and sinks. This requires rather long wires and, as aconsequence, significant efforts with respect to signalstability and reliability, connectors, as well as testing andmaintenance.The third topic to address consists of the large variety ofcommunication protocols. Since each connection has slightlydifferent timing parameters, further system extensions arehard to realize, or nearly impossible.The fourth limitation concerns the incorporation of a newprocessing scheme, which is currently under development atbasysPrint. This new scheme tries to avoid mechanicalinterruptions and thus detrimental vibrations by a rathercontinuous exposing process.

Control-PCLAN Interbuswire drag chainmotorX-axisencoderX-axismotorY-axisencoderX-axisfocusadjustmentcontrolimage processingsystemcoolercontrolTriggerlogicCTRLInterfaceNIOS IIMPSoClightningcontrolLANInterfacelocalmemCore 0masterNIOS II (f)peripheralinterfacelocalmemCore 1slaveNIOS II (s)LANinterfacelocalmemCore 2slaveNIOS II (s)avalon switch fabricfocusinterfacemotorinterfacesharedmemorymemoryinterfacetriggerinterfaceFig. 3: Schematic of the modified systemAs a consequence of the issues discussed above,basysPrint, in cooperation with the University of Rostock, isredesigning the entire electrical system 3 . In so doing, itpursues the following goals:1. Significantly reducing the total number of all dataand control wires.2. Aiming at a compact system design, i.e., manycomponents at only a few places, in order to reducethe number of cables, connectors, and potentialsources of failures.3. Concentration of functionalities locally in order toavoid permanent data-transfers and to reduce thenumber of required bus protocols.The following subsection presents a system design thataccounts for the problems and goals discussed above.C. An FPGA-Based Multiprocessor ArchitectureThe new architecture, as shown in Fig. 3, is based on aprogrammable FPGA-device. The main part of the newsystem is a NIOS II-based multiprocessor architecture, which– among other advantages – allows for scalability on demandand loosely coupled system designs. For an in-depthdiscussion of the advantages and disadvantages ofmultiprocessor architectures, the interested reader is referredto [7]. The chosen FPGA contains the multiprocessor systemon a chip (MPSoC) and the trigger-logic, formerly installedin the host-PC, as well. To ensure the system’s proper timingbehavior, i.e., the timely coordination of the motormovements, trigger events, and supply of image data, theMPSoC includes one processor-core only for managing thetime-critical operations. This approach significantly relaxesthe mutual dependencies, and thus limitations, between theexposure system and the host. Since the trigger-logic residesinside the FPGA, it also shortens the communication paths,and thus reducing the requirements and structures for signalpropagation on the fly.3 In other cooperation with the University of Rostock, basysPrint is alsoredesigning other system parts.cooler,control-PCfocus adjustmentcontrol-PCmotorFig. 4: Components of the NIOSII-MPSoCtriggerlogicIn case basysPrint succeeds in the development of newexposing processes, the trigger-logic has to be properlyadapted. The new logic will replace the old trigger-logicalready implemented in the system.This approach, as compared to the existing system, has thefollowing distinct advantage: Any modification of thetrigger-logic does not have any side-effects on the systemboard,as long as the external interfaces of the trigger-logicremain fixed. Any new download of a hardwareconfiguration file into the FPGA affects only the internallogic-elements of the FPGA.The structure of the MPSoC proposed in this paper is anasymmetric shared memory architecture as all cores haveaccess to the external memory device shown in Fig. 4. Thisenables communication between the various processor coresvia globally accessible memory constructs. Since accesses tothe shared memory are realized by simple load and storeoperations, it significantly simplifies communication efforts;i.e., this approach does not require any particular overhead,such as message queues, queue maintenance, or messageprocessing.The utilization of shared memory also allows dynamicchanges in the executed software environment. For example,depending on the currently used printing plate type, core 0can receive parameters or entire software segments byutilizing the LAN-Interface. After sending a notification, adifferent processor, e.g., core 1, can access the very samedata without any further copying or processing operations.In that way, the flexibility for different purposes is increasedas the system can adapt to various other plate types, whichhave varying characteristics and thus require slightmodifications in the exposing process.As can be seen in Fig. 4, all components are coordinated inthe following way: Core 0, labelled “master”, is responsiblefor maintaining status information and managing datatransfer to and from the host-PC. It also controls execution ofthe two slave-cores, 1 and 2. The first slave processes allmovement data generated by the attached trigger-logic. The

second slave-core operates as a peripheral controllersupporting integrated system features, such as the focusadjustment, the cooler, and various other auxiliarycomponents.The MPSoC itself is created mostly by custom elementsfrom ALTERA’s system libraries. Only a few systemspecificinterfaces for focus control, motor-connection, andtrigger-logic have to be designed by the developer. But eventhis work is supported by the ALTERA tools. Therefore, thedesign efforts for building interfaces are held at its minimum.The system shown in Fig. 4 represents an expandableplatform. Whenever the addition of further functionalitiesexceeds the current computational capabilities, the developermay solve this problem by adding another CPU. This way,the system performance can be adapted to any requirements.Especially time-restricted operations profit from thisapproach.A. MethodsV. IMPLEMENTATIONThe development discussed in this paper concentrates onthe ALTERA NIOS development kit Cyclone Edition [11].It features a Cyclone FPGA EP1C20 with approximately20,000 programmable logic elements. The developmentboard is equipped with a wide range of useful peripherals,such as 16MB SDRAM, 8MB flash-memory, an onboardEthernet device, and several I/O-interfaces.The Cyclone FPGA offers 300 configurable user I/Opins,which accomplishes the application at hand. The pricefor such a device starts at approximately 100 US$ per devicefor a 24-device tray. Depending on the ordered volume, theprice may be as low as 25 US$ per device.As mentioned above, this research resorts on theconfigurable NIOS II CPU. “Configurable” in the context ofthe NIOS II CPU means that features, such as interfaces, onchip memories, watchdogs, and timers, can be freely addedor removed. It is furthermore possible to augment the CPU’sarithmetic logical unit (ALU) with dedicated hardware forspecial purposes, such as video- or audio-processing. Thisadditional ALU-hardware is called “custom instruction”.From the software-perspective, custom instructions appear asmachine-generated assembly macros or C functions [3]. Thisapproach yields significant performance improvements, sincesoftware functionalities can be transferred to physicalhardware. A minimal configuration of a NIOS II processorconsumes between 700 and 1800 logic elements and runs at aclock speed of up to 200 MHz.ALTERA provides special hardware mutexes to simplifyaccesses to components shared by more than one processor.Such mutex performs an atomic test-and-set operation, inorder to avoid concurrent memory access by two or moreprocessors.The creation of the processor system has been done withthe help of ALTERA’s SOPC-Builder. It provides agraphical user interface, which instantiates system featuresand handles both address and interrupt management. Formore detailed information about ALTERAs SOPC-Builder,the interested reader is referred to the literature [6].B. First Results and Critical DiscussionThe first proof-of-concept implementation in the ALERACyclone FPGA takes about 9,000 logic elements, which isapproximately 45% of the overall logic-resources. The clockgeneration is realized by the two onboard phase locked loops(PLL). In order to keep compilation time at a minimum, thecore speed was set to 50 MHz and no optimizationconstraints were established during the development stage.When switching to the final release, the system will beoptimized in order to gain higher clock rates, with anexpectation of approximately 80 MHz.The current development version already achieves thedesired goals mentioned in Section IV; the aggregation of thetrigger-logic and processing elements into an embeddedsystem allows for shorter communication paths, reduced thenumber of separated system units, and made many of thewires connected to the host-PC dispensable. On a short term,this approach yields cost and maintenance improvements. Ona long term, this modifiable adaptable platform is open tofurther improvements and also provides enough resources foradditional features.While fulfilling the given requirements, the prototypicalimplementation points to some issues, which are subject tocurrent as well as future research. First of all, the centralsystem bus, which handles all the interprocessorcommunications, might turn into a bottleneck. This potentialproblem should be appropriately addressed by both hardwareand software designs. Current research is devoted to thedevelopment of simple and adaptable solutions [8, 9]. Theprototype described in this paper uses the Avalon switchfabric for interprocessor communication purposes. Inaddition, the Avalon switch fabric improves the performanceby its ability to support multiple bus masters. In theapplication at hand, it is possible to map software tasks ontoseparate CPUs, i.e., rather distributed than parallelprocessing, interprocessor communication is not a severeissue; other application profiles might require differentcommunication mechanisms, such as message passing [7].VI. FUTURE WORKThe current implementation is a prototype that represents aproof-of-concept. Future research will be devoted to thedevelopment of a complete platform, which will be convertedto a production system by basysPrint. The remainder of thissection sketches the most important hardware and softwareissues.On the hardware side, the current VHDL code of theexisting multiprocessor platform is to be enhanced by all therequired interfaces. This includes a LAN-connection for

transferring image data, interfacing the peripherals, such ascooler, motors, and other auxiliary hardware, and connectinga CAN bus. Another major part consists of the integration ofthe existing trigger-logic functionality.On the software side, the next steps are as follows: First ofall, the existing software functionalities have to be ported tothe new system. Then, the distribution of the data andcommunication objects, i.e., the memory map, should beoptimized with respect to the system’s runtime behavior.After the completion of the steps mentioned above, a finalfield study has to prove both sufficient processing speed andfulfilment of the required timing behavior.VII. CONCLUSIONThis paper has presented the benefits of utilizing an FPGAto implement a multiprocessor platform for an industrialapplication in the field of offset printing. This paper hasfurthermore shown that FPGA-based solutions enable theusage of soft-core processors, which leads to flexible,scalable, and easy-to-maintain systems.For the following reasons, the approach presented heremight be of particular interests for industrial applications: Itenables the efficient participation of future trends, such asdynamically reconfigurable hardware [10]; the support bypowerful tools, the usage of an abstract hardware descriptionlanguage, and the option of employing IP-cores all result insignificant time and money savings; since the particularsystem is not bound to a particular FPGA, i.e., the hardwarecan be ported to a different FPGA by a simple recompilation,it can be easily scaled if demands desire so.Another point to consider, when working with FPGAs, isthat hardware description, i.e., the VHDL code, remains atthe development side and can furthermore not be recoveredby third parties by reading the configuration file. That is, allsystem-related information can be kept confidential. Thisalso reduces time and money costs during communication tothird-party companies.All the advantages described above are a strong argumentfor using FPGAs in industrial applications. Another equallyimportant argument is that all the provided tools allow almostany developer to utilize FPGAs at very low personal andmonetary costs.VIII. ACKNOWLEDGMENTSThe authors gratefully thank Dr. Horst Steppat, managingdirector at basysPrint, and John Hedde, director of researchand development at basysPrint, for providing the existingtechnology and the excellent cooperation. In addition theauthors sincerely thank Jens Hildebrandt, former member ofthis research and now with Siemens VDO Automotive AG.This research was supported in part by the German federalministry of education and research, grant number 03i4919B.IX. REFERENCES[1] Chris Wright and Mike Arens, “FPGA-based Systemon-ModuleApproach Cuts Time to Market, AvoidsObsolescence”, FPGA and Programmable LogicJournal, Volume VI, No. 6, Feb. 2005[2] Salil Raje, “Catching the FPGA Productivity Wave”,Electronic Design, Oct. 2004, Online ID 8931[3] Altera Corp., NIOS II Processor Reference Handbook,Altera Document NII5V1-1.2, Altera Corp., San Jose,CA, Jan. 2005[4] Gaisler Resarch, LEON2 Processor User’s Manual –XST Edition, Gaisler Research AB, Goteborg, Sweden,Jan. 2005[5] XILINX Inc., MicroBlaze Processor Reference Guide,XILINX Document UG081 (v5.0), XILINX Inc., SanJose, CA, Jan. 2005[6] Altera Corp., Quartus II Handbook Volume 4 - SOPC-Builder, Altera Document QII5V4-1.0, Altera Corp.,San Jose, CA, Feb. 2005[7] David. E. Culler and Jaswinder Pal Singh, ParallelComputer Architecture – A Hardware/SoftwareApproach, Morgan Kaufmann Publishers, Inc., SanFrancisco, California, 1999[8] José Carlos Palma, Aline Vieira del Melo, FernandoGehm Moraes, Ney Calanzans, “Core CommunicationInterface for FPGAs”, 15 th Symposium on IntegratedCircuits and System Design, Porto Allegre, Brazil, 2002[9] Ross B. Ortega and Gaetano Borriello, “CommunicationSynthesis for Distributed Embedded Systems,” inProceedings of the 1998 IEEE/ACM internationalconference on Computer-aided design, pp. 437-444,1998[10] Reiner Hartenstein, “The Microprocessor is no moreGeneral Purpose: why Future Reconfigurable Platformswill win,” in Proceedings of the Second Annual IEEEInternational Conference on Innovative Systems inSilicon, 1997[11] Altera Corp., Nios Development Board ReferenceManual, Cyclone Edition, Altera Document MNL-N2DEVLBDCYC-1.1, Altera Corp., San Jose, CA,[12] basysPrint, UV-Setters Series 7, basysPrint Ltd., 2004