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An ARM Backend for PyPyls Tracing JIT - STUPS Group

An ARM Backend for PyPyls Tracing JIT - STUPS Group

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6 2 <strong>ARM</strong>As <strong>ARM</strong> states [<strong>ARM</strong>10] the architecture spots a set of typical RISC characteristics, witha few additional properties only provided by <strong>ARM</strong> processors. The <strong>ARM</strong> architectureprovides:• a large set of multi-purpose registers• data processing operations that work on register contents and not directly on datastored in memory• a simple and direct addressing mode based only on register contents and constantoffsetsAmong the special features only found on <strong>ARM</strong> are:• the combination of shift operations with logical and arithmetic operations, meaningthat it is possible to apply a shift to arguments of operations be<strong>for</strong>e they areevaluated• auto-decrement and increment addressing modes• instructions to load and store multiple register values at once, to improve datathroughput• conditional execution of most of the instructions, to avoid jump operations andimprove per<strong>for</strong>mance and cache behaviour2.2.1 <strong>ARM</strong>/THUMBThe latest version of the <strong>ARM</strong> architecture is version 7 which is usually referred to as<strong>ARM</strong>v7. This architecture defines two main instruction sets and corresponding executionmodes.Chronologically the first was the <strong>ARM</strong> instruction set, introduced in 1983 by AcornsComputers. The <strong>ARM</strong> instruction set is a fixed width 32-bit instructions set, providingthe best per<strong>for</strong>mance and the biggest flexibility in the interaction with the processor.The second was the Thumb instruction set, first introduced with some cores of the <strong>ARM</strong>v4processor family around 1993, it was a fixed width 16 bit instruction set designed to improvethe code density at the cost of execution speed. The speed penalty is present becauseThumb instructions are translated at runtime to the corresponding <strong>ARM</strong> instructions.[<strong>ARM</strong>95]The Thumb instruction set evolved into Thumb-2 which is a variable width instructionset trying to combine the code density of Thumb with per<strong>for</strong>mance comparable to the<strong>ARM</strong> instruction set.There are also additional instruction sets and execution modes targeting virtual machinessuch as Jazelle which specifically targets Java bytecode. Jazelle has been deprecated infavor of ThumbEE which extends the Thumb instruction set with null pointer checks andsome other additional features.

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