CMOS Logic Data - Italy

DL131/DRev. 4, Mar-2000CMOS Logic DataON Semiconductor

CMOS Logic DataThis book presents technical data for the broad line of CMOS logic integrated circuits and demonstrates ON Semiconductor’scontinued commitment to Metal–Gate CMOS. Complete specifications are provided in the form of data sheets.In addition, a Product Selector Guide and a Handling and Design Guidelines chapter have been included to familiarizethe user with these circuits.DL131/DRev. 4, March–2000© SCILLC, 2000Previous Edition © 1991“All Rights Reserved’’

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changeswithout further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particularpurpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/orspecifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must bevalidated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicationsintended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or deathmay occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLCand its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney feesarising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges thatSCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.PUBLICATION ORDERING INFORMATIONNORTH AMERICA Literature Fulfillment:Literature Distribution Center for ON SemiconductorP.O. Box 5163, Denver, Colorado 80217 USAPhone: 303–675–2175 or 800–344–3860 Toll Free USA/CanadaFax: 303–675–2176 or 800–344–3867 Toll Free USA/CanadaEmail: ONlit@hibbertco.comFax Response Line: 303–675–2167 or 800–344–3810 Toll Free USA/CanadaN. American Technical Support: 800–282–9855 Toll Free USA/CanadaEUROPE: LDC for ON Semiconductor – European SupportGerman Phone: (+1) 303–308–7140 (M–F 1:00pm to 5:00pm Munich Time)Email: ONlit–german@hibbertco.comFrench Phone: (+1) 303–308–7141 (M–F 1:00pm to 5:00pm Toulouse Time)Email: ONlit–french@hibbertco.comEnglish Phone: (+1) 303–308–7142 (M–F 12:00pm to 5:00pm UK Time)Email: ONlit@hibbertco.comEUROPEAN TOLL–FREE ACCESS*: 00–800–4422–3781*Available from Germany, France, Italy, England, IrelandCENTRAL/SOUTH AMERICA:Spanish Phone: 303–308–7143 (Mon–Fri 8:00am to 5:00pm MST)Email: ONlit–spanish@hibbertco.comASIA/PACIFIC: LDC for ON Semiconductor – Asia SupportPhone: 303–675–2121 (Tue–Fri 9:00am to 1:00pm, Hong Kong Time)Toll Free from Hong Kong & Singapore:001–800–4422–3781Email: ONlit–asia@hibbertco.comJAPAN: ON Semiconductor, Japan Customer Focus Center4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–8549Phone: 81–3–5740–2745Email: r14525@onsemi.comON Semiconductor Website: http://onsemi.comFor additional information, please contact your localSales Representative.http://onsemi.com2

Table of ContentsPageChapter 1 — Master Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5Alphanumeric Listing of All CMOS Part Numbers with Function and Page Number Information ProvidedChapter 2 — Product Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9CMOS Selection Guide Sorted by Product FunctionChapter 3 — Reliability Audit Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Explanation of On Semiconductor’s Outgoing Product Performance Audit ProgramChapter 4 — B and UB Series Family Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Explanation of Standardized Specifications for the Product FamilyChapter 5 — CMOS Handling and Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Handling Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24Input Protection Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25Propagation Delay and Rise Time versus Series Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29CMOS Latch Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29Chapter 6 — CMOS Logic Data Sheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31See the Master Index for Page Numbering InformationChapter 7 — CMOS Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432Basic Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432Thermal Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434Air Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434Optimizing the Long Term Reliability of Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435Chapter 8 — Equivalent Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437Chapter 9 — Packaging Information Including Surface Mounts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441ON Semiconductor Major Worldwide Sales Offices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447ON Semiconductor Standard Document Type Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448http://onsemi.com3

ALExIS, Bullet–Proof, CHIPSCRETES, Designer’s, DUOWATT, E–FET, EASY SWITCHER, ECL300, ECLinPS, ECLinPS Lite,ECLinPS Plus, ELite, EpiBase, Epicap, EZFET, FULLPAK, GEMFET, ICePAK, L 2 TMOS, MCCS, MDTL, MECL, MEGAHERTZ,MHTL, MiniMOS, MiniMOSORB, Mosorb, MRTL, MTTL, Multi–Pak, ON–Demand, PowerBase, POWERTAP, Quake,SCANSWITCH, SENSEFET, SLEEPMODE, SMALLBLOCK, SMARTDISCRETES, SMARTswitch, SUPERBRIDGES,SuperLock, Surmetic, SWITCHMODE, Thermopad, Thermowatt, TMOS, TMOS & Design Device, TMOS Stylized, Unibloc,UNIT/PAK, Uniwatt, WaveFET, Z–Switch and ZIP R TRIM are trademarks of Semiconductor Components Industries, LLC(SCILLC).HDTMOS and HVTMOS are registered trademarks of Semiconductor Components Industries, LLC (SCILLC).All other brand names and product names appearing in this publication are registered trademarks or trademarks of theirrespective holders.http://onsemi.com4

http://onsemi.com5CHAPTER 1Master Index

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MASTER INDEXDevice Function PageMC14001B Quad 2–Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32MC14001UB Quad 2–Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40MC14007UB Dual Complementary Pair Plus Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45MC14008B 4–Bit Full Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50MC14011B Quad 2–Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32MC14011UB Quad 2–Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40MC14013B Dual D Flip–Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56MC14014B 8–Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61MC14015B Dual 4–Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66MC14016B Quad Analog Switch/Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73MC14017B Decade Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81MC14018B Presettable Divide–by–N Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87MC14020B 14–Bit Binary Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92MC14021B 8–Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61MC14022B Octal Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97MC14023B Triple 3–Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32MC14024B 7–Stage Ripple Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103MC14025B Triple 3–Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32MC14027B Dual J–K Flip–Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109MC14028B BCD–to–Decimal/Binary–to–Octal Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114MC14029B Presettable Binary/BCD Up/Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120MC14040B 12–Bit Binary Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126MC14042B Quad Transparent Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131MC14043B Quad NOR R–S Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136MC14044B Quad NAND R–S Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136MC14046B Phase–Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141MC14049B Hex Inverting Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146MC14049UB Hex Inverting Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151MC14050B Hex Noninverting Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146MC14051B 8–Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155MC14052B Dual 4–Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155MC14053B Triple 2–Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155MC14060B 14–Bit Binary Counter and Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164MC14066B Quad Analog Switch/Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169MC14067B 16–Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176MC14069UB Hex Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185MC14070B Quad Exclusive OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188MC14071B Quad 2–Input OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32MC14073B Triple 3–Input AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32MC14076B Quad D–Type Register with Tri–State Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191MC14077B Quad Exclusive NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188http://onsemi.com7

Device Function PageMC14081B Quad 2–Input AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32MC14082B Dual 4–Input AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32MC14093B Quad 2–Input NAND Schmitt Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196MC14094B 8–Stage Shift/Store Register with Tri–State Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201MC14099B 8–Bit Addressable Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207MC14106B Hex Schmitt Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212MC14174B Hex D Flip–Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218MC14175B Quad D Flip–Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223MC14490 Hex Contact Bounce Eliminator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228MC14503B Hex 3–State Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236MC14504B TTL or CMOS to CMOS Hex Level Shifter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241MC14511B BCD–to–7–Segment Latch/Decoder/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246MC14512B 8–Channel Data Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253MC14513B BCD–to–7–Segment Latch/Decoder/Driver with Ripple Blanking . . . . . . . . . . . . . . . . . 259MC14514B 4–Bit Transparent Latch/4–to–16 Line Decoder (High) . . . . . . . . . . . . . . . . . . . . . . . . . . 268MC14515B 4–Bit Transparent Latch/4–to–16 Line Decoder (Low) . . . . . . . . . . . . . . . . . . . . . . . . . . 268MC14516B Presettable Binary Up/Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275MC14517B Dual 64–Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285MC14518B Dual BCD Up Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290MC14520B Dual Binary Up Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290MC14521B 24–Stage Frequency Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296MC14526B Presettable 4–Bit Binary Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304MC14528B Dual Monostable Multivibrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313MC14532B 8–Bit Priority Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320MC14536B Programmable Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327MC14538B Dual Precision Monostable Multivibrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340MC14541B Programmable Oscillator/Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349MC14543B BCD–to–7–Segment Latch/Decoder/Driver for Liquid Crystals . . . . . . . . . . . . . . . . . . . 354MC14549B Successive Approximation Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360MC14551B Quad 2–Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368MC14553B 3–Digit BCD Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376MC14555B Dual Binary to 1–of–4 Decoder (Active High Outputs) . . . . . . . . . . . . . . . . . . . . . . . . . . 383MC14556B Dual Binary to 1–of–4 Decoder (Active Low Outputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . 383MC14557B 1–to–64 Bit Variable Length Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387MC14559B Successive Approximation Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360MC14562B 128–Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393MC14569B Programmable Dual 4–Bit Binary/BCD Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . 399MC14572UB Hex Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411MC14584B Hex Schmitt Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415MC14585B 4–Bit Magnitude Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420MC14598B 8–Bit Bus–Compatible Addressable Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425http://onsemi.com8

http://onsemi.com9CHAPTER 2Product Selection Guide

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CMOS Selection Guide by FunctionDevice Function PageNAND GatesMC14011B Quad 2–Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32MC14011UB Quad 2–Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40MC14093B Quad 2–Input NAND Schmitt Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196MC14023B Triple 3–Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32NOR GatesMC14001B Quad 2–Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32MC14001UB Quad 2–Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40MC14025B Triple 3–Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32AND GatesMC14081B Quad 2–Input AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32MC14073B Triple 3–Input AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32MC14082B Dual 4–Input AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Complex GatesMC14070B Quad Exclusive OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188MC14077B Quad Exclusive NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188MC14572UB Hex Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411Inverters/Buffers/Level TranslatorMC14007UB Dual Complementary Pair Plus Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45MC14049B Hex Inverting Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146MC14049UB Hex Inverting Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151MC14050B Hex Noninverting Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146MC14069UB Hex Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185MC14503B Hex 3–State Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236MC14504B TTL or CMOS to CMOS Hex Level Shifter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241MC14584B Hex Schmitt Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415Decoders/EncodersMC14028B BCD–to–Decimal/Binary–to–Octal Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114MC14511B BCD–to–7–Segment Latch/Decoder/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246MC14513B BCD–to–7–Segment Latch/Decoder/Driver with Ripple Blanking . . . . . . . . . . . . . . . . . 259MC14543B BCD–to–7–Segment Latch/Decoder/Driver for Liquid Crystals . . . . . . . . . . . . . . . . . . . 354MC14514B 4–Bit Transparent Latch/4–to–16 Line Decoder (High) . . . . . . . . . . . . . . . . . . . . . . . . . . 268MC14515B 4–Bit Transparent Latch/4–to–16 Line Decoder (Low) . . . . . . . . . . . . . . . . . . . . . . . . . . 268MC14532B 8–Bit Priority Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320MC14555B Dual Binary to 1–of–4 Decoder (Active High Outputs) . . . . . . . . . . . . . . . . . . . . . . . . . . 383MC14556B Dual Binary to 1–of–4 Decoder (Active Low Outputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . 383Multiplexers/Demultiplexers/Bilateral SwitchesMC14016B Quad Analog Switch/Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73MC14066B Quad Analog Switch/Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169MC14551B Quad 2–Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368MC14053B Triple 2–Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155MC14052B Dual 4–Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155MC14067B 16–Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176MC14051B 8–Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155MC14512B 8–Channel Data Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253Schmitt TriggersMC14093B Quad 2–Input NAND Schmitt Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196MC14106B Hex Schmitt Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212MC14584B Hex Schmitt Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415http://onsemi.com11

Device Function PageOR GatesMC14071B Quad 2–Input OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Flip–Flops/LatchesMC14042B Quad Transparent Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131MC14043B Quad NOR R–S Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136MC14044B Quad NAND R–S Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136MC14076B Quad D–Type Register with Tri–State Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191MC14175B Quad D Flip–Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223MC14013B Dual D Flip–Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56MC14027B Dual J–K Flip–Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109MC14174B Hex D Flip–Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218MC14099B 8–Bit Addressable Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207MC14598B 8–Bit Bus–Compatible Addressable Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425Shift RegistersMC14015B Dual 4–Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66MC14517B Dual 64–Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285MC14562B 128–Bit Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393MC14557B 1–to–64 Bit Variable Length Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387MC14014B 8–Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61MC14021B 8–Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61MC14094B 8–Stage Shift/Store Register with Tri–State Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201MC14549B Successive Approximation Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360MC14559B Successive Approximation Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360CountersMC14017B Decade Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81MC14018B Presettable Divide–by–N Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87MC14020B 14–Bit Binary Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92MC14022B Octal Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97MC14024B 7–Stage Ripple Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103MC14029B Presettable Binary/BCD Up/Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120MC14040B 12–Bit Binary Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126MC14060B 14–Bit Binary Counter and Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164MC14516B Presettable Binary Up/Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275MC14518B Dual BCD Up Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290MC14520B Dual Binary Up Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290MC14526B Presettable 4–Bit Binary Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304MC14553B 3–Digit BCD Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376MC14569B Programmable Dual 4–Bit Binary/BCD Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399Oscillators/TimersMC14521B 24–Stage Frequency Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296MC14536B Programmable Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327MC14541B Programmable Oscillator/Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349MultivibratorsMC14528B Dual Monostable Multivibrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313MC14538B Dual Precision Monostable Multivibrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340Adders/ComparatorsMC14008B 4–Bit Full Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50MC14585B 4–Bit Magnitude Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420Other Complex FunctionsMC14046B Phase–Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141MC14490 Hex Contact Bounce Eliminator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228http://onsemi.com12

http://onsemi.com13CHAPTER 3Reliability Audit Program

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Reliability Audit ProgramFor Logic Integrated Circuits1.0 INTRODUCTIONThe Reliability Audit Program developed in March 1977is the ON Semiconductor internal reliability audit which isdesigned to assess outgoing product performance underaccelerated stress conditions. Logic Reliability Engineeringhas overall responsibility for RAP, including updating itsrequirements, interpreting its results, administration atoffshore locations, and monthly reporting of results. Thesereports are available at all sales offices. Also available is the“Reliability and Quality Handbook” which contains data forall ON Semiconductor devices (HBD851/D).RAP is a system of environmental and electrical testsperformed periodically on randomly selected samples ofstandard products. Each sample receives the tests specifiedin section 2.0. Frequency of testing is specified per internaldocument 12MRM15301A.http://onsemi.com15

2.0 RAP TEST FLOWPull 500* piece sample from lot following Group Aacceptance.45* 340 100PTHB48 HRSPTH***48 HRSINTERIMELECTRICALINITIALSEAL**TEMP CYCLES40 CYCLESINTERIMTESTADD 460 CYCLESINTERIMTESTOP LIFE40 HOURSINTERIMELECTRICALOP LIFE210 HRS (ADDITIONAL)FINALINTERIM #ELECTRICALFINALELECTRICAL(48 HRS)PTH48 HRS(ADDITIONAL)FINALELECTRICAL(96 HRS)ADD 500 CYCLESFINALINTERIM*TESTTEMP CYCLES #1000 CYCLES(ADDITIONAL)FINALELECTRICAL& SEAL**(2000 CYCLES)OP LIFE #750 HRS(ADDITIONAL)FINAL #ELECTRICAL(1000 HRS)SCRAPSCRAPSCRAP#One sample per month for FAST, LS, 10H, 10K, MG CMOS, and HSL CMOS.* PTHB or PTH not required for hermetic products: reduce total sample size to 450 pcs.** Seal (Fine & Gross Leak) required only for hermetic products.*** PTH to be used when sockets for PTHB are not available.3.0 TEST CONDITIONS AND COMMENTSPTHB — 15 psig/121°C/100% RH at rated V CC or V EE —to be performed on plastic encapsulated devicesonly.TEMP CYCLING — MIL–STD–883, Method 1010,Condition C, – 65°C/+ 150°C.OP LIFE — MIL–STD–883, Method 1005, Condition C(Power plus Reverse Bias), T A = 145°C.NOTES:1. All standard 25°C dc and functional parameters will bemeasured Go/No/Go at each readout.2. Any indicated failure is first verified and then submittedto the Product Analysis Lab for detailed analysis.3. Sampling to include all package types routinely.4. Device types sampled will be by generic type within eachlogic I/C product family (CMOS, TTL, etc.) and willinclude all assembly locations (Korea, Philippines,Malaysia, etc.).5. 16 hrs. PTHB is equivalent to approximately 800 hoursof 85°C/85% RH THB for V CC 15 V.6. Only moisture related failures (like corrosion) are criteriafor failure on PTHB test.7. Special device specifications (48A’s) for logic productswill reference 12MRM15301A as source of generic datafor any customer required monthly audit reports.http://onsemi.com16

CHAPTER 4B and UB Series Family Datahttp://onsemi.com17

MAXIMUM RATINGS* (Voltages Referenced to V SS )ParametersValueÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbolÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎV DD DC Supply VoltageÎÎÎÎÎÎVÎÎÎÎÎÎÎÎÎÎÎÎÎÎoutÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎV in , V Input or Output Voltage (DC or Transient)VI in , l Input or Output Current (DC or Transient), per Pin± 10mAP DPower Dissipation, per Package†Unit– 0.5 to +ÎÎÎ18.0– 0.5 to V DD +ÎÎÎ0.5ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎT ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎstg Storage Temperature– 65ÎÎÎto + 150T LLead Temperature (8–Second Soldering)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ500mWCÎÎÎ260 C* Maximum Ratings are those values values beyond which damage to the device may occur.†Temperature Derating:Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 CCeramic “L” Packages: – 12 mW/ C From 100 C To 125 C5.0 VV IL = 1.5 V V out = 0.5 V V outFIRST STAGE(NONINVERTING BUFFER)V IL = 1.5 VSECOND STAGE(NONINVERTING BUFFER)Figure 1.ELECTRICAL CHARACTERISTICSTable 1. EIA/JEDEC Format for CMOS Industry B and UB Series SpecificationsÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ+ 25 C ÎÎÎÎÎÎTempV DDÎÎÎÎÎÎÎÎParameterConditions Min MaxÎÎÎÎÎÎÎÎÎMinMax ÎÎÎÎÎÎMin Max UnitsRangeÎÎÎÎÎÎ(Vdc)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎI DD QuiescentÎÎÎ MilÎÎÎ5 ÎÎÎÎÎÎÎÎÎÎÎÎ0.25ÎÎÎ ÎÎÎ0.25 ÎÎÎÎÎÎ7.5ÎÎεAdcDeviceÎÎÎ ÎÎÎCurrentÎÎÎÎÎÎ10ÎÎÎÎÎÎÎÎÎV in = V SS or V DD ÎÎÎ0.5ÎÎÎ ÎÎÎ0.5ÎÎÎ ÎÎÎ15ÎÎÎÎÎÎÎ15GATES Comm 5 All valid input10 combinations15ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎMil51015ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎVÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎIN = V SS or V DDBUFFERS, Comm ÎÎÎ 5 All valid inputFLIP–FLOPS 10 combinations15ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎMil5ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ10ÎÎÎÎÎÎVÎÎÎÎIN = V SS or V DD 10ÎÎÎ ÎÎÎ ÎÎÎ10ÎÎÎ ÎÎÎ300ÎÎÎÎÎÎÎ15MSI Comm 5 All valid input10 combinations15ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎV OLLow–LevelOutput VoltageAll51015V IN = V SS or V DD|I O | < 1 µAÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎV OHHigh–LevelOutput VoltageAll51015V IN = V SS or V DD|I O | < 1 µAÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ4.959.9514.95T LOW *1.01.02.04.01.02.04.048165202040800.050.050.054.959.9514.95Limits1.01.02.04.01.02.04.04.08.016.05202040800.050.050.054.959.9514.95T HIGH *307.51530306012030601201506001503006000.050.050.05µAdcµAdcµAdcµAdcµAdcVdcVdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎhttp://onsemi.com20

Table 1. EIA/JEDEC Format for CMOS Industry B and UB Series Specifications (continued)ELECTRICAL CHARACTERISTICSÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ+ 25 CÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎV ILParameterInputLow Voltage #B TypesÎÎÎ ÎÎÎÎÎÎ Temp VDDV T LOW *Min MaxÎÎÎ(Vdc)RangeConditionsAll 5 V O = 0.5V or 4.5V1.510 V O = 1.0V or 9.0V3.015 V O = 1.5V or 13.5V4.0ÎÎÎÎMinÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎV ILInputLow Voltage #UB TypesAll51015ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎV IHInputHigh Voltage #B TypesAll51015|I O | < 1 µAV O = 0.5V or 4.5VV O = 1.0V or 9.0VV O = 1.5V or 13.5V|I O | < 1 µAV O = 0.5V or 4.5VV O = 1.0V or 9.0VV O = 1.5V or 13.5V|I O | < 1 µALimitsT HIGH *ÎÎÎMax ÎÎÎMin ÎÎÎUnits1.51.5 Vdc3.03.04.04.0ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎV IHInputHigh Voltage#UB TypesAll51015ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎI OLOutput Low(Sink) CurrentMil510ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ15V O = 0.5V or 4.5VV O = 1.0V or 9.0VV O = 1.5V or 13.5V|I O | < 1 µAV O = 0.4V,V IN = 0 or 5VV O = 0.5V,V IN = 0 or 10VV O = 1.5V,V IN = 0 or 15VÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎCom 5 V O = 0.4V,V ÎÎÎIN = 0 or 5V10 V O = 0.5V,V IN = 0 or 10VV O = 1.5V,ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ15ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎI OHOutput High(Source) CurrentMil5ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ10V IN = 0 or 15VV O = 4.6V,V IN = 0 or 5VV O = 9.5V,V IN = 0 or 10VV O = 13.5V,ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ15 V IN = 0 or 15VCom ÎÎÎ V O = 4.6V,5 V IN = 0 or 5VV O = 9.5V,10 V IN = 0 or 10VV O = 13.5V15 V IN = 0 or 15VÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎI INInput CurrentMilComm1515V IN = 0 or 15VV IN = 0 or 15VÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎI oz3–State OutputMil 15 V IN = 0 or 15VComm V IN = 0 or 15VÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎLeakage CurrentÎÎÎ15 ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎεAdcÎÎÎÎÎÎCÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎIN Input Capacitance All —ÎÎÎÎÎÎÎÎAnyÎÎÎ ÎÎÎ ÎÎÎInputpFÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎper unit load3.57.011.04.08.012.50.641.64.20.521.33.6– 0.25– 0.62– 1.8– 0.2– 0.5– 1.41.02.02.5± 0.1± 0.33.57.011.04.08.012.50.511.33.40.441.13.0– 0.2– 0.5– 1.5– 0.16*T LOW = – 55 C for Military temperature range device, – 40°C for Commercial temperature range device.T HIGH = + 125 C for Military temperature range device, + 85 C for Commercial temperature range device.#Applies for Worst Case input combinations.– 0.4– 1.21.02.02.5± 0.1± 0.33.57.011.04.08.012.50.360.92.40.360.92.4– 0.14– 0.35– 1.1– 0.12– 0.3– 1.01.02.02.5± 1.0± 1.0VdcVdcmAdcmAdcmAdcmAdcµAdcµAdc± 0.4± 0.4± 12 µAdc± 1.6 ± 1.6 ± 12 ÎÎÎÎÎÎÎÎÎ7.5 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎhttp://onsemi.com21

Table 2. ON Semiconductor Format for CMOS Industry B and UB Series SpecificationsELECTRICAL CHARACTERISTICSÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎV – 55 C 25 C + 125 DDCÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCharacteristicÎÎÎVdcÎÎÎÎMin MaxÎÎÎÎÎÎÎÎÎÎÎUnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Voltage“0” LevelÎÎÎV OLÎÎÎÎ5.0ÎÎΗÎÎÎ0.05ÎÎΗÎÎÎÎ0.05ÎÎΗÎÎÎ0.05ÎÎÎVdcV in = V DD or 0V in = 0 or V DD“1” LevelSymbolÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎOHÎÎÎÎMin Max10 — 0.05 —15 — 0.05 —V 5.0 4.95 — 4.9510 9.95 — 9.9515 14.95 — 14.95ÎÎÎMinÎÎÎMaxÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput Voltage B Types“0” LevelÎÎÎV ILÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVdc(V O = 4.5 or 0.5 Vdc)(V O = 9.0 or 1.0 Vdc)(V O = 13.5 or 1.5 Vdc)5.01015ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΓ1” LevelÎÎÎV IHÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVdc(V O = 0.5 or 4.5 Vdc)(V O = 1.0 or 9.0 Vdc)(V O = 1.5 or 13.5 Vdc)5.01015ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput Voltage UB Types“0” LevelÎÎÎV ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎIL Vdc(V O = 4.5 or 0.5 Vdc)(V O = 9.0 or 1.0 Vdc)(V O = 13.5 or 1.5 Vdc)5.01015ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΓ1” ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎLevelÎÎÎÎÎÎÎÎÎÎ ÎÎÎV ÎÎÎIH Vdc(VÎÎÎÎÎÎÎÎÎÎÎÎÎO =ÎÎÎ0.5ÎÎÎorÎÎÎÎ4.5ÎÎÎVdc)ÎÎÎ5.0ÎÎÎÎÎÎ4.0ÎÎÎÎÎÎΗ 4.0 — 4.0 —(V O = 1.0 or 9.0 Vdc)(V O = 1.5 or 13.5 Vdc)1015ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎI OHÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Drive Current B Gates(V OH = 2.5 Vdc) Source(V OH = 4.6 Vdc)(V OH = 9.5 Vdc)(V OH = 13.5 Vdc)5.05.01015ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(VÎÎÎÎÎÎÎOL =ÎÎÎ0.4 Vdc)ÎÎÎSinkÎÎÎÎI OL 5.0ÎÎÎ0.64 —ÎÎÎ0.51ÎÎΗ 0.36 —ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V OL = 0.5 Vdc)(V OL = 1.5 Vdc)1015———3.57.011———8.012.5– 3.0– 0.64– 1.6– 4.21.53.04.0———1.02.02.5—————————3.57.011———8.012.5– 2.4– 0.51– 1.3– 3.40.050.05———1.53.04.0———1.02.02.5————————4.959.9514.95———3.57.011———8.012.5– 1.7– 0.36– 0.9– 2.4Output DriveÎÎÎCurrent ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎUBÎÎÎÎÎÎGatesÎÎÎ ÎÎÎI OH(V ÎÎÎÎÎÎÎÎÎÎÎÎÎOH = ÎÎÎ2.5 ÎÎÎVdc) SourceÎÎÎÎ5.0ÎÎΖ 1.2ÎÎΗÎÎΖ ÎÎÎ1.0 —ÎÎΖ 0.7 —ÎÎÎÎ(V OH = 4.6 Vdc)(V OH = 9.5 Vdc)(V OH = 13.5 Vdc)5.01015ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎI OLÎÎÎÎ 5.0 ÎÎÎ 0.64 ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ(V OL = 0.4 Vdc) Sink(V OL = 0.5 Vdc)(V OL = 1.5 Vdc)10151.64.2– 0.25– 0.62– 1.8—————1.33.4– 0.2– 0.5– 1.5—————0.92.4– 0.14– 0.35– 1.1ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎI OH ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Drive Current Other Devices(V OH = 4.6 Vdc) Source(V OH = 9.5 Vdc)(V OH = 13.5 Vdc)5.01015ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V OL = 0.4 Vdc)ÎÎÎSink I OL ÎÎÎ5.0ÎÎÎ0.64ÎÎΗÎÎÎÎ0.51ÎÎΗÎÎÎ0.36ÎÎΗÎÎÎÎ(V OL = 0.5 Vdc)(V OL = 1.5 Vdc)10151.64.2– 0.64– 1.6– 4.2——————0.511.33.4– 0.51– 1.3– 3.4——————0.360.92.4– 0.36– 0.9– 2.4ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput CurrentÎÎÎ I in ÎÎÎ15 — ÎÎÎ — ÎÎÎÎ — ÎÎεAdcÎÎÎÎInput Capacitance (V in = 0)C in — — — — — — pFÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎGate Quiescent CurrentI DD 5.0 — 0.25 — 0.25 — 7.5 µAdc(Per Package)1.64.2— 1.3— 3.4± 0.1 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎFlip–Flop and Buffer Quiescent CurrentI DDÎÎÎÎ 5.0 — 1.0 —(Per Package)10151015——0.92.40.050.05———1.53.04.0———1.02.02.5———————————————————VdcmAdcmAdcmAdc± 0.1 ÎÎÎ ± 1.0 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ0.5 — 157.51.0 — 301.0 — 302.0 — 604.0 — 1205.0 — 15010 — 30020 — 600ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMSI Quiescent CurrentÎÎÎI DD ÎÎÎ5.0ÎÎΗÎÎÎ5.0ÎÎÎÎÎÎÎÎÎΗµAdcÎÎÎÎ(Per Package)1015————0.51.02.04.0————µAdcÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎLSI Quiescent CurrentI DDÎÎÎÎSee Individual Data Sheets.——1020——ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎhttp://onsemi.com22ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

CHAPTER 5CMOS Handling and Design Guidelineshttp://onsemi.com23

HANDLING PRECAUTIONSAll MOS devices have insulated gates that are subject tovoltage breakdown. The gate oxide for ON SemiconductorCMOS devices is about 900 Å thick and breaks down at agate–source potential of about 100 volts. To guard againstsuch a breakdown from static discharge or other voltagetransients, the protection networks shown in Figures 1A and1B are used on each input to the CMOS device.Static damaged devices behave in various ways,depending on the severity of the damage. The most severelydamaged inputs are the easiest to detect because the inputhas been completely destroyed and is either shorted to V DD ,shorted to V SS , or open–circuited. The effect is that thedevice no longer responds to signals present at the damagedinput. Less severe cases are more difficult to detect becausethey show up as intermittent failures or as degradedperformance. Another effect of static damage is that theinputs generally have increased leakage currents.Although the input protection network does provide agreat deal of protection, CMOS devices are not immune tolarge static voltage discharges that can be generated duringhandling. For example, static voltages generated by a personwalking across a waxed floor have been measured in the4–15 kV range (depending on humidity, surface conditions,etc.). Therefore, the following precautions should beobserved:1. Do not exceed the Maximum Ratings specified by thedata sheet.2. All unused device inputs should be connected to V DDor V SS .3. All low–impedance equipment (pulse generators,etc.) should be connected to CMOS inputs only afterthe device is powered up. Similarly, this type ofequipment should be disconnected before power isturned off.4. Circuit boards containing CMOS devices are merelyextensions of the devices, and the same handlingprecautions apply. Contacting edge connectors wireddirectly to device inputs can cause damage. Plasticwrapping should be avoided. When externalconnections to a PC board are connected to an input ofa CMOS device, a resistor should be used in serieswith the input. This resistor helps limit accidentaldamage if the PC board is removed and brought intocontact with static generating materials. The limitingfactor for the series resistor is the added delay. This iscaused by the time constant formed by the seriesresistor and input capacitance. Note that the maximuminput rise and fall times should not be exceeded. InFigure 2, two possible networks are shown using aseries resistor to reduce ESD (ElectrostaticDischarge) damage. For convenience, an equation foradded propagation delay and rise time effects due toseries resistance size is given.5. All CMOS devices should be stored or transported inmaterials that are antistatic. CMOS devices must notbe inserted into conventional plastic “snow”,styrofoam, or plastic trays, but should be left in theiroriginal container until ready for use.6. All CMOS devices should be placed on a groundedbench surface and operators should groundthemselves prior to handling devices, since a workercan be statically charged with respect to the benchsurface. Wrist straps in contact with skin are stronglyrecommended. See Figure 3 for an example of atypical work station.7. Nylon or other static generating materials should notcome in contact with CMOS devices.8. If automatic handlers are being used, high levels ofstatic electricity may be generated by the movementof the device, the belts, or the boards. Reduce staticbuild–up by using ionized air blowers or roomhumidifiers. All parts of machines which come intocontact with the top, bottom, or sides of IC packagesmust be grounded to metal or other conductivematerial.9. Cold chambers using CO 2 for cooling should beequipped with baffles, and the CMOS devices must becontained on or in conductive material.10. When lead–straightening or hand–soldering isnecessary, provide ground straps for the apparatusused and be sure that soldering ties are grounded.http://onsemi.com24

INPUT PROTECTION NETWORKV DDV DDCMOSINPUT< 1500 ΩTO CIRCUITCMOSINPUT300 ΩV SSFigure 1a. Input Protection NetworkDouble DiodeV SSFigure 1b. Input Protection NetworkTriple Diode11. The following steps should be observed during wavesolder operations:a. The solder pot and conductive conveyor system ofthe wave soldering machine must be grounded toan earth ground.b. The loading and unloading work benches shouldhave conductive tops which are grounded to anearth ground.c. Operators must comply with precautionspreviously explained.d. Completed assemblies should be placed inantistatic containers prior to being moved tosubsequent stations.12. The following steps should be observed duringboard–cleaning operations:a. Vapor degreasers and baskets must be grounded toan earth ground.b. Brush or spray cleaning should not be used.c. Assemblies should be placed into the vapordegreaser immediately upon removal from theantistatic container.d. Cleaned assemblies should be placed in antistaticcontainers immediately after removal from thecleaning basket.e. High velocity air movement or application ofsolvents and coatings should be employed onlywhen assembled printed circuit boards aregrounded and a static eliminator is directed at theboard.13. The use of static detection meters for production linesurveillance is highly recommended.14. Equipment specifications should alert users to thepresence of CMOS devices and requirefamiliarization with this specification prior toperforming any kind of maintenance or replacementof devices or modules.15. Do not insert or remove CMOS devices from testsockets with power applied. Check all power suppliesto be used for testing devices to be certain there are novoltage transients present.16. Double check test equipment setup for proper polarityof V DD and V SS before conducting parametric orfunctional testing.17. Do not recycle shipping rails or trays. Repeated usecauses deterioration of their antistatic coating.RECOMMENDED FOR READING:“Total Control of the Static in Your Business”Available by writing to:3M CompanyStatic Control SystemsP.O. Box 2963Austin, Texas 78769–2963Or by Calling:1–800–328–1368http://onsemi.com25

V DDTO OFF–BOARDCONNECTIONR1CMOSINPUTOROUTPUTTO OFF–BOARDCONNECTIONR2D1D2CMOSINPUTOROUTPUTAdvantage:Disadvantage:Requires minimal board areaR1 > R2 for the same level ofprotection, therefore rise and falltimes, propagation delays, and outputdrives are severely affected.Advantage:R2 < R1 for the samelevel of protection.Impact on ac and dccharacteristics is minimizedDisadvantage: More board area, higher initial costNote: These networks are useful for protecting the followingABdigital inputs and outputsanalog inputs and outputsCD3–state outputsbidirectional (I/O) portsV SSPROPAGATION DELAY AND RISE TIMEvs. SERIES RESISTANCERtwhere:C kR = the maximum allowable series resistance in ohmst = the maximum tolerable propagation delay or rise time in secondsC = the board capacitance plus the driven device’s= input capacitance in faradsk = 0.7 for propagation delay calculationsk = 2.3 for rise time calculationsFigure 2. Networks for Minimizing ESD and ReducingCMOS Latch Up Susceptibilityhttp://onsemi.com26

53412NOTES: 1. 1/16 inch conductive sheet stock covering benchtop work area.2. Ground strap.3. Wrist strap in contact with skin.4. Static neutralizer. (Ionized air blower directed atwork.) Primarily for use in areas where directgrounding is impractical.5. Room humidifier. Primarily for use in areas wherethe relative humidity is less than 45%. Caution:building heating and cooling systems usually drythe air causing the relative humidity inside ofbuildings to be less than outside humidity.RESISTOR =1 MEGAOHMFigure 3. Typical Manufacturing Work StationPOWER SUPPLIESCMOS devices have low power requirements and theability to operate over a wide range of supply voltages.These two characteristics allow CMOS designs to beimplemented using inexpensive, conventional powersupplies, instead of switching power supplies and powersupplies with cooling fans. In addition, batteries may be usedas either a primary power source or for emergency backup.The absolute maximum power supply voltage for 14000Series Metal–gate CMOS is 18.0 Vdc. Figure 4 offers someinsight as to how this specification was derived. In thefigure, V S is the maximum power supply voltage and I S isthe sustaining current of the latch–up mode. The value of V Swas chosen so that the secondary breakdown effect may beavoided.In an ideal system design, a power supply should bedesigned to deliver only enough current to insure properoperation of all devices. The obvious benefit of this typedesign is cost savings; an added benefit is protection againstthe possibility of latch–up related failures. This systemprotection can be provided by the power supply filter and/orvoltage regulator.CMOS devices can be used with battery or battery backupsystems. A few precautions should be taken when designingbattery–operated systems:1. The recommended power supply voltage should beobserved. For battery backup systems such as the onein Figure 5, the battery voltage must be at least 3.7Volts (3 Volts from the minimum power supplyvoltage and 0.7 Volts to account for the voltage dropacross the series diode).2. Inputs that might go above the battery backup voltageshould either use a series resistor to limit the inputcurrent to less than 10 mA or use the MC14049UB orMC14050B high–to–low voltage translators.3. Outputs that are subject to voltage levels above V DDor below V SS should be protected with a series resistorto limit the current to less than 10 mA or withclamping diodes.I DDLATCHUP MODESECONDARYBREAKDOWNLOW CURRENTJUNCTIONAVALANCHEI SV S V DDV S = DATA SHEET MAXIMUM SUPPLY RATINGFigure 4. Secondary Breakdown Characteristicshttp://onsemi.com27

POWER SUPPLYLINE POWER ONLYSYSTEMBATTERY BACKUPSYSTEMBATTERY BACKUPRECHARGECMOSSYSTEMMC14049UBMC14050BCMOSSYSTEMMC14049UBMC14050BFigure 5. Battery Backup InterfaceINPUTSV DD = 5.0 VdcAll inputs, while in the recommended operating range(V SS < V in < V DD ) can be modeled as shown in Figure 6. Forinput voltages in this range, diodes D1 and D2 are modeledas resistors, representing the reverse bias impedance of thediodes. The maximum input current is worst case, 1 µA,when the inputs are at V DD or V SS , and V DD = 15.0 V. Thismodel does not apply to inputs with pull–up or pull–downresistors.V out , OUTPUT VOLTAGE (V)5.04.03.02.0SINGLE INPUT NAND, ANDMULTIPLE INPUT NOR, ORSINGLE INPUT NOR, ORMULTIPLE INPUT NAND, AND1.0V DDR1R1 = R2 = HIGH Z00 1.0 2.0 3.0 4.0 5.0V in , INPUT VOLTAGE (V)Figure 7. Typical Transfer Characteristicsfor Buffered DevicesR27.5 pFFigure 6. Input Model for V SS V in V DDWhen left open–circuited, the inputs may self–bias at ornear the typical switchpoint, where both the P–channel andN–channel transistors are conducting, causing excessivecurrent drain. Due to the high gain of the inverters (seeFigure 7), the device may also go into oscillation from anynoise in the system. Since CMOS devices dissipate the mostpower during switching, this oscillation can cause very largecurrent drain and undesired switching.For these reasons, all unused inputs should be connectedeither to V DD or V SS . For applications with inputs going toedge connectors, a 100 kilohm resistor to V SS should beused, as well as a series resistor for static protection andcurrent limiting (Figure 8). The 100 kilohm resistor will helpeliminate any static charges that might develop on theprinted circuit board. See Figure 2 for other possibleprotection arrangements.FROMEDGECONNECTOR100 kR SFigure 8. External ProtectionCMOSDEVICEhttp://onsemi.com28

For input voltages outside of the recommended operatingrange, the CMOS input is modeled as in Figure 9. Theresistor–diode protection network allows the user greaterfreedom when designing a worst case system. The deviceinputs are guaranteed to withstand voltages from V SS – 0.5V to V DD + 0.5 V and a maximum current of 10 mA. Withthe above input ratings, most designs will require no specialterminations or design considerations.D1 1.5 kFigure 9. Input Model for V in > V DD or V in < V SSD27.5 pFOther specifications that should be noted are themaximum input rise and fall times. Figure 10 shows theoscillations that may result from exceeding the 15 µsmaximum rise and fall time at V DD = 5.0 V, 5 µs at 10 V, or4 µs at 15 V. As the voltage passes through the switchingthreshold region with a slow rise time, any noise that is onthe input is amplified, and passed through to the output,causing oscillations. The oscillation may have a low enoughfrequency to cause succeeding stages to switch, givingunexpected results. If input rise or fall times are expected toexceed 15 µs at 5.0 V, 5 µs at 10 V, or 4 µs at 15 V,Schmitt–trigger devices such as the MC14093B,MC14584B, MC14106B, HC14, or HC132 arerecommended for squaring–up these slow transitions.V DDV inV SSV OHV outV OLFigure 10. Maximum Rise and Fall Time ViolationsOUTPUTSAll CMOS B–Series outputs are buffered to insureconsistent output voltage and current performance. Allbuffered outputs have guaranteed output voltages of V OL =0.05 V and V OH = V DD – 0.05 V for V in = V DD or V SS andl out = 0 µA. The output drives for all buffered CMOS devicesare such that 1 LSTTL load can be driven across the fulltemperature range.CMOS outputs are limited to externally forced outputvoltages of V SS – 0.5 V V out V DD + 0.5 V. Whenvoltages are forced outside of this range, a silicon controlledrectifier (SCR) formed by parasitic transistors can betriggered, causing the device to latch up. For moreinformation on this, see the explanation of CMOS Latch Upin this section.The maximum rated output current for most outputs is10 mA. The output short–circuit currents of these devicestypically exceed these limits. Care must be taken not toexceed the maximum ratings found on every data sheet.For applications that require driving high capacitive loadswhere fast propagation delays are needed (e.g., drivingpower MOSFETs), two or more outputs on the same chipmay be externally paralleled.CMOS LATCH UPLatch up will not be a problem for most designs, but thedesigner should be aware of it, what causes it, and how toprevent it.Figure 11 shows the cross–section of a typical CMOSinverter and Figure 12 shows the parasitic bipolar devices.The circuit formed by the parasitic transistors and resistorsis the basic configuration of a silicon controlled rectifier, orSCR. In the latch up condition, transistors Q1 and Q2 areturned ON, each providing the base current necessary for theother to remain in saturation, thereby latching the devices inthe ON state. Unlike a conventional SCR, where the deviceis turned ON by applying a voltage to the base of the NPNtransistor, the parasitic SCR is turned ON by applying avoltage to the emitter of either transistor. The two emittersthat trigger the SCR are the same point, the CMOS output.Therefore, to latch up the CMOS device, the output voltagemust be greater than V DD + 0.5 V or less than V SS – 0.5 Vand have sufficient current to trigger the SCR. The latch–upmechanism is similar for the inputs.Once a CMOS device is latched up, if the supply currentis not limited, the device will be destroyed. Ways to preventsuch occurrences are listed below:1. Insure that inputs and outputs are limited to themaximum rated values, as follows:–0.5 V ≤ V in or V out V DD + 0.5 V (referenced toV SS ) |I in or I out | 10 mA (unless otherwise indicatedon the data sheet)2. If voltage transients of sufficient energy to latch up thedevice are expected on the inputs or outputs, externalprotection diodes can be used to clamp the voltage.Another method of protection is to use a series resistorto limit the expected worst case current to themaximum rating of 10 mA. (See Figure 2).3. Sequence power supplies so that the inputs or outputsof CMOS devices are not active before the supply pinsare powered up (e.g., recessed edge connectors and/orhttp://onsemi.com29

series resistors may be used in plug–in boardapplications).4. Voltage regulating or filtering should be used in boarddesign and layout to insure that power–supply linesare free of excessive noise.5. Limit the available power supply current to thedevices that are subject to latch–up conditions. Thiscan be accomplished with the power supply filteringnetwork or with a current–limiting regulator.P–CHANNELINPUTN–CHANNELV DDV DDP–CHANNELOUTPUTOUTPUTN–CHANNELOUTPUTV SSFIELD OXIDE FIELD OXIDE FIELD OXIDEN+ P+ P+ N+ N+ P+ÇÇÇÇÇN – SUBSTRATEP – WELLFigure 11. CMOS Wafer Cross SectionN–CHANNEL OUTPUTN+Q1N+ N–N–SUBSTRATE RESISTANCEV DDV SSV SSP–WELL RESISTANCEP–N–P–Q2P+P+V DDP–CHANNEL OUTPUTFigure 12. Latch Up Circuit Schematichttp://onsemi.com30

http://onsemi.com31CHAPTER 6CMOS Logic Data Sheets

MC14001B, MC14011B, MC14023B,MC14025B, MC14071B, MC14073B,MC14081B, MC14082BThe B Series logic gates are constructed with P and N channelenhancement mode devices in a single monolithic structure(Complementary MOS). Their primary use is where low powerdissipation and/or high noise immunity is desired.• Supply Voltage Range = 3.0 Vdc to 18 Vdc• All Outputs Buffered• Capable of Driving Two Low–power TTL Loads or One Low–powerSchottky TTL Load Over the Rated Temperature Range.• Double Diode Protection on All Inputs Except: Triple DiodeProtection on MC14011B and MC14081B• Pin–for–Pin Replacements for Corresponding CD4000 Series BSuffix DevicesMAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 1.)Symbol Parameter Value UnitV DD DC Supply Voltage Range –0.5 to +18.0 VV in , V out Input or Output Voltage Range(DC or Transient)–0.5 to V DD + 0.5 VI in , I outP DInput or Output Current(DC or Transient) per PinPower Dissipation,per Package (Note 2.)±10 mA500 mWT A Ambient Temperature Range –55 to +125 °CT stg Storage Temperature Range –65 to +150 °CT LLead Temperature(8–Second Soldering)260 °C1. Maximum Ratings are those values beyond which damage to the devicemay occur.2. Temperature Derating:Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 CThis device contains protection circuitry to guard against damage due to highstatic voltages or electric fields. However, precautions must be taken to avoidapplications of any voltage higher than maximum rated voltages to thishigh–impedance circuit. For proper operation, V in and V out should be constrainedto the range V SS (V in or V out ) V DD .Unused inputs must always be tied to an appropriate logic voltage level (e.g.,either V SS or V DD ). Unused outputs must be left open.DeviceMC14001BMC14011BMC14023BMC14025BMC14071BMC14073Bhttp://onsemi.comPDIP–14P SUFFIXCASE 646SOIC–14D SUFFIXCASE 751ATSSOP–14DT SUFFIXCASE 948GSOEIAJ–14F SUFFIXCASE 965DEVICE INFORMATIONDescriptionQuad 2–Input NOR GateQuad 2–Input NAND GateTriple 3–Input NAND GateTriple 3–Input NOR GateQuad 2–Input OR GateMARKINGDIAGRAMS14114114MC140XXBCPAWLYYWW140XXBAWLYWW14XX = Specific Device CodeA = Assembly LocationWL or L = Wafer LotYY or Y = YearWW or W = Work Week11Triple 3–Input AND Gate140XXBALYWMC140XXBAWLYWWMC14081BMC14082BQuad 2–Input AND GateDual 4–Input AND GateORDERING INFORMATIONSee detailed ordering and shipping information in the packagedimensions section on page 39 of this data sheet.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 132 Publication Order Number:MC14001B/D

MC14001B SeriesLOGIC DIAGRAMSNORNANDORANDMC14001BQuad 2–Input NOR GateMC14011BQuad 2–Input NAND GateMC14071BQuad 2–Input OR GateMC14081BQuad 2–Input AND Gate1231231231232 INPUT5689410568941056894105689410121311121311121311121311MC14025BTriple 3–Input NOR GateMC14023BTriple 3–Input NAND GateMC14073BTriple 3–Input AND GateMC14082BDual 4–Input AND Gate3 INPUT12 9834 651112 1013MC14001BQuad 2–Input NOR Gate12 9834 651112 1013MC14011BQuad 2–Input NAND GatePIN ASSIGNMENTS12 9834 651112 1013MC14023BTriple 3–Input NAND Gate23459101112V DD = PIN 14V SS = PIN 7FOR ALL DEVICESNC = 6, 8MC14025BTriple 3–Input NOR Gate113IN 1 AIN 2 A121413V DDIN 2 DIN 1 AIN 2 A121413V DDIN 2 DIN 1 AIN 2 A121413V DDIN 3 CIN 1 AIN 2 A121413OUT A 3 12 IN 1 D OUT A 3 12 IN 1 D IN 1 B 3 12 IN 2 C IN 1 B 3 12OUT B 4 11 OUT D OUT B 4 11 OUT D IN 2 B 4 11 IN 1 C IN 2 B 4 11IN 1 B 5 10 OUT C IN 1 B 5 10 OUT C IN 3 B 5 10 OUT C IN 3 B 5 10IN 2 B 6 9 IN 2 C IN 2 B 6 9 IN 2 C OUT B 6 9 OUT A OUT B 6 9V SS 7 8 IN 1 C V SS 7 8 IN 1 C V SS 7 8 IN 3 A V SS 7 8V DDIN 3 CIN 2 CIN 1 COUT COUT AIN 3 AMC14071BQuad 2–Input OR GateMC14073BTriple 3–Input AND GateMC14081BQuad 2–Input AND GateMC14082BDual 4–Input AND GateIN 1 AIN 2 A121413V DDIN 2 DIN 1 AIN 2 A121413V DDIN 3 CIN 1 AIN 2 A121413V DDIN 2 DOUT AIN 1 A121413OUT A 3 12 IN 1 D IN 1 B 3 12 IN 2 C OUT A 3 12 IN 1 D IN 2 A 3 12OUT B 4 11 OUT D IN 2 B 4 11 IN 1 C OUT B 4 11 OUT D IN 3 A 4 11IN 1 B 5 10 OUT C IN 3 B 5 10 OUT C IN 1 B 5 10 OUT C IN 4 A 5 10IN 2 B 6 9 IN 2 C OUT B 6 9 OUT A IN 2 B 6 9 IN 2 CNC 6 9V SS 7 8 IN 1 C V SS 7 8 IN 3 A V SS 7 8 IN 1 C V SS 7 8V DDOUT BIN 4 BIN 3 BIN 2 BIN 1 BNCNC = NO CONNECTIONhttp://onsemi.com33

MC14001B SeriesELECTRICAL CHARACTERISTICS (Voltages Referenced to V SS )ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΖ 55 C 25 C ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCharacteristicV DDSymbol ÎÎÎVdc ÎÎÎÎÎÎMin 125 ÎÎÎCÎÎÎMin UnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMin Typ (3.) MaxÎÎÎÎ MaxMaxÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput VoltageV in = V DD or 0“0” Level“1” LevelV OL5.01015———ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎV in = 0 or V DDInput Voltage(V O = 4.5 or 0.5 Vdc)(V O = 9.0 or 1.0 Vdc)(V O = 13.5 or 1.5 Vdc)“0” LevelV OHV IL5.010154.959.9514.95ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5.01015———0.050.050.05——————4.959.9514.950005.010150.050.050.05——————4.959.9514.95ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V O = 0.5 or 4.5 Vdc)(V O = 1.0 or 9.0 Vdc)(V O = 1.5 or 13.5 Vdc)“1” LevelV IH5.010153.57.011ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Drive Current(V OH = 2.5 Vdc) Source(V OH = 4.6 Vdc)(V OH = 9.5 Vdc)(V OH = 13.5 Vdc)I OHÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5.05.01015– 3.0– 0.64– 1.6– 4.2ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V OL = 0.4 Vdc) Sink(V OL = 0.5 Vdc)(V OL = 1.5 Vdc)I OL5.010150.641.64.2ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ1.53.04.0——————————3.57.011– 2.4– 0.51– 1.3– 3.42.254.506.752.755.508.25– 4.2– 0.88– 2.25– 8.81.53.04.0——————————3.57.011– 1.7– 0.36– 0.9– 2.4ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput CurrentÎÎÎÎÎÎ15 — ± — ±0.00001— ± µAdcÎÎÎ ÎÎÎ 0.1ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ 1.0ÎÎÎÎÎÎÎI inÎÎÎÎÎÎÎÎÎÎInput CapacitanceÎÎÎÎC ÎÎÎÎÎÎin — — — — 5.0 — — pFÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V in = 0)Quiescent Current(Per Package)I DD5.01015——————0.511.33.40.882.258.8———0.360.92.4± 0.17.5 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTotal Supply Current (4.) (5.)(Dynamic plus Quiescent,Per Gate, C L = 50 pF)I T5.01015ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ0.250.51.0———0.00050.00100.0015ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ0.250.51.0I T = (0.3 µA/kHz) f + I DD /NI T = (0.6 µA/kHz) f + I DD /NI T = (0.9 µA/kHz) f + I DD /N3. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.4. The formulas given are for the typical characteristics only at 25 C.5. To calculate total supply current at loads other than 50 pF:I T (C L ) = I T (50 pF) + (C L – 50) Vfk———0.050.050.05———1.53.04.0——————————7.51530VdcVdcVdcVdcmAdcmAdcµAdcµAdcwhere: I T is in µA (per package), C L in pF, V = (V DD – V SS ) in volts, f in kHz is input frequency, and k = 0.001 x the number of exercised gatesper package.http://onsemi.com34

MC14001B SeriesB–SERIES GATE SWITCHING TIMESSWITCHING CHARACTERISTICS (6.) (C L = 50 pF, T A = 25 C)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCharacteristicÎÎÎÎSymbolMin Typ (7.) Max UnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Rise Time, All B–Series Gatest TLH = (1.35 ns/pF) C L + 33 nst TLH = (0.60 ns/pF) C L + 20 nst TLH = (0.40 ns/PF) C L + 20 nst TLHÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Fall Time, All B–Series Gatest THL = (1.35 ns/pF) C L + 33 nst THL = (0.60 ns/pF) C L + 20 nst THL = (0.40 ns/pF) C L + 20 nst THLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPropagation Delay TimeMC14001B, MC14011B onlyt PLH , t PHL = (0.90 ns/pF) C L + 80 nst PLH , t PHL = (0.36 ns/pF) C L + 32 nsÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎt PLH , t PHL = (0.26 ns/pF) C L + 27 nsAll Other 2, 3, and 4 Input Gatest PLH , t PHL = (0.90 ns/pF) C L + 115 nsÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎt PLH , t PHL = (0.36 ns/pF) C L + 47 nst PLH , t PHL = (0.26 ns/pF) C L + 37 ns8–Input Gates (MC14068B, MC14078B)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎt PLH , t PHL = (0.90 ns/pF) C L + 155 nst PLH , t PHL = (0.36 ns/pF) C L + 62 nst PLH , t PHL = (0.26 ns/pF) C L + 47 nst PLH , t PHLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ6. The formulas given are for the typical characteristics only at 25 C.7. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎV DDVdc5.010155.010155.010155.010155.01015———————————————10050401005040125504016065502008060200100802001008025010080300130100350150110nsnsnsPULSEGENERATORINPUT*147V DDV SSC LOUTPUT*All unused inputs of AND, NAND gates must be connected to V DD .All unused inputs of OR, NOR gates must be connected to V SS .20 ns 20 nsINPUT90%50%10%t PHLt PLH90%OUTPUT50%10%INVERTINGt THLt TLHt PLHOUTPUTNON–INVERTINGt TLHV DD0 VV OHV OLt PHLV OH90%50%10% V OLt THLFigure 1. Switching Time Test Circuit and Waveformshttp://onsemi.com35

MC14001B SeriesCIRCUIT SCHEMATICNOR, OR GATESMC14001B, MC14071BOne of Four Gates ShownMC14025BOne of Three Gates Shown1, 6, 8, 132, 5, 9, 12V DD14 V DD1, 3, 11*2, 4, 123, 4, 10, 117 V SSV SS*Inverter omitted in MC14001BV SSV DDV DD*14V DD9, 6, 108, 5, 137V SSV SS*Inverter omitted in MC14025BCIRCUIT SCHEMATICNAND, AND GATESMC14023B, MC14073BOne of Three Gates ShownV DDMC14011B, MC14081BOne of Four Gates Shown*14V DD3, 4, 10, 112, 4, 1214V DD2, 5, 9, 121, 3, 11V SSV DDV SS*1, 6, 8, 137*Inverter omitted in MC14011BV SS8, 5, 139, 6, 10*Inverter omitted in MC14023B7V SShttp://onsemi.com36

MC14001B SeriesTYPICAL B–SERIES GATE CHARACTERISTICSN–CHANNEL DRAIN CURRENT (SINK)P–CHANNEL DRAIN CURRENT (SOURCE)5.0– 10– 9.0I D , DRAIN CURRENT (mA)4.03.02.01.0T A = – 55°C+ 85°C– 40°C+ 25°C+ 125°CI D , DRAIN CURRENT (mA)– 8.0– 7.0– 6.0– 5.0– 4.0– 3.0– 2.0T A = – 55°C+ 85°C– 40°C+ 25°C+ 125°C– 1.0001.0 2.0 3.0 4.0 5.000– 1.0 – 2.0 – 3.0 – 4.0 – 5.0V DS , DRAIN–TO–SOURCE VOLTAGE (Vdc)V DS , DRAIN–TO–SOURCE VOLTAGE (Vdc)Figure 2. V GS = 5.0 VdcFigure 3. V GS = – 5.0 Vdc20– 50I D , DRAIN CURRENT (mA)18161412108.06.04.0T A = – 55°C– 40°C+ 25°C+ 85°C+ 125°CI D , DRAIN CURRENT (mA)– 45– 40– 35– 30– 25– 20– 15– 10T A = – 55°C– 40°C+ 25°C+ 85°C+ 125°C2.000– 5.01.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 1000 – 1.0 – 2.0 – 3.0 – 4.0 – 5.0 – 6.0 – 7.0 – 8.0 – 9.0 – 10V DS , DRAIN–TO–SOURCE VOLTAGE (Vdc)V DS , DRAIN–TO–SOURCE VOLTAGE (Vdc)Figure 4. V GS = 10 VdcFigure 5. V GS = – 10 Vdc50– 10045– 9040– 80I D , DRAIN CURRENT (mA)353025201510T A = – 55°C– 40°C+ 25°C+ 125°C+ 85°CI D , DRAIN CURRENT (mA)– 70– 60– 50– 40– 30– 20T A = – 55°C– 40°C+ 25°C+ 85°C+ 125°C5.0– 100 00 2.0 4.0 6.0 8.0 10 12 14 16 18 200V DS , DRAIN–TO–SOURCE VOLTAGE (Vdc)Figure 6. V GS = 15 Vdc– 2.0 – 4.0 – 6.0 – 8.0 – 10 – 12 – 14 – 16 – 18 – 20V DS , DRAIN–TO–SOURCE VOLTAGE (Vdc)Figure 7. V GS = – 15 VdcThese typical curves are not guarantees, but are design aids.Caution: The maximum rating for output current is 10 mA per pin.http://onsemi.com37

MC14001B SeriesTYPICAL B–SERIES GATE CHARACTERISTICS (cont’d)VOLTAGE TRANSFER CHARACTERISTICSV out , OUTPUT VOLTAGE (Vdc)5.04.03.02.01.0SINGLE INPUT NAND, ANDMULTIPLE INPUT NOR, ORSINGLE INPUT NOR, ORMULTIPLE INPUT NAND, ANDV out , OUTPUT VOLTAGE (Vdc)108.06.04.02.0SINGLE INPUT NAND, ANDMULTIPLE INPUT NOR, ORSINGLE INPUT NOR, ORMULTIPLE INPUT NAND, AND001.0 2.0 3.0 4.0 5.0V in , INPUT VOLTAGE (Vdc)002.0 4.0 6.0 8.0 10V in , INPUT VOLTAGE (Vdc)Figure 8. V DD = 5.0 VdcFigure 9. V DD = 10 VdcV out , OUTPUT VOLTAGE (Vdc)1600 2.0 4.0 6.0 8.0 1014SINGLE INPUT NAND, ANDMULTIPLE INPUT NOR, OR1210SINGLE INPUT NOR, ORMULTIPLE INPUT NAND, AND8.06.04.02.0V in , INPUT VOLTAGE (Vdc)Figure 10. V DD = 15 VdcDC NOISE MARGINThe DC noise margin is defined as the input voltage rangefrom an ideal “1” or “0” input level which does not produceoutput state change(s). The typical and guaranteed limitvalues of the input values V IL and V IH for the output(s) tobe at a fixed voltage V O are given in the ElectricalCharacteristics table. V IL and V IH are presented graphicallyin Figure 11.Guaranteed minimum noise margins for both the “1” and“0” levels =1.0 V with a 5.0 V supply2.0 V with a 10.0 V supply2.5 V with a 15.0 V supplyV outV DDV outV DDV OV OV OV OV DDV DD0V in0V inV ILV IH(a) Inverting FunctionV IL V IHV SS = 0 VOLTS DC(b) Non–Inverting FunctionFigure 11. DC Noise Immunityhttp://onsemi.com38

MC14001B SeriesORDERING & SHIPPING INFORMATION:Device Package ShippingMC14001BCP PDIP–14 2000 Units per BoxMC14001BD SOIC–14 2750 Units per BoxMC14001BDR2 SOIC–14 2500 Units / Tape & ReelMC14001BDT TSSOP–14 96 Units per RailMC14001BDTR2 TSSOP–14 96 Units per RailORDERING & SHIPPING INFORMATION:Device Package ShippingMC14071BCP PDIP–14 2000 Units per BoxMC14071BD SOIC–14 55 Units per RailMC14071BDR2 SOIC–14 2500 Units / Tape & ReelMC14071BDT TSSOP–14 96 Units per RailMC14071BDTR2 TSSOP–14 96 Units per RailMC14011BCP PDIP–14 2000 Units per BoxMC14011BD SOIC–14 2750 Units per BoxMC14011BDR2 SOIC–14 2500 Units / Tape & ReelMC14011BDT TSSOP–14 96 Units per RailMC14011BDTEL TSSOP–14 2000 Units / Tape & ReelMC14011BDTR2 TSSOP–14 50 Units per RailMC14023BCP PDIP–14 2000 Units per BoxMC14023BD SOIC–14 2750 Units per BoxMC14023BDR2 SOIC–14 2500 Units / Tape & ReelMC14025BCP PDIP–14 2000 Units per BoxMC14025BD SOIC–14 2750 Units per BoxMC14025BDR2 SOIC–14 2500 Units / Tape & ReelMC14073BCP PDIP–14 2000 Units per BoxMC14073BD SOIC–14 55 Units per RailMC14073BDR2 SOIC–14 2500 Units / Tape & ReelMC14081BCP PDIP–14 2000 Units per BoxMC14081BD SOIC–14 55 Units per RailMC14081BDR2 SOIC–14 2500 Units / Tape & ReelMC14081BDT TSSOP–14 96 Units per RailMC14081BDTR2 TSSOP–14 2500 Units / Tape & ReelMC14082BCP PDIP–14 2000 Units per BoxMC14082BD SOIC–14 55 Units per RailMC14082BDR2 SOIC–14 2500 Units / Tape & ReelFor ordering information on the EIAJ version of the SOIC packages,please contact your local ON Semiconductor representative.http://onsemi.com39

The UB Series logic gates are constructed with P and N channelenhancement mode devices in a single monolithic structure(Complementary MOS). Their primary use is where low powerdissipation and/or high noise immunity is desired. The UB set ofCMOS gates are inverting non–buffered functions.• Supply Voltage Range = 3.0 Vdc to 18 Vdc• Linear and Oscillator Applications• Capable of Driving Two Low–power TTL Loads or One Low–powerSchottky TTL Load Over the Rated Temperature Range• Double Diode Protection on All Inputs• Pin–for–Pin Replacements for Corresponding CD4000 Series UBSuffix DevicesMAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 1.)Symbol Parameter Value UnitV DD DC Supply Voltage Range –0.5 to +18.0 VV in , V out Input or Output Voltage Range(DC or Transient)–0.5 to V DD + 0.5 VI in , I outP DInput or Output Current(DC or Transient) per PinPower Dissipation,per Package (Note 2.)±10 mA500 mWhttp://onsemi.comMC14001UBQuad 2–Input NOR GateMC14011UBQuad 2–Input NAND GatePDIP–14P SUFFIXCASE 646SOIC–14D SUFFIXCASE 751AMARKINGDIAGRAMS14MC140XXUBCPAWLYYWW1141140XXUAWLYWWT A Ambient Temperature Range –55 to +125 °CT stg Storage Temperature Range –65 to +150 °CT LLead Temperature(8–Second Soldering)260 °C1. Maximum Ratings are those values beyond which damage to the devicemay occur.2. Temperature Derating:Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 CThis device contains protection circuitry to guard against damage due to highstatic voltages or electric fields. However, precautions must be taken to avoidapplications of any voltage higher than maximum rated voltages to thishigh–impedance circuit. For proper operation, V in and V out should be constrainedto the range V SS (V in or V out ) V DD .Unused inputs must always be tied to an appropriate logic voltage level (e.g.,either V SS or V DD ). Unused outputs must be left open.XX = Specific Device CodeA = Assembly LocationWL or L = Wafer LotYY or Y = YearWW or W = Work WeekORDERING INFORMATIONDevice Package ShippingMC14001UBCP PDIP–14 2000/BoxMC14001UBD SOIC–14 55/RailMC14001UBDR2 SOIC–14 2500/Tape & ReelMC14011UBCPMC14011UBDMC14011UBDR2PDIP–14SOIC–14SOIC–142000/Box55/Rail2500/Tape & Reel© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 340 Publication Order Number:MC14001UB/D

MC14001UB, MC14011UBLOGIC DIAGRAMSMC14001UBQuad 2–InputNOR GateMC14011UBQuad 2–InputNAND Gate12568912133410111256891213341011V DD = PIN 14V SS = PIN 7FOR ALL DEVICESPIN ASSIGNMENTSMC14001UBQuad 2–Input NOR GateMC14011UBQuad 2–Input NAND GateIN 1 AIN 2 A121413V DDIN 2 DIN 1 AIN 2 A121413OUT A 3 12 IN 1 DOUT A 3 12OUT B 4 11 OUT DOUT B 4 11IN 1 B 5 10 OUT CIN 1 B 5 10IN 2 B 6 9 IN 2 CIN 2 B 6 9V SS 7 8 IN 1 CV SS 7 8V DDIN 2 DIN 1 DOUT DOUT CIN 2 CIN 1 Chttp://onsemi.com41

MC14001UB, MC14011UBELECTRICAL CHARACTERISTICS (Voltages Referenced to V SS )ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΖ 55 C 25 C DDCharacteristicOutput VoltageV in = V DD or 0“0” LevelV DDSymbolÎÎÎÎÎVdcV OL 5.0 —10 —15 —125 ÎÎÎCÎÎÎMax UnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMinÎÎÎÎÎÎ MaxÎÎÎÎÎÎÎÎÎMinÎÎÎMaxÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎV in = 0 or V DDLevelÎÎÎΓ1” V OH 5.010154.959.9514.95ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput Voltage(V O = 4.5 Vdc)(V O = 9.0 Vdc)(V O = 13.5 Vdc)“0” LevelV ILÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5.01015———0.050.050.05———Min———4.959.9514.95Typ (3.)0005.010150.050.050.05——————4.959.9514.95ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V O = 0.5 Vdc) “1” Level(V O = 1.0 Vdc)(V O = 1.5 Vdc)I IH5.010154.08.012.5ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Drive Current(V OH = 2.5 Vdc) Source(V OH = 4.6 Vdc)ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V OH = 9.5 Vdc)(V OH = 13.5 Vdc)I OH5.05.01015– 1.2– 0.25– 0.62– 1.8ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V OL = 0.4 Vdc) Sink(V OL = 0.5 Vdc)(V OL = 1.5 Vdc)I OL5.010150.641.64.2ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ1.02.02.5——————————4.08.012.5– 1.0– 0.2– 0.5– 1.52.254.506.752.755.508.25– 1.7– 0.36– 0.9– 3.51.02.02.5——————————4.08.012.5– 0.7– 0.14– 0.35– 1.1ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput Current ÎÎÎÎ I in 15 ÎÎÎ — ÎÎÎ — ÎÎÎÎ — ÎÎÎÎÎεAdcÎÎÎΗ ÎÎΗ ÎÎΗ ÎÎÎΗ ÎÎÎΗ ÎÎΗ ÎÎÎpFInput Capacitance(V in = 0)C in———0.511.33.40.882.258.8———0.360.92.40.050.050.05———1.02.02.5——————————VdcVdcVdcVdcmAdcmAdc± 0.1 ÎÎÎÎ ±0.00001 ÎÎÎ ± 0.1 ÎÎÎ ± 1.0 ÎÎÎÎÎÎ5.0 7.5 ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎQuiescent Current(Per Package)I DD5.01015———ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTotal Supply Current (4.) (5.)(Dynamic plus Quiescent,Per Gate C L = 50 pF)I T5.01015ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ0.250.51.0———0.00050.00100.0015ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ0.250.51.0I T = (0.3 µA/kHz) f + I DD /NI T = (0.6 µA/kHz) f + I DD /NI T = (0.8 µA/kHz) f + I DD /N3. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.4. The formulas given are for the typical characteristics only at 25 C.5. To calculate total supply current at loads other than 50 pF:I T (C L ) = I T (50 pF) + (C L – 50) Vfk———7.51530µAdcµAdcwhere: I T is in µH (per package), C L in pF, V = (V DD – V SS ) in volts, f in kHz is input frequency, and k = 0.001 x the number of exercised gatesper package.http://onsemi.com42

MC14001UB, MC14011UBSWITCHING CHARACTERISTICS (6.) (C L = 50 pF, T A = 25 C)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCharacteristicÎÎÎÎSymbolMin Typ (7.) ÎÎÎMaxÎÎÎÎUnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Rise Timet TLH = (3.0 ns/pF) C L + 30 nst TLH = (1.5 ns/pF) C L + 15 nst TLH = (1.1 ns/pF) C L + 10 nst TLHÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Fall Timet THL = (1.5 ns/pF) C L + 25 nst THL = (0.75 ns/pF) C L + 12.5 nst THL = (0.55 ns/pF) C L + 9.5 nst THLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPropagation Delay Timet PLH , t PHL = (1.7 ns/pF) C L + 30 nst PLH , t PHL = (0.66 ns/pF) C L + 22 nst PLH , t PHL = (0.50 ns/pF) C L + 15 nst PLH , t PHLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ6. The formulas given are for the typical characteristics only at 25 C.7. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎV DDVdc5.010155.010155.01015—————————180906510050409050403601801302001008018010080nsnsnsPULSEGENERATORINPUTV DD147 V SS*All unused inputs of AND, NAND gates must beconnected to V DD .All unused inputs of OR, NOR gates must beconnected to V SS .*OUTPUTC LFigure 1. Switching Time Test Circuit and Waveforms20 ns 20 nsINPUTt PHLOUTPUTINVERTINGV90%DD50%10%0 Vt PLH90%V OH50%10%V OLt THL t TLHhttp://onsemi.com43

MC14001UB, MC14011UBMC14001UB CIRCUIT SCHEMATICMC14011UB CIRCUIT SCHEMATIC(1/4 of Device Shown)3V DD14 1014 V DD3, 4, 10, 1118291, 6, 8, 132, 5, 9, 126137 V SS5124 7 11V SSVout , OUTPUT VOLTAGE (Vdc)1614V DD = 15 Vdc T A = + 25°CUnused inputconnected to12V SS .1010 Vdc a One input onlyb Both inputs8.08.0b a6.06.05.0 Vdc15 Vdc4.0 b a4.0b a10 Vdc2.02.00 00 2.0 4.0 6.0 8.0 10 12 14 16ID, DRAIN CURRENT (mAdc)Vout , OUTPUT VOLTAGE (Vdc)161412108.06.04.02.010 Vdc5.0 VdcaV DD = 15 Vdc Unused inputconnected toba V SS .baba T A = + 125°Cb T A = – 55°C00 2.0 4.0 6.0 8.0 10 12 14 16V in , INPUT VOLTAGE (Vdc)Figure 2. Typical Voltage andCurrent Transfer CharacteristicsV in , INPUT VOLTAGE (Vdc)Figure 3. Typical Voltage TransferCharacteristics versusTemperatureID, DRAIN CURRENT (mAdc)0– 2.0– 4.0– 6.0– 8.0abcT A = – 55°CT A = + 25°CT A = + 125°CV GS = – 5.0 Vdc– 10 Vdccba a–10– 10 – 8.0 – 6.0 – 4.0 – 2.0 0V DS , DRAIN VOLTAGE (Vdc)cbacb– 15 VdcID, DRAIN CURRENT (mAdc)108.06.04.02.0ab cbac15 VdcacV GS = 10 Vdc00V DS , DRAIN VOLTAGE (Vdc)2.0 4.0 6.0 8.0 10babc5.0 VdcT A = – 55°CT A = + 25°CT A = + 125°CFigure 4. Typical Output SourceCharacteristicsFigure 5. Typical Output SinkCharacteristicshttp://onsemi.com44

The MC14007UB multi–purpose device consists of threeN–channel and three P–channel enhancement mode devices packagedto provide access to each device. These versatile parts are useful ininverter circuits, pulse–shapers, linear amplifiers, high inputimpedance amplifiers, threshold detectors, transmission gating, andfunctional gating.• Diode Protection on All Inputs• Supply Voltage Range = 3.0 Vdc to 18 Vdc• Capable of Driving Two Low–power TTL Loads or One Low–powerSchottky TTL Load Over the Rated Temperature Range• Pin–for–Pin Replacement for CD4007A or CD4007UB• This device has 2 outputs without ESD Protection. Anti–staticprecautions must be taken.MAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 2.)Symbol Parameter Value UnitV DD DC Supply Voltage Range –0.5 to +18.0 VV in , V out Input or Output Voltage Range(DC or Transient)–0.5 to V DD + 0.5 VI in , I outP DInput or Output Current(DC or Transient) per PinPower Dissipation,per Package (Note 3.)±10 mA500 mWT A Ambient Temperature Range –55 to +125 °CT stg Storage Temperature Range –65 to +150 °CT LLead Temperature(8–Second Soldering)260 °C2. Maximum Ratings are those values beyond which damage to the devicemay occur.3. Temperature Derating:Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 CThis device contains protection circuitry to guard against damage due to highstatic voltages or electric fields. However, precautions must be taken to avoidapplications of any voltage higher than maximum rated voltages to thishigh–impedance circuit. For proper operation, V in and V out should be constrainedto the range V SS (V in or V out ) V DD .Unused inputs must always be tied to an appropriate logic voltage level (e.g.,either V SS or V DD ). Unused outputs must be left open.http://onsemi.comA = Assembly LocationWL or L = Wafer LotYY or Y = YearWW or W = Work WeekORDERING INFORMATIONDevice Package ShippingMC14007UBCP PDIP–14 2000/BoxMC14007UBD SOIC–14 55/RailMC14007UBDR2 SOIC–14 2500/Tape & ReelMC14007UBDTMC14007UBFPDIP–14P SUFFIXCASE 646SOIC–14D SUFFIXCASE 751ATSSOP–14DT SUFFIXCASE 948GSOEIAJ–14F SUFFIXCASE 965TSSOP–14SOEIAJ–14MARKINGDIAGRAMS14MC14007UBCPAWLYYWW114114114007UAWLYWW14114007UALYWMC14007UAWLYWW96/RailSee Note 1.MC14007UBFEL SOEIAJ–14 See Note 1.1. For ordering information on the EIAJ version ofthe SOIC packages, please contact your localON Semiconductor representative.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 345 Publication Order Number:MC14007UB/D

MC14007UBPIN ASSIGNMENTD–P B 1 14 V DDS–P B 2 13 D–P AGATE B 3 12 OUT CS–N B 4 11 S–P CD–N B 5 10 GATE CGATE AV SS6798D = DRAINS = SOURCES–N CD–N ASCHEMATIC14 13 2 1 116127 8 3 4 5 10 9V DD = PIN 14V SS = PIN 7AAB1291BC32INPUTV DD1454C11INPUT10OUTPUT CONDITIONA = C, B = OPENA = B, C = OPENINPUT613810Substrates of P–channel devices internallyconnected to V DD ; substrates of N–channeldevices internally connected to V SS .7 V SSFigure 1. Typical Application: 2–Input Analog Multiplexerhttp://onsemi.com46

MC14007UBELECTRICAL CHARACTERISTICS (Voltages Referenced to V SS )ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΖ 55 C 25 C DDCharacteristicOutput VoltageV in = V DD or 0“0” LevelV DDÎÎÎ ÎÎÎSymbol VdcV OL 5.0 —10 —15 —125 ÎÎÎCÎÎÎMin UnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMinÎÎÎÎÎÎ MaxÎÎÎÎÎÎÎÎÎMaxÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎV in = 0 or V DDLevelÎÎÎΓ1” V OH 5.010154.959.9514.95ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput Voltage(V O = 4.5 Vdc)(V O = 9.0 Vdc)(V O = 13.5 Vdc)“0” LevelV ILÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5.01015———0.050.050.05———Min———4.959.9514.95Typ (4.)0005.01015Max0.050.050.05——————4.959.9514.95ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V O = 0.5 Vdc) “1” Level(V O = 1.0 Vdc)(V O = 1.5 Vdc)V IH5.010154.08.012.5ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ1.02.02.5——————4.08.012.52.254.506.752.755.508.251.02.02.5——————4.08.012.50.050.050.05———1.02.02.5———VdcVdcVdcVdcOutput Drive Current(V OH = 2.5 Vdc) Source(V OH = 4.6 Vdc)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V OH = 9.5 Vdc)(V OH = 13.5 Vdc)I OH5.05.01015– 3.0– 0.64– 1.6– 4.2————– 2.4– 0.51– 1.3– 3.4– 5.0– 1.0– 2.5– 10————– 1.7– 0.36– 0.9– 2.4————mAdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V OL = 0.4 Vdc) Sink(V OL = 0.5 Vdc)(V OL = 1.5 Vdc)I OL5.010150.641.64.2ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎInput Current ÎÎÎÎ I in ÎÎÎ15 ÎÎΗ 0.1ÎÎÎα ÎÎÎΗ ÎÎΗ 1.0ÎÎα ÎÎεAdc— ÎÎΗ ÎÎΗ ÎÎÎÎ — ÎÎΗ ÎÎÎpFInput Capacitance(V in = 0)C in———0.511.33.41.02.510———0.360.92.4ÎÎα0.00001 ± ÎÎÎ0.1ÎÎÎ5.0 ÎÎÎ7.5———mAdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎQuiescent Current(Per Package)I DD5.01015———ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTotal Supply Current (5.) (6.)(Dynamic plus Quiescent,Per Gate) (C L = 50 pF)I T5.01015ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ0.250.51.0———0.00050.00100.0015ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ0.250.51.0I T = (0.7 µA/kHz) f + I DD /6I T = (1.4 µA/kHz) f + I DD /6I T = (2.2 µA/kHz) f + I DD /64. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.5. The formulas given are for the typical characteristics only at 25 C.6. To calculate total supply current at loads other than 50 pF:I T (C L ) = I T (50 pF) + (C L – 50) Vfkwhere: I T is in µA (per package), C L in pF, V = (V DD – V SS ) in volts, f in kHz is input frequency, and k = 0.003.———7.51530µAdcµAdcÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΗÎÎÎÎhttp://onsemi.com47

MC14007UBSWITCHING CHARACTERISTICS (7.) (C L = 50 pF, T A = 25 C)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCharacteristicÎÎÎÎSymbolMin Typ (8.) ÎÎÎMaxÎÎÎÎUnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Rise Timet TLH = (1.2 ns/pF) C L + 30 nst TLH = (0.5 ns/pF) C L + 20 nst TLH = (0.4 ns/pF) C L + 15 nst TLHÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Fall Timet THL = (1.2 ns/pF) C L + 15 nst THL = (0.5 ns/pF) C L + 15 nsÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎt THL = (0.4 ns/pF) C L + 10 nst THLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTurn–Off Delay Timet PLH = (1.5 ns/pF) C L + 35 nst PLH = (0.2 ns/pF) C L + 20 nst PLH = (0.15 ns/pF) C L + 17.5 nst PLHÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTurn–On Delay Timet PHL = (1.0 ns/pF) C L + 10 nst PHL = (0.3 ns/pF) C L + 15 nst PHL = (0.2 ns/pF) C L + 15 nst PHLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ7. The formulas given are for the typical characteristics only. Switching specifications are for device connected as an inverter.8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎV DDVdc5.010155.010155.010155.01015————————————9045357540306030256030251809070150806012575551257555nsnsnsnsV DD = – V GSV DD = V GS714V SSI OHV DS = V OH – V DD714V SSI OLV DS = V OLAll unused inputs connected to ground.All unused inputs connected to ground.IOH, DRAIN CURRENT (mAdc)0– 4.0– 8.0–12–16abcT A = – 55°CT A = + 25°CT A = + 125°CV GS = – 5.0 Vdc–20– 10 – 8.0 – 6.0 – 4.0 – 2.0 – 0V DS , DRAIN VOLTAGE (Vdc)cbacbbc– 10 Vdc a – 15 VdcaIOL , DRAIN CURRENT (mAdc)2016128.04.0ababccV GS = 15 Vdc10 Vdcac00 2.0 4.0 6.0 8.0 10V DS , DRAIN VOLTAGE (Vdc)b5.0 VdcabcT A = – 55°CT A = + 25°CT A = + 125°CFigure 2. Typical Output Source CharacteristicsFigure 3. Typical Output Sink CharacteristicsThese typical curves are not guarantees, but are design aids.Caution: The maximum current rating is 10 mA per pin.http://onsemi.com48

MC14007UB500 µFPULSEGENERATORV DD20 ns 20 ns0.01 µF90%I D CERAMICV in 50%10%14t PHLt PLHV inV 90%outV out50%7 V C SSL10%V DDV SSV OHV OLt THLt TLHFigure 4. Switching Time and Power Dissipation Test Circuit and WaveformsAPPLICATIONSThe MC14007UB dual pair plus inverter, which hasaccess to all its elements offers a number of unique circuitapplications. Figures 1, 5, and 6 are a few examples of thedevice flexibility.DISABLE 3+V DD211110BV DD141311128OUT = A+B•C21OUTPUTINPUT 10DISABLE 698712 OUTPUTINPUT DISABLE OUTPUT10XX = Don’t Care00101OPEN3C6A954Substrates of P–channel devices internally connected to V DD ;Substrates of N–channel devices internally connected to V SS .Figure 6. AOI Functions Using Tree Logic7Figure 5. 3–State Bufferhttp://onsemi.com49

The MC14008B 4–bit full adder is constructed with MOSP–channel and N–channel enhancement mode devices in a singlemonolithic structure. This device consists of four full adders with fastinternal look–ahead carry output. It is useful in binary addition andother arithmetic applications. The fast parallel carry output bit allowshigh–speed operation when used with other adders in a system.• Look–Ahead Carry Output• Diode Protection on All Inputs• All Outputs Buffered• Supply Voltage Range = 3.0 Vdc to 18 Vdc• Capable of Driving Two Low–power TTL Loads or One Low–powerSchottky TTL Load Over the Rated Temperature Range• Pin–for–Pin Replacement for CD4008BMAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 2.)Symbol Parameter Value UnitV DD DC Supply Voltage Range –0.5 to +18.0 VV in , V out Input or Output Voltage Range(DC or Transient)–0.5 to V DD + 0.5 VI in , I outP DInput or Output Current(DC or Transient) per PinPower Dissipation,per Package (Note 3.)±10 mA500 mWT A Ambient Temperature Range –55 to +125 °CT stg Storage Temperature Range –65 to +150 °CT LLead Temperature(8–Second Soldering)260 °C2. Maximum Ratings are those values beyond which damage to the devicemay occur.3. Temperature Derating:Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 CThis device contains protection circuitry to guard against damage due to highstatic voltages or electric fields. However, precautions must be taken to avoidapplications of any voltage higher than maximum rated voltages to thishigh–impedance circuit. For proper operation, V in and V out should be constrainedto the range V SS (V in or V out ) V DD .Unused inputs must always be tied to an appropriate logic voltage level (e.g.,either V SS or V DD ). Unused outputs must be left open.http://onsemi.comPDIP–16P SUFFIXCASE 648SOIC–16D SUFFIXCASE 751BSOEIAJ–16F SUFFIXCASE 966A = Assembly LocationWL or L = Wafer LotYY or Y = YearWW or W = Work WeekORDERING INFORMATIONMARKINGDIAGRAMSDevice Package ShippingMC14008BCP PDIP–16 2000/BoxMC14008BDR2 SOIC–16 2500/Tape & ReelMC14008BF SOEIAJ–16 See Note 1.1. For ordering information on the EIAJ version ofthe SOIC packages, please contact your localON Semiconductor representative.161161161MC14008BCPAWLYYWW14008BAWLYWWMC14008BAWLYWW© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 350 Publication Order Number:MC14008B/D

MC14008BTRUTH TABLE(One Stage)C in B A C out S0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1PIN ASSIGNMENTA4116V DDB3215B4A3314C outB2413S4A2512S3B1611S2A1710S1V SS89C inBLOCK DIAGRAMHIGH–SPEEDPARALLEL CARRY14 C outB4 15A4 1B3 2A3 3B2 4A2 5B1 6A1 7C in 9ADDER4C4ADDER3C3ADDER2C2ADDER113 S412 S311 S210 S1V DD = PIN 16V SS = PIN 8http://onsemi.com51

MC14008BELECTRICAL CHARACTERISTICS (Voltages Referenced to V SS )ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΖ 55 C 25 C 125 C V DDÎÎÎÎÎÎÎÎÎÎCharacteristic ÎÎÎÎÎÎÎMinÎÎÎMaxÎÎÎÎ MinÎÎÎÎÎTyp (4.) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎMaxMaxÎÎÎUnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput VoltageV in = V DD or 0V in = 0 or V DD“0” LevelÎÎÎ ÎÎÎSymbol VdcV OL 5.0 —10 —15 —LevelÎÎÎΓ1” V OH 5.010154.959.9514.95ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput Voltage(V O = 4.5 or 0.5 Vdc)(V O = 9.0 or 1.0 Vdc)(V O = 13.5 or 1.5 Vdc)“0” LevelV IL0.050.050.05———0000.050.050.05ÎÎÎMin— 0.05 Vdc— 0.05— 0.05ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5.01015——————4.959.9514.955.01015———4.959.9514.95ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V O = 0.5 or 4.5 Vdc) “1” Level(V O = 1.0 or 9.0 Vdc)(V O = 1.5 or 13.5 Vdc)V IH5.010153.57.011ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ1.53.04.0——————3.57.0112.254.506.752.755.508.251.53.04.0——————3.57.011———1.53.04.0———VdcVdcVdcOutput Drive Current(V OH = 2.5 Vdc) Source(V OH = 4.6 Vdc)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V OH = 9.5 Vdc)(V OH = 13.5 Vdc)I OH5.05.01015– 3.0– 0.64– 1.6– 4.2————– 2.4– 0.51– 1.3– 3.4– 4.2– 0.88– 2.25– 8.8————– 1.7– 0.36– 0.9– 2.4————mAdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V OL = 0.4 Vdc) Sink(V OL = 0.5 Vdc)(V OL = 1.5 Vdc)I OL5.010150.641.64.2ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput Current ÎÎÎÎ I in ÎÎÎ15 ÎÎΗ 0.1ÎÎÎα ÎÎΗ ÎÎΗ 1.0ÎÎα ÎÎεAdc— ÎÎÎΗ ÎÎΗ ÎÎÎ5.0 ÎÎΗ ÎÎΗ ÎÎÎpFInput Capacitance(V in = 0)C in———0.511.33.40.882.258.8———0.360.92.4± 0.1 ÎÎα0.00001ÎÎÎÎÎÎÎ7.5———mAdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎQuiescent Current(Per Package)I DD5.01015———ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTotal Supply Current (5.) (6.)(Dynamic plus Quiescent,Per Package)(C L = 50 pF on all outputs, allbuffers switching)I T5.01015ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5.01020———0.0050.0100.0155.01020I T = (1.7 µA/kHz) f + I DDI T = (3.4 µA/kHz) f + I DDI T = (5.0 µA/kHz) f + I DD4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.5. The formulas given are for the typical characteristics only at 25 C.6. To calculate total supply current at loads other than 50 pF:I T (C L ) = I T (50 pF) + (C L – 50) Vfkwhere: I T is in µA (per package), C L in pF, V = (V DD – V SS ) in volts, f in kHz is input frequency, and k = 0.005.———150300600µAdcµAdcÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΗÎÎÎÎhttp://onsemi.com52

MC14008BSWITCHING CHARACTERISTICS (7.) (C L = 50 pF, T A = 25 C)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCharacteristicÎÎÎÎSymbolMin Typ (8.) ÎÎÎMaxÎÎÎÎUnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Rise and Fall Timet TLH , t THL = (1.5 ns/pF) C L + 25 nst TLH , t THL = (0.75 ns/pF) C L + 12.5 nst TLH , t THL = (0.55 ns/pF) C L + 9.5 nst TLH ,t THLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPropagation Delay TimeSum in to Sum OutÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎt PLH , t PHL = (1.7 ns/pF) C L + 315 nst PLH , t PHL = (0.66 ns/pF) C L + 127 nst PLH , t PHL = (0.5 ns/pF) C L + 90 nsSum In to Carry Outt PLH , t PHL = (1.7 ns/pF) C L + 220 nst PLH , t PHL = (0.66 ns/pF) C L + 112 nst PLH , t PHL = (0.5 ns/pF) C L + 85 nsCarry In to Sum OutÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎt PLH , t PHL = (1.7 ns/pF) C L + 290 nst PLH , t PHL = (0.66 ns/pF) C L + 122 nst PLH , t PHL = (0.5 ns/pF) C L + 90 nsCarry In to Carry Outt PLH , t PHL = (1.7 ns/pF) C L + 85 nst PLH , t PHL = (0.66 ns/pF) C L + 42 nst PLH , t PHL = (0.5 ns/pF) C L + 30 nst PLH , t PHLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ7. The formulas given are for the typical characteristics only at 25 C.8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎV DDVdc5.010155.010155.010155.010155.01015———————————————1005040400160115305145110375155115170755520010080800320230610290220750310230340150110nsnsV DD = – V GSV outV DD = V GSV out1616B4 S4A4B3 S3A3B2 S2A2B1 S1I OHA1C in C out8 V SSEXTERNALPOWERSUPPLYB4A4B3A3B2A2B1A1C inS4S3S2S1C out8 V SSI OLEXTERNALPOWERSUPPLYFigure 1. Typical Source CurrentCharacteristics Test CircuitFigure 2. Typical Sink CurrentCharacteristics Test Circuithttp://onsemi.com53

MC14008BV DD1620 ns 20 nsV in90%10%V DDV SSPULSEGENERATORB4 S4A4B3 S3A3B2 S2A2CB1 S1LCA1LCC in C L outC LC8 V L SS500 µFI DDFigure 3. Dynamic Power Dissipation Test Circuit and WaveformV DD16PULSEGENERATORB4 S4A4B3 S3A3B2 S2A2B1 S1C LA1C LCC in C L outC L8 VC L SSI DD20 ns 20 nsC inS1 – S4C out90%50%10%50%t PHL90%50%10%t PLHt THLV DDV SSt PLHV OHV OLt TLHV OHV OLt PHLFigure 4. Switching Time Test Circuit and Waveformshttp://onsemi.com54

MC14008BC outB4A4S4B3A3S3B2A2S2B1A1S1C inFigure 5. Logic DiagramTYPICAL APPLICATIONWORD A + B INPUTSA1 B4 A1 B4 A1 B4 A1 B4CHIPCHIPCHIPCHIPC in C out C in C out C in C out C inC1234 outS1 S4 S1 S4 S1 S4 S1 S4SUM OUTPUTSCalculation of 16–bit adder speed:t P total = t P (Sum to Carry) + t P (Carry to Sum) + 2 t P (Carry to Carry)The guaranteed 16–bit adder speed at 10 V, 25°C, C L = 50 pF is:t p total = 290 + 310 + 300 = 900 nsFigure 6. Using the MC14008B in a 16–Bit Adder Configurationhttp://onsemi.com55

The MC14013B dual type D flip–flop is constructed with MOSP–channel and N–channel enhancement mode devices in a singlemonolithic structure. Each flip–flop has independent Data, (D), DirectSet, (S), Direct Reset, (R), and Clock (C) inputs and complementaryoutputs (Q and Q). These devices may be used as shift registerelements or as type T flip–flops for counter and toggle applications.• Static Operation• Diode Protection on All Inputs• Supply Voltage Range = 3.0 Vdc to 18 Vdc• Logic Edge–Clocked Flip–Flop DesignLogic state is retained indefinitely with clock level either high or low;information is transferred to the output only on the positive–goingedge of the clock pulse• Capable of Driving Two Low–power TTL Loads or One Low–powerSchottky TTL Load Over the Rated Temperature Range• Pin–for–Pin Replacement for CD4013Bhttp://onsemi.comPDIP–14P SUFFIXCASE 646SOIC–14D SUFFIXCASE 751AMARKINGDIAGRAMS141141MC14013BCPAWLYYWW14013BAWLYWW14MAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 2.)Symbol Parameter Value UnitV DD DC Supply Voltage Range –0.5 to +18.0 VV in , V out Input or Output Voltage Range(DC or Transient)–0.5 to V DD + 0.5 VI in , I outP DInput or Output Current(DC or Transient) per PinPower Dissipation,per Package (Note 3.)±10 mA500 mWT A Ambient Temperature Range –55 to +125 °CT stg Storage Temperature Range –65 to +150 °CT LLead Temperature(8–Second Soldering)260 °C2. Maximum Ratings are those values beyond which damage to the devicemay occur.3. Temperature Derating:Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 CThis device contains protection circuitry to guard against damage due to highstatic voltages or electric fields. However, precautions must be taken to avoidapplications of any voltage higher than maximum rated voltages to thishigh–impedance circuit. For proper operation, V in and V out should be constrainedto the range V SS (V in or V out ) V DD .Unused inputs must always be tied to an appropriate logic voltage level (e.g.,either V SS or V DD ). Unused outputs must be left open.A = Assembly LocationWL or L = Wafer LotYY or Y = YearWW or W = Work WeekORDERING INFORMATIONDevice Package ShippingMC14013BCP PDIP–14 2000/BoxMC14013BD SOIC–14 55/RailMC14013BDR2 SOIC–14 2500/Tape & ReelMC14013BDTMC14013BFTSSOP–14DT SUFFIXCASE 948GSOEIAJ–14F SUFFIXCASE 965TSSOP–14SOEIAJ–14141114013BALYWMC14013BAWLYWW96/RailMC14013BDTR2 TSSOP–14 2500/Tape & ReelSee Note 1.MC14013BFEL SOEIAJ–14 See Note 1.1. For ordering information on the EIAJ version ofthe SOIC packages, please contact your localON Semiconductor representative.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 356 Publication Order Number:MC14013B/D

MC14013BTRUTH TABLEInputsOutputsClock † Data Reset Set Q Q0 0 0 0 11 0 0 1 0X 0 0 Q QX X 1 0 0 1X X 0 1 1 0X X 1 1 1 1X = Don’t Care† = Level ChangeNoChangePIN ASSIGNMENTQ A114V DDQ A213Q BC A312Q BR A411C BD A510R BS A69D BV SS78S BBLOCK DIAGRAM65DSQ13CRQ2489DSQ1311CRQ1210V DD = PIN 14V SS = PIN 7http://onsemi.com57

MC14013BELECTRICAL CHARACTERISTICS (Voltages Referenced to V SS )ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΖ 55 C 25 C 125 C V DDÎÎÎÎÎÎÎÎÎÎCharacteristic ÎÎÎÎÎÎÎMinÎÎÎMaxÎÎÎÎ MinÎÎÎÎÎTyp (4.) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎMaxMaxÎÎÎUnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput VoltageV in = V DD or 0V in = 0 or V DD“0” LevelÎÎÎ ÎÎÎSymbol VdcV OL 5.0 —10 —15 —LevelÎÎÎΓ1” V OH 5.010154.959.9514.95ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput Voltage(V O = 4.5 or 0.5 Vdc)(V O = 9.0 or 1.0 Vdc)(V O = 13.5 or 1.5 Vdc)“0” LevelV IL0.050.050.05———0000.050.050.05ÎÎÎMin— 0.05 Vdc— 0.05— 0.05ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5.01015——————4.959.9514.955.01015———4.959.9514.95ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V O = 0.5 or 4.5 Vdc) “1” Level(V O = 1.0 or 9.0 Vdc)(V O = 1.5 or 13.5 Vdc)V IH5.010153.57.011ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ1.53.04.0——————3.57.0112.254.506.752.755.508.251.53.04.0——————3.57.011———1.53.04.0———VdcVdcVdcOutput Drive Current(V OH = 2.5 Vdc) Source(V OH = 4.6 Vdc)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V OH = 9.5 Vdc)(V OH = 13.5 Vdc)I OH5.05.01015– 3.0– 0.64– 1.6– 4.2————– 2.4– 0.51– 1.3– 3.4– 4.2– 0.88– 2.25– 8.8————– 1.7– 0.36– 0.9– 2.4————mAdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V OL = 0.4 Vdc) Sink(V OL = 0.5 Vdc)(V OL = 1.5 Vdc)I OL5.010150.641.64.2ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput Current ÎÎÎÎ I in ÎÎÎ15 ÎÎΗ 0.1ÎÎÎα ÎÎΗ ÎÎΗ 1.0ÎÎα ÎÎεAdc— ÎÎÎΗ ÎÎΗ ÎÎÎ5.0 ÎÎΗ ÎÎΗ ÎÎÎpFInput Capacitance(V in = 0)C in———0.511.33.40.882.258.8———0.360.92.4± 0.1 ÎÎα0.00001ÎÎÎÎÎÎÎ7.5———mAdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎQuiescent Current(Per Package)I DD5.01015———ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTotal Supply Current (5.) (6.)(Dynamic plus Quiescent,Per Package)(C L = 50 pF on all outputs, allbuffers switching)I T5.01015ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ1.02.04.0———0.0020.0040.0061.02.04.0I T = (0.75 µA/kHz) f + I DDI T = (1.5 µA/kHz) f + I DDI T = (2.3 µA/kHz) f + I DD4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.5. The formulas given are for the typical characteristics only at 25 C.6. To calculate total supply current at loads other than 50 pF:I T (C L ) = I T (50 pF) + (C L – 50) Vfkwhere: I T is in µA (per package), C L in pF, V = (V DD – V SS ) in volts, f in kHz is input frequency, and k = 0.002.———3060120µAdcµAdcÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΗÎÎÎÎhttp://onsemi.com58

SWITCHING CHARACTERISTICS (7.) (C L = 50 pF, T A = 25 C)MC14013BÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCharacteristicSymbolMinTyp (8.) MaxUnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Rise and Fall Timet TLH , t THL = (1.5 ns/pF) C L + 25 nst TLH , t THL = (0.75 ns/pF) C L + 12.5 nst TLH , t THL = (0.55 ns/pF) C L + 9.5 nsPropagation Delay TimeClock to Q, Qt PLH , t PHL = (1.7 ns/pF) C L + 90 nst PLH , t PHL = (0.66 ns/pF) C L + 42 nst PLH , t PHL = (0.5 ns/pF) C L + 25 nst TLH ,t THLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎt PLHt PHLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSet to Q, Qt PLH , t PHL = (1.7 ns/pF) C L + 90 nst PLH , t PHL = (0.66 ns/pF) C L + 42 nst PLH , t PHL = (0.5 ns/pF) C L + 25 nsÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎReset to Q, Qt PLH , t PHL = (1.7 ns/pF) C L + 265 nst PLH , t PHL = (0.66 ns/pF) C L + 67 nst PLH , t PHL = (0.5 ns/pF) C L + 50 nsSetup Times (9.)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎt suÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎHold Times (9.)t hÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎClock Pulse Widtht WL , t WHÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎClock Pulse Frequencyf clÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎClock Pulse Rise and Fall Timet TLHt THLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSet and Reset Pulse Widtht WL , t WHÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎRemoval TimesSett remÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎResetÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎV DD5.010155.010155.010155.010155.010155.010155.010155.010155.010155.010155101551015————————————40201540201525010070——————250100708045355030251005040175755017575502251007520107.520107.512550354.01014———1255035055– 35– 10– 57. The formulas given are for the typical characteristics only at 25 C.8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.9. Data must be valid for 250 ns with a 5 V supply, 100 ns with 10 V, and 70 ns with 15 V.20010080350150100350150100450200150—————————2.05.07.0155.04.0—————————nsnsnsnsnsMHzµsnsnsSCLOGIC DIAGRAM (1/2 of Device Shown)CQDCCCCQCCCCCRhttp://onsemi.com59

MC14013B20 ns 20 nsDt su (H)CQt WH90%50%10%t PLH90%50%10%20 ns 20 nstV SSsu (L)t20 ns90%hVSET OR90%DD50%RESET10%t wt remV SS20 ns 20 nst WL90%1CLOCK50%10%f cl50%10%V DDt TLH t THLt PHLV OHV OLQ OR Qt PLHt PHL50%t wV DDV SSV DDV SSV OHV OLInputs R and S low.Figure 1. Dynamic Signal Waveforms(Data, Clock, and Output)Figure 2. Dynamic Signal Waveforms(Set, Reset, Clock, and Output)TYPICAL APPLICATIONSn–STAGE SHIFT REGISTER12n thDDQDQDQQCQCQCQCLOCKBINARY RIPPLE UP–COUNTER (Divide–by–2 n )12n thDQDQDQQCLOCKCQCQCQT FLIP–FLOPMODIFIED RING COUNTER (Divide–by–(n+1))12n thDQDQDQQCQCQCQCLOCKhttp://onsemi.com60

The MC14014B and MC14021B 8–bit static shift registers areconstructed with MOS P–channel and N–channel enhancement modedevices in a single monolithic structure. These shift registers findprimary use in parallel–to–serial data conversion, synchronous andasynchronous parallel input, serial output data queueing; and othergeneral purpose register applications requiring low power and/or highnoise immunity.• Synchronous Parallel Input/Serial Output (MC14014B)• Asynchronous Parallel Input/Serial Output (MC14021B)• Synchronous Serial Input/Serial Output• Full Static Operation• “Q” Outputs from Sixth, Seventh, and Eighth Stages• Double Diode Input Protection• Supply Voltage Range = 3.0 Vdc to 18 Vdc• Capable of Driving Two Low–power TTL Loads or One Low–powerSchottky TTL Load Over the Rated Temperature Range• MC14014B Pin–for–Pin Replacement for CD4014B• MC14021B Pin–for–Pin Replacement for CD4021BMAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 2.)Symbol Parameter Value UnitV DD DC Supply Voltage Range –0.5 to +18.0 VV in , V out Input or Output Voltage Range(DC or Transient)–0.5 to V DD + 0.5 VI in , I outP DInput or Output Current(DC or Transient) per PinPower Dissipation,per Package (Note 3.)±10 mA500 mWT A Ambient Temperature Range –55 to +125 °CT stg Storage Temperature Range –65 to +150 °CT LLead Temperature(8–Second Soldering)260 °C2. Maximum Ratings are those values beyond which damage to the devicemay occur.3. Temperature Derating:Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 CThis device contains protection circuitry to guard against damage due to highstatic voltages or electric fields. However, precautions must be taken to avoidapplications of any voltage higher than maximum rated voltages to thishigh–impedance circuit. For proper operation, V in and V out should be constrainedto the range V SS (V in or V out ) V DD .Unused inputs must always be tied to an appropriate logic voltage level (e.g.,either V SS or V DD ). Unused outputs must be left open.http://onsemi.comPDIP–16P SUFFIXCASE 648SOIC–16D SUFFIXCASE 751BSOEIAJ–16F SUFFIXCASE 966XX = Specific Device CodeA = Assembly LocationWL or L = Wafer LotYY or Y = YearWW or W = Work WeekORDERING INFORMATIONMARKINGDIAGRAMS16Device Package ShippingMC14014BCP PDIP–16 2000/BoxMC14014BD SOIC–16 48/RailMC14014BDR2 SOIC–16 2500/Tape & Reel1. For ordering information on the EIAJ version ofthe SOIC packages, please contact your localON Semiconductor representative.1161161MC140XXBCPAWLYYWW140XXBAWLYWWMC140XXBAWLYWWMC14014BF SOEIAJ–16 See Note 1.MC14014BFEL SOEIAJ–16 See Note 1.MC14021BCP PDIP–16 2000/BoxMC14021BD SOIC–16 48/RailMC14021BDR2 SOIC–16 2500/Tape & ReelMC14021BF SOEIAJ–16 See Note 1.MC14021BFEL SOEIAJ–16 See Note 1.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 361 Publication Order Number:MC14014B/D

MC14014B, MC14021BTRUTH TABLESERIAL OPERATION:Q6 Q7 Q8t Clock D S P/S t=n+6 t=n+7 t=n+8n 0 0 0 ? ?n+1 1 0 1 0 ?n+2 0 0 0 1 0n+3 1 0 1 0 1X 0 Q6 Q7 Q8PARALLEL OPERATION:ClockMC14014B MC14021B D S P/S P n *Q nX X 1 0 0X X 1 1 1*Q6, Q7, & Q8 are available externallyX = Don’t CarePIN ASSIGNMENTP8116V DDQ6215P7Q8314P6P4413P5P3512Q7P2611D SP1710CV SS89P/SP/S9LOGIC DIAGRAMP1 P2 P3 P6 P7 P87 6 5 14 15 1D S11DQDQDQDQDQDCCCCQ C Q C Q10CLOCKV DD = PIN 16V SS = PIN 8P4 = PIN 4P5 = PIN 132 12 3Q6 Q7 Q8http://onsemi.com62

MC14014B, MC14021BELECTRICAL CHARACTERISTICS (Voltages Referenced to V SS )ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΖ 55 C 25 C 125 C V DDÎÎÎÎÎÎÎÎÎÎCharacteristic ÎÎÎÎÎÎÎMinÎÎÎMaxÎÎÎÎ MinÎÎÎÎÎTyp (4.) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎMaxMaxÎÎÎUnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput VoltageV in = V DD or 0V in = 0 or V DD“0” LevelÎÎÎ ÎÎÎSymbol VdcV OL 5.0 —10 —15 —LevelÎÎÎΓ1” V OH 5.010154.959.9514.95ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput Voltage(V O = 4.5 or 0.5 Vdc)(V O = 9.0 or 1.0 Vdc)(V O = 13.5 or 1.5 Vdc)“0” LevelV IL0.050.050.05———0000.050.050.05ÎÎÎMin— 0.05 Vdc— 0.05— 0.05ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5.01015——————4.959.9514.955.01015———4.959.9514.95ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V O = 0.5 or 4.5 Vdc) “1” Level(V O = 1.0 or 9.0 Vdc)(V O = 1.5 or 13.5 Vdc)V IH5.010153.57.011ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ1.53.04.0——————3.57.0112.254.506.752.755.508.251.53.04.0——————3.57.011———1.53.04.0———VdcVdcVdcOutput Drive Current(V OH = 2.5 Vdc) Source(V OH = 4.6 Vdc)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V OH = 9.5 Vdc)(V OH = 13.5 Vdc)I OH5.05.01015– 3.0– 0.64– 1.6– 4.2————– 2.4– 0.51– 1.3– 3.4– 4.2– 0.88– 2.25– 8.8————– 1.7– 0.36– 0.9– 2.4————mAdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V OL = 0.4 Vdc) Sink(V OL = 0.5 Vdc)(V OL = 1.5 Vdc)I OL5.010150.641.64.2ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput Current ÎÎÎÎ I in ÎÎÎ15 ÎÎΗ 0.1ÎÎÎα ÎÎΗ ÎÎΗ 1.0ÎÎα ÎÎεAdc— ÎÎÎΗ ÎÎΗ ÎÎÎ5.0 ÎÎΗ ÎÎΗ ÎÎÎpFInput Capacitance(V in = 0)C in———0.511.33.40.882.258.8———0.360.92.4± 0.1 ÎÎα0.00001ÎÎÎÎÎÎÎ7.5———mAdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎQuiescent Current(Per Package)I DD5.01015———ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTotal Supply Current (5.) (6.)(Dynamic plus Quiescent,Per Package)(C L = 50 pF on all outputs, allbuffers switching)I T5.01015ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5.01015———0.0050.0100.0155.01015I T = (0.75 µA/kHz) f + I DDI T = (1.50 µA/kHz) f + I DDI T = (2.25 µA/kHz) f + I DD4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.5. The formulas given are for the typical characteristics only at 25 C.6. To calculate total supply current at loads other than 50 pF:I T (C L ) = I T (50 pF) + (C L – 50) Vfkwhere: I T is in µA (per package), C L in pF, V = (V DD – V SS ) in volts, f in kHz is input frequency, and k = 0.0015.———150300600µAdcµAdcÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΗÎÎÎÎhttp://onsemi.com63

MC14014B, MC14021BSWITCHING CHARACTERISTICS (7.) (C L = 50 pF, T A = 25 C)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCharacteristicÎÎÎÎSymbolMin Typ (8.) ÎÎÎMaxÎÎÎÎUnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Rise and Fall Timet TLH , t THL = (1.5 ns/pF) C L + 25 nst TLH , t THL = (0.75 ns/pF) C L + 12.5 nst TLH , t THL = (0.55 ns/pF) C L + 9.5 nst TLH ,t THLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPropagation Delay Time (Clock to Q, P/S to Q)t PHL , t PLH = (1.7 ns/pF) C L + 315 nst PHL , t PLH = (0.66 ns/pF) C L + 137 nsÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎt PHL , t PLH = (0.5 ns/pF) C L + 90 nst PLH ,t PHLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎClock Pulse Widtht WHÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎClock Frequencyf clÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎParallel/Serial Control Pulse Widtht WHÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSetup TimeP/S to Clockt suÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎHold TimeClock to P/St hÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSetup TimeData (Parallel or Serial) toClock or P/St suÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎHold TimeClock to D st hÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎHold TimeClock to P nt hÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput Clock Rise TimeÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎV DDVdc5.010155.010155.010155.010155.010155.010155.010155.010155.010155.01015——————400175135———400175135200100802020253508060453535504545100504040017011515075403.06.08.015075401005040– 2.5– 1007. The formulas given are for the typical characteristics only at 25 C.8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.t r(cl)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5.01015———1505030005252020———20010080800340230———1.53.04.0——————————————————1554nsnsnsMHznsnsnsnsnsnsµsV DDV outV DDV outPULSEGENERATORP/SCP6P7P8D SQ6Q7Q8I OHPULSEGENERATORP/SCP6P7P8D SQ6Q7Q8I OLEXTERNALPOWERSUPPLYEXTERNALPOWERSUPPLYPreset output under test to a logic “1” level.Figure 1. Output Source Current Test CircuitFigure 2. Output Sink Current Test Circuithttp://onsemi.com64

MC14014B, MC14021BV DD500 µF I D0.01 µFPULSEGENERATOR 1PULSEGENERATOR 2P/SCP1P2P3P4P5P6P7P8D SQ6Q7Q8V SSCERAMICC LC LC LCLOCK50%1fDATAFigure 3. Power Dissipation Test Circuit and WaveformSW 1V DD1PULSEGENERATOR 1PULSEGENERATOR 22221 1SWITCH POSITION 1 = PARALLEL INSWITCH POSITION 2 = SERIAL INP/SCP1P2P3P4P5P6P7P8D SV DDQ6Q7Q8V SSSW 2C LPARALLEL ORSERIAL DATAINPUTt WHCLOCK OR P/SINPUTQOUTPUT20 ns 20 nsV90%DD50%10%V SSt sut THLV90%DD50%10%V SSt WH t WLt PLHt PHLV90%OH50%10%V OLt TLHt THLt WL = t WH = 50% DUTY CYCLEFigure 4. Switching Time Test Circuit and Waveformshttp://onsemi.com65

The MC14015B dual 4–bit static shift register is constructed withMOS P–channel and N–channel enhancement mode devices in asingle monolithic structure. It consists of two identical, independent4–state serial–input/parallel–output registers. Each register hasindependent Clock and Reset inputs with a single serial Data input.The register states are type D master–slave flip–flops. Data is shiftedfrom one stage to the next during the positive–going clock transition.Each register can be cleared when a high level is applied on the Resetline. These complementary MOS shift registers find primary use inbuffer storage and serial–to–parallel conversion where low powerdissipation and/or noise immunity is desired.• Diode Protection on All Inputs• Supply Voltage Range = 3.0 Vdc to 18 Vdc• Logic Edge–Clocked Flip–Flop Design —Logic state is retained indefinitely with clock level either high or low;information is transferred to the output only on the positive goingedge of the clock pulse.• Capable of Driving Two Low–power TTL Loads or One Low–powerSchottky TTL Load Over the Rated Temperature Range.MAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 2.)Symbol Parameter Value UnitV DD DC Supply Voltage Range –0.5 to +18.0 VV in , V out Input or Output Voltage Range(DC or Transient)–0.5 to V DD + 0.5 VI in , I outP DInput or Output Current(DC or Transient) per PinPower Dissipation,per Package (Note 3.)±10 mA500 mWT A Ambient Temperature Range –55 to +125 °CT stg Storage Temperature Range –65 to +150 °CT LLead Temperature(8–Second Soldering)260 °C2. Maximum Ratings are those values beyond which damage to the devicemay occur.3. Temperature Derating:Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 CThis device contains protection circuitry to guard against damage due to highstatic voltages or electric fields. However, precautions must be taken to avoidapplications of any voltage higher than maximum rated voltages to thishigh–impedance circuit. For proper operation, V in and V out should be constrainedto the range V SS (V in or V out ) V DD .Unused inputs must always be tied to an appropriate logic voltage level (e.g.,either V SS or V DD ). Unused outputs must be left open.http://onsemi.comPDIP–16P SUFFIXCASE 648SOIC–16D SUFFIXCASE 751BTSSOP–16DT SUFFIXCASE 948FSOEIAJ–16F SUFFIXCASE 966A = Assembly LocationWL or L = Wafer LotYY or Y = YearWW or W = Work WeekORDERING INFORMATIONMARKINGDIAGRAMSDevice Package ShippingMC14015BCP PDIP–16 2000/BoxMC14015BD SOIC–16 48/RailMC14015BDR2 SOIC–16 2500/Tape & Reel1. For ordering information on the EIAJ version ofthe SOIC packages, please contact your localON Semiconductor representative.161161161MC14015BCPAWLYYWW14015BAWLYWW14015BALYWMC14015BAWLYWWMC14015BDT TSSOP–16 2000/Tape & Reel16MC14015BF SOEIAJ–16 See Note 1.MC14015BFEL SOEIAJ–16 See Note 1.1© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 366 Publication Order Number:MC14015B/D

MC14015BTRUTH TABLEC D R Q0 Q n0 0 0 Q n–11 0 1 Q n–1X 0 No Change No ChangeX X 1 0 0X = Don’t CareQ n = Q0, Q1, Q2, or Q3, as applicable.Q n–1 = Output of prior stage.PIN ASSIGNMENTC B116V DDQ3 B215D BQ2 A314R BQ1 A413Q0 BQ0 A512Q1 BR A611Q2 BD A710Q3 AV SS89C ABLOCK DIAGRAM7DQ0Q1549CRQ2Q3310615DQ0Q113121CRQ2Q311214V DD = PIN 16V SS = PIN 8http://onsemi.com67

MC14015BELECTRICAL CHARACTERISTICS (Voltages Referenced to V SS )ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΖ 55 C 25 C 125 C V DDÎÎÎÎÎÎÎÎÎÎCharacteristic ÎÎÎÎÎÎÎMinÎÎÎMaxÎÎÎÎ MinÎÎÎÎÎTyp (4.) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎMaxMaxÎÎÎUnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput VoltageV in = V DD or 0V in = 0 or V DD“0” LevelÎÎÎ ÎÎÎSymbol VdcV OL 5.0 —10 —15 —LevelÎÎÎΓ1” V OH 5.010154.959.9514.95ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput Voltage(V O = 4.5 or .05 Vdc)(V O = 9.0 or 1.0 Vdc)(V O = 13.5 or 1.5 Vdc)“0” LevelV IL0.050.050.05———0000.050.050.05ÎÎÎMin— 0.05 Vdc— 0.05— 0.05ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5.01015——————4.959.9514.955.01015———4.959.9514.95ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V O = 0.5 or 4.5 Vdc) “1” Level(V O = 1.0 or 9.0 Vdc)(V O = 1.5 or 13.5 Vdc)V IH5.010153.57.011ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Drive Current(V OH = 2.5 Vdc) Source(V OH = 4.6 Vdc)ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V OH = 9.5 Vdc)(V OH = 13.5 Vdc)I OH5.05.01015– 3.0– 0.64– 1.6– 4.2ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V OL = 0.4 Vdc) Sink(V OL = 0.5 Vdc)(V OL = 1.5 Vdc)I OL5.010150.641.64.2ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ1.53.04.0——————————3.57.011– 2.4– 0.51– 1.3– 3.42.254.506.752.755.508.25– 4.2– 0.88– 2.25– 8.81.53.04.0——————————3.57.011– 1.7– 0.36– 0.9– 2.4ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput Current ÎÎÎÎ I in 15 ÎÎÎ — ÎÎÎ — ÎÎΗ ÎÎÎÎÎεAdcÎÎÎΗ ÎÎÎ — ÎÎÎ — ÎÎÎÎ — ÎÎÎ 5.0 ÎÎÎÎ — ÎÎÎ — ÎÎÎ pFInput Capacitance(V in = 0)C in———0.511.33.40.882.258.8———0.360.92.4———1.53.04.0——————————VdcVdcVdcmAdcmAdc± 0.1 ÎÎÎÎ ±0.00001 ÎÎÎÎ ± 0.1 ÎÎÎ ± 1.0 ÎÎÎÎÎÎ7.5ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎQuiescent Current(Per Package)I DD5.01015———ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTotal Supply Current (5.) (6.)(Dynamic plus Quiescent,Per Package)(C L = 50 pF on all outputs, allbuffers switching)I T5.01015ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5.01020———0.0050.0100.0155.01020I T = (1.2 µA/kHz)f + I DDI T = (2.4 µA/kHz)f + I DDI T = (3.6 µA/kHz)f + I DD4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.5. The formulas given are for the typical characteristics only at 25 C.6. To calculate total supply current at loads other than 50 pF:I T (C L ) = I T (50 pF) + (C L – 50) Vfkwhere: I T is in µA (per package), C L in pF, V = (V DD – V SS ) in volts, f in kHz is input frequency, and k = 0.002.———150300600µAdcµAdchttp://onsemi.com68

SWITCHING CHARACTERISTICS (7.) (C L = 50 pF, T A = 25 C)MC14015BÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCharacteristicSymbolMinTyp (8.) MaxUnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Rise and Fall Timet TLH , t THL = (1.5 ns/pF) C L + 25 nst TLH , t THL = (0.75 ns/pF) C L + 12.5 nsÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎt TLH , t THL = (0.55 ns/pF) C L + 9.5 nsPropagation Delay TimeClock, Data to Qt TLH ,t THLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎt PLH , t PHL = (1.7 ns/pF) C L + 225 nst PLH , t PHL = (0.66 ns/pF) C L + 92 nst PLH , t PHL = (0.5 ns/pF) C L + 65 nsReset to QÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎt PLH , t PHL = (1.7 ns/pF) C L + 375 nst PLH , t PHL = (0.66 ns/pF) C L + 147 nst PLH , t PHL = (0.5 ns/pF) C L + 95 nst PLH ,t PHLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎClock Pulse Widtht WHÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎClock Pulse Frequencyf clÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎClock Pulse Rise and Fall Timest TLH , t THLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎReset Pulse Widtht WHÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSetup TimeÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ7. The formulas given are for typical characteristics only at 25 C.8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.t suV DD5.010155.010155.010155.010155.010155.010155.010155.01015—————————400175135——————4001601203501007510050403101259046018012018585552.06.07.5———2008060100504020010080750250170750250170———1.53.03.751554——————nsnsnsMHzµsnsnsÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPULSEGENERATOR2PULSEGENERATOR1500 µFDCRV DD0.01 µFI D CERAMICV DDQ0Q1Q2Q3C LC LC LC LV SS1fCLOCK50%DATAFigure 1. Power Dissipation Test Circuit and Waveformhttp://onsemi.com69

MC14015Bt TLHSYNCPULSEGENERATOR2PULSEGENERATOR1DATAINPUTV DDt TLHD Q0CLOCKQ1C L INPUTQ2C LC Q3C LR C LV SSt WL = t WH = 50% Duty Cyclet TLH = t THL ≤ 20 nsQ0t sut WHt PLHt TLHt–90%50%10%t THL90%50%10%t WLt PHL90%t THLt THLV DD50%10%0 VV DD0 VFigure 2. Switching Test Circuit and WaveformsSYNCPULSEGENERATOR2PULSEGENERATOR1V DDD Q0Q1C LCRQ2Q3C LC LC LV SSCLOCKINPUTDATAINPUT50%50%t sut hV DD0 VV DD0 VFigure 3. Setup and Hold Time Test Circuit and Waveformshttp://onsemi.com70

MC14015BCIRCUIT SCHEMATICSDATAINSINGLE BITVDDQRESETCLOCKDATAINTO D OFNEXT BITVSSDATA INPUT BUFFER RESET INPUT BUFFER CLOCK INPUT BUFFERVDDVDDVDDDATA TOFIRST BITRESETINRESETTO 4 BITSCLOCKINCLOCKTO 4 BITSVSSVSSV SShttp://onsemi.com71

MC14015BLOGIC DIAGRAMSSINGLE BITDATACCQTO D OFNEXT BITCCCCRESETCCCCCCOMPLETE DEVICE5 4 3 10Q0 Q1 Q2 Q3D7C9DATA INPUT BUFFERCLOCK INPUT BUFFERD QC QRD QC QRD QC QRD QC QRR6RESET INPUT BUFFER13 1211 2Q0 Q1 Q2 Q3D15C1R14DATA INPUT BUFFERCLOCK INPUT BUFFERD QC QRD QC QRD QC QRD QC QRV DD = PIN 16V SS = PIN 8RESET INPUT BUFFERhttp://onsemi.com72

The MC14016B quad bilateral switch is constructed with MOSP–channel and N–channel enhancement mode devices in a singlemonolithic structure. Each MC14016B consists of four independentswitches capable of controlling either digital or analog signals. Thequad bilateral switch is used in signal gating, chopper, modulator,demodulator and CMOS logic implementation.• Diode Protection on All Inputs• Supply Voltage Range = 3.0 Vdc to 18 Vdc• Linearized Transfer Characteristics• Low Noise — 12 nV/√Cycle, f ≥ 1.0 kHz typical• Pin–for–Pin Replacements for CD4016B, CD4066B (Note improvedtransfer characteristic design causes more parasitic couplingcapacitance than CD4016)• For Lower R ON , Use The HC4016 High–Speed CMOS Device orThe MC14066B• This Device Has Inputs and Outputs Which Do Not Have ESDProtection. Antistatic Precautions Must Be Taken.MAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 2.)Symbol Parameter Value UnitV DD DC Supply Voltage Range –0.5 to +18.0 VV in , V out Input or Output Voltage Range(DC or Transient)–0.5 to V DD + 0.5 VI inInput Current (DC or Transient)per Control Pin±10 mAI SW Switch Through Current ±25 mAP DPower Dissipation,per Package (Note 3.)500 mWT A Ambient Temperature Range –55 to +125 °CT stg Storage Temperature Range –65 to +150 °CT LLead Temperature(8–Second Soldering)260 °C2. Maximum Ratings are those values beyond which damage to the devicemay occur.3. Temperature Derating:Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 CThis device contains protection circuitry to guard against damage due to highstatic voltages or electric fields. However, precautions must be taken to avoidapplications of any voltage higher than maximum rated voltages to thishigh–impedance circuit. For proper operation, V in and V out should be constrainedto the range V SS (V in or V out ) V DD .Unused inputs must always be tied to an appropriate logic voltage level (e.g.,either V SS or V DD ). Unused outputs must be left open.http://onsemi.comPDIP–14P SUFFIXCASE 646SOIC–14D SUFFIXCASE 751ASOEIAJ–14F SUFFIXCASE 965A = Assembly LocationWL or L = Wafer LotYY or Y = YearWW or W = Work WeekORDERING INFORMATIONMARKINGDIAGRAMSDevice Package ShippingMC14016BCP PDIP–14 2000/BoxMC14016BD SOIC–14 55/RailMC14016BDR2 SOIC–14 2500/Tape & Reel14MC14016BF SOEIAJ–14 See Note 1.1141141MC14016BCPAWLYYWW14016BAWLYWWMC14016BAWLYWWMC14016BFEL SOEIAJ–14 See Note 1.1. For ordering information on the EIAJ version ofthe SOIC packages, please contact your localON Semiconductor representative.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 373 Publication Order Number:MC14016B/D

MC14016BPIN ASSIGNMENTIN 1114V DDOUT 1213CONTROL 1OUT 2312CONTROL 4IN 2411IN 4CONTROL 2510OUT 4CONTROL 369OUT 3V SS78IN 3BLOCK DIAGRAM13CONTROL 11IN 15CONTROL 24IN 26CONTROL 38IN 312CONTROL 411IN 42OUT 13OUT 29OUT 310OUT 4V DD = PIN 14V SS = PIN 7ControlSwitch0 = V SS Off1 = V DD OnLOGIC DIAGRAM(1/4 OF DEVICE SHOWN)OUTCONTROLLOGIC DIAGRAM RESTRICTIONSV SS ≤ V in ≤ V DDV SS ≤ V out ≤ V DDINhttp://onsemi.com74

MC14016BELECTRICAL CHARACTERISTICS (Voltages Referenced to V SS )ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΖ 55 C 25 C ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCharacteristicV DDSymbol ÎÎÎ VdcFigureÎÎÎÎ125 ÎÎÎCTyp (4.) Max ÎÎ UnitÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MinÎÎÎ ÎÎÎÎ MaxÎÎÎ ÎÎÎÎMinÎÎÎÎ MinÎÎÎÎÎÎÎÎÎÎÎÎÎÎMaxÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ1 ÎÎÎÎ V IL ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ5.0ÎÎVdcÎÎÎInput VoltageControl InputV IH10155.01015ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎInput Current Control— 15 — ÎÎΗ ±0.00001 ±0.1 — µAdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput CapacitanceControlSwitch InputSwitch OutputFeed Through—I inC in———————————————————3.08.013±0.1 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎQuiescent Current(Per Package) (5.)I DD5.01015ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ2,3ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΓON” Resistance(V C = V DD , R L = 10 kΩ)(V in = + 5.0 Vdc)(V in = – 5.0 Vdc) V SS = – 5.0 Vdc(V in = ± 0.25 Vdc)4,5,6R ON————————————1.51.51.52.06.0115.05.05.00.20.90.90.9———————————————————————Vdc± 1.0ÎÎÎpF————ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΗ——0.250.51.0———0.00050.00100.0015ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V in = + 7.5 Vdc)(V in = – 7.5 Vdc) V SS = – 7.5 Vdc(V in = ± 0.25 Vdc)(V in = + 10 Vdc)(V in = + 0.25 Vdc) V SS = 0 Vdc(V in = + 5.6 Vdc)5.0ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ7.5ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V in = + 15 Vdc)(V in = + 0.25 Vdc) V SS = 0 Vdc(V in = + 9.3 Vdc)10ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ∆ “ON” ResistanceBetween any 2 circuits in a commonpackage(V C = V DD )(V in = ± 5.0 Vdc, V SS = – 5.0 Vdc)(V in = ± 7.5 Vdc, V SS = – 7.5 Vdc)∆R ON15ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ —ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5.07.5ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΗÎÎÎÎ — ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎεAdcInput/Output Leakage Current(V C = V SS )(V in = + 7.5, V out = – 7.5 Vdc)(V in = – 7.5, V out = + 7.5 Vdc)7.57.5ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΗ———————————————600600600360360360600600600360360360——±0.1±0.1——————————————————3003002802402401802603103102602603001510±0.0015±0.0015NOTE: All unused inputs must be returned to V DD or V SS as appropriate for the circuit application.4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.5. For voltage drops across the switch (∆V switch ) > 600 mV ( > 300 mV at high temperature), excessive V DD current may be drawn; i.e., thecurrent out of the switch may contain both V DD and switch input components. The reliability of the device will be unaffected unless theMaximum Ratings are exceeded. (See first page of this data sheet.) Reference Figure 14.0.250.51.0660660660400400400660660660400400400——±0.1± 0.1—————————————————————7.51530840840840520520520840840840520520520——± 1.0± 1.0µAdcOhmsOhmshttp://onsemi.com75

MC14016BELECTRICAL CHARACTERISTICS (6.) (C L = 50 pF, T A = 25 C)CharacteristicFigureSymbolÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPropagation Delay Time (V SS = 0 Vdc)V in to V out(V C = V DD , R L = 10 kΩ)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ7ÎÎÎt PLH ,t ÎÎÎÎ5.0ÎÎΗÎÎÎÎ15ÎÎÎ45ÎÎÎÎnsPHL 10 — 7.0 15V DDVdcMinÎÎÎTyp (7.) MaxÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎControl to ÎÎÎOutputÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ8 t ÎÎÎ PHZ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ,ÎÎÎÎns(V in 10 Vdc, R L = 10 kΩ)t PLZÎÎÎÎ,ÎÎÎ ÎÎÎ5.0 —t ÎÎÎÎÎÎÎ34ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ90PZH ,ÎÎÎÎ10 — 20 45ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ t ÎÎÎ PZL ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCrosstalk, Control ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎto Output (V SS = ÎÎÎ0 ÎÎÎVdc)9 — ÎÎÎÎÎÎÎ ÎÎÎÎ5.0ÎÎΗ 30 ÎÎÎΗ mV(V C = V DD , R in = 10 kΩ, R out = 10 kΩ,10 — 50 —ÎÎÎÎf ÎÎÎ= ÎÎÎÎ1.0 ÎÎÎkHz)ÎÎÎÎÎÎÎ ÎÎÎ15 — 100 —ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCrosstalk between any two switches ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V SS ÎÎÎÎÎÎÎÎΗÎÎÎÎ= 0 Vdc)ÎÎÎΗ — ÎÎÎÎÎÎΗ dBÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(R LÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ= 1.0 kΩ, f = 1.0 MHz,crosstalk 20 log10 V out1Vout2 )Noise Voltage (V SS = 0 Vdc)(V C = V DD , f = 100 Hz)10,11 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΗÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V C = V DD , f = 100 kHz)ÎÎÎ1515——5.0 ÎÎÎ6.0151235– 80 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSecond Harmonic Distortion (V SS = – 5.0 Vdc)(V in = 1.77 Vdc, RMS Centered @ 0.0 Vdc,R L = 10 kΩ, f = 1.0 kHz)—5.01015———242530———UnitnV/√CycleÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ12 ÎÎΗ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎdBÎÎÎInsertion Loss (V C = V DD , V in = 1.77 Vdc,V SS = – 5.0 Vdc, RMS centered = 0.0 Vdc, f = 1.0 MHz)Iloss 20 log10 V outVin )(R L = 1.0 kΩ)(R L = 10 kΩ)(R L = 100 kΩ)(R L = 1.0 MΩ)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎBandwidth (– 3.0 dB)ÎÎÎ12,13 BW ÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎMHzÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V C = V DD , V in = 1.77 Vdc, V SS = – 5.0 Vdc,RMS centered @ 0.0 Vdc)(R L = 1.0 kΩ)(R L = 10 kΩ)(R L = 100 kΩ)(R L = 1.0 MΩ)—5.010155.0————5.0 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOFF Channel Feedthrough Attenuation— ÎÎÎ —ÎÎÎÎ ÎÎÎÎÎÎÎÎÎkHzÎÎÎÎÎÎ(V SS = – 5.0 Vdc)Vout(V C = V SS , 20 log 10 –50 dB)Vin(R L = 1.0 kΩ)(R L = 10 kΩ)(R L = 100 kΩ)(R L = 1.0 MΩ)————5.0 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΗ———5.0 ÎÎÎ6. The formulas given are for typical characteristics only at 25 C.7. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.————1212150.162.30.20.10.05544038371250140182.0————————————————%http://onsemi.com76

MC14016BV CV in V outI SV IL : V C is raised from V SS until V C = V IL .V IL : at V C = V IL : I S = ±10 µA with V in = V SS , V out = V DD or V in = V DD , V out = V SS .V IH : When V C = V IH to V DD , the switch is ON and the R ON specifications are met.Figure 1. Input Voltage Test Circuit10,000V DD = 15 Vdc10 VdcPULSEGENERATORTO ALL4 CIRCUITSf cV DDI DV DDV outCONTROLINPUT10 kPD , POWER DISSIPATION ( µW)100010010T A = 25°C5.0 VdcP D = V DD x I DV SSV inFigure 2. Quiescent Power DissipationTest Circuit1.05.0 k 10 k100 k1.0 Mf c , FREQUENCY (Hz)10 MFigure 3. Typical Power Dissipation per Circuit(1/4 of device shown)50 MTYPICAL R ON versus INPUT VOLTAGERON, “ON” RESISTANCE (OHMS)700600500400300200100V C = V DD = 5.0 VdcV SS = – 5.0 VdcR L = 10 kΩT A = 25°CV C = V DD = 7.5 VdcV SS = – 7.5 VdcRON, “ON” RESISTANCE (OHMS)700600500400300200100V C = V DD = 10 VdcV SS = 0 VdcR L = 10 kΩT A = 25°CV C = V DD = 15 Vdc0– 10 – 8.0 – 4.0 0 4.0 8.0 10V in , INPUT VOLTAGE (Vdc)Figure 4. V SS = – 5.0 V and – 7.5 V00 2.0 6.0 10 14 18 20V in , INPUT VOLTAGE (Vdc)Figure 5. V SS = 0 Vhttp://onsemi.com77

MC14016BV CV outV inR LV outR L C LV in20 ns 20 nsV DDV90%in50% 10%V SSV outt PLH t PHL50%Figure 6. R ON CharacteristicsTest CircuitFigure 7. Propagation Delay Test Circuitand WaveformsV C20 nsV Ct PZHV out 10%t PZLV 90%outV outV inR L C LV X90%50%10%90%10%t PHZV DDV SSt PLZV in = V DDV x = V SSV CV outV in1 kV in = V SS10 k 15 pFFigure 8. Turn–On Delay Time Test Circuitand WaveformsFigure 9. Crosstalk Test Circuit35V C = V DDOUTINQUAN–TECHMODEL2283OR EQUIVNOISE VOLTAGE (nV/ CYCLE)30252015105.0010V DD = 15 Vdc10 Vdc5.0 Vdc1001.0 kf, FREQUENCY (Hz)10 k100 kFigure 10. Noise Voltage Test CircuitFigure 11. Typical Noise Characteristicshttp://onsemi.com78

MC14016B2.0TYPICAL INSERTION LOSS (dB)0– 2.0– 4.0– 6.0– 8.0–10–1210 kR L = 1 MΩ AND 100 kΩ10 kΩ1.0 kΩ– 3.0 dB (R L = 1.0 MΩ )– 3.0 dB (R L = 10 kΩ )– 3.0 dB (R L = 1.0 kΩ )100 k 1.0 M10 Mf in , INPUT FREQUENCY (Hz)100 MV inV CV outR L+ 2.5 Vdc0.0 Vdc– 2.5 VdcFigure 12. Typical Insertion Loss/BandwidthCharacteristicsFigure 13. Frequency Response Test CircuitON SWITCHCONTROLSECTIONOF ICVLOADSOURCEFigure 14. ∆V Across Switchhttp://onsemi.com79

MC14016BAPPLICATIONS INFORMATIONFigure A illustrates use of the Analog Switch. The 0–to–5V Digital Control signal is used to directly control a 5 V p–panalog signal.The digital control logic levels are determined by V DDand V SS . The V DD voltage is the logic high voltage; the V SSvoltage is logic low. For the example, V DD = +5 V logic highat the control inputs; V SS = GND = 0 V logic low.The maximum analog signal level is determined by V DDand V SS . The analog voltage must not swing higher thanV DD or lower than V SS .The example shows a 5 V p–p signal which allows nomargin at either peak. If voltage transients above V DDand/or below V SS are anticipated on the analog channels,external diodes (D x ) are recommended as shown in FigureB. These diodes should be small signal types able to absorbthe maximum anticipated current surges during clipping.The absolute maximum potential difference betweenV DD and V SS is 18.0 V. Most parameters are specified up to15 V which is the recommended maximum differencebetween V DD and V SS .+5 VV DDV SS+ 5.0 V+5 V5 V p–pANALOG SIGNALSWITCHINSWITCHOUT5 V p–pANALOG SIGNAL+ 2.5 VEXTERNALCMOSDIGITALCIRCUITRY0–TO–5 V DIGITALCONTROL SIGNALSMC14016BGNDFigure A. Application ExampleV DDV DDD xD xSWITCHINSWITCHOUTD xD xV SSV SSFigure B. External Germanium or Schottky Clipping Diodeshttp://onsemi.com80

The MC14017B is a five–stage Johnson decade counter withbuilt–in code converter. High speed operation and spike–free outputsare obtained by use of a Johnson decade counter design. The tendecoded outputs are normally low, and go high only at theirappropriate decimal time period. The output changes occur on thepositive–going edge of the clock pulse. This part can be used infrequency division applications as well as decade counter or decimaldecode display applications.• Fully Static Operation• DC Clock Input Circuit Allows Slow Rise Times• Carry Out Output for Cascading• Divide–by–N Counting• Supply Voltage Range = 3.0 Vdc to 18 Vdc• Capable of Driving Two Low–power TTL Loads or One Low–powerSchottky TTL Load Over the Rated Temperature Range• Pin–for–Pin Replacement for CD4017B• Triple Diode Protection on All Inputshttp://onsemi.comPDIP–16P SUFFIXCASE 648SOIC–16D SUFFIXCASE 751BMARKINGDIAGRAMS161161MC14017BCPAWLYYWW14017BAWLYWWMAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 2.)Symbol Parameter Value UnitV DD DC Supply Voltage Range –0.5 to +18.0 VV in , V out Input or Output Voltage Range(DC or Transient)–0.5 to V DD + 0.5 VI in , I outP DInput or Output Current(DC or Transient) per PinPower Dissipation,per Package (Note 3.)±10 mA500 mWT A Ambient Temperature Range –55 to +125 °CT stg Storage Temperature Range –65 to +150 °CT LLead Temperature(8–Second Soldering)260 °C2. Maximum Ratings are those values beyond which damage to the devicemay occur.3. Temperature Derating:Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 CThis device contains protection circuitry to guard against damage due to highstatic voltages or electric fields. However, precautions must be taken to avoidapplications of any voltage higher than maximum rated voltages to thishigh–impedance circuit. For proper operation, V in and V out should be constrainedto the range V SS (V in or V out ) V DD .Unused inputs must always be tied to an appropriate logic voltage level (e.g.,either V SS or V DD ). Unused outputs must be left open.SOEIAJ–16F SUFFIXCASE 966A = Assembly LocationWL or L = Wafer LotYY or Y = YearWW or W = Work WeekORDERING INFORMATIONDevice Package ShippingMC14017BCP PDIP–16 2000/BoxMC14017BD SOIC–16 48/RailMC14017BDR2 SOIC–16 2500/Tape & Reel1. For ordering information on the EIAJ version of theSOIC packages, please contact your local ONSemiconductor representative.161MC14017BAWLYWWMC14017BF SOEIAJ–16 See Note 1.MC14017BFEL SOEIAJ–16 See Note 1.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 381 Publication Order Number:MC14017B/D

MC14017BPIN ASSIGNMENTQ5116V DDQ1215RESETQ0314CLOCKQ2Q6451312CEC outQ7611Q9Q3710Q4V SS89Q8FUNCTIONAL TRUTH TABLE(Positive Logic)ClockDecodeClock Enable Reset Output=n0 X 0 nX 1 0 nX X 1 Q00 0 n+1X 0 nX 0 n1 0 n+1X = Don’t Care. If n < 5 Carry = “1”,Otherwise = “0”.CLOCKCLOCKENABLERESETBLOCK DIAGRAM14Q0 31315Q1Q2Q3Q4Q5Q6Q7Q8Q9C out2471015691112V DD = PIN 16V SS = PIN 8LOGIC DIAGRAMQ5 Q1 Q7 Q3 Q912671114CLOCKCLOCKENABLERESET1315CCDRQQRCCDRQQRCCDRQQRCCDRQQRCCDRQQR12CARRY3 5 4 9 10Q0 Q6 Q2 Q3 Q4http://onsemi.com82

MC14017BELECTRICAL CHARACTERISTICS (Voltages Referenced to V SS )ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΖ 55 C 25 C ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCharacteristicV DDSymbol ÎÎÎVdc ÎÎÎÎÎÎMin 125 ÎÎÎCÎÎÎMin UnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMin Typ (4.) MaxÎÎÎÎ MaxMaxÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput VoltageV in = V DD or 0“0” Level“1” LevelV OL5.01015———ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎV in = 0 or V DDInput Voltage(V O = 4.5 or 0.5 Vdc)(V O = 9.0 or 1.0 Vdc)(V O = 13.5 or 1.5 Vdc)“0” LevelV OHV IL5.010154.959.9514.95ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5.01015———0.050.050.05——————4.959.9514.950005.010150.050.050.05——————4.959.9514.95ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V O = 0.5 or 4.5 Vdc)(V O = 1.0 or 9.0 Vdc)(V O = 1.5 or 13.5 Vdc)“1” LevelV IH5.010153.57.011ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ1.53.04.0——————3.57.0112.254.506.752.755.508.251.53.04.0——————3.57.0110.050.050.05———1.53.04.0———VdcVdcVdcVdcOutput Drive Current(V OH = 2.5 Vdc) Source(V OH = 4.6 Vdc)(V OH = 9.5 Vdc)(V OH = 13.5 Vdc)I OH5.05.01015– 3.0– 0.64– 1.6– 4.2ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΗ———– 2.4– 0.51– 1.3– 3.4– 4.2– 0.88– 2.25– 8.8————– 1.7– 0.36– 0.9– 2.4————mAdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V OL = 0.4 Vdc) Sink(V OL = 0.5 Vdc)(V OL = 1.5 Vdc)I OL5.010150.641.64.2ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput CurrentI in 15 — — ±0.00001± 0.1 — ± 1.0 µAdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput Capacitance(V in = 0)C in—————0.511.33.40.882.258.8±ÎÎÎÎ0.1— — 5.0———7.50.360.92.4—————mAdcpFÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎQuiescent Current(Per Package)I DD5.01015———ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTotal Supply Current (5.) (6.)(Dynamic plus Quiescent,Per Package)(C L = 50 pF on all outputs, allbuffers switching)I T5.01015ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5.01020———0.0050.0100.015ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5.01020I T = (0.27 µA/kHz) f + I DDI T = (0.55 µA/kHz) f + I DDI T = (0.83 µA/kHz) f + I DD4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.5. The formulas given are for the typical characteristics only at 25 C.6. To calculate total supply current at loads other than 50 pF:I T (C L ) = I T (50 pF) + (C L – 50) Vfkwhere: I T is in µA (per package), C L in pF, V = (V DD – V SS ) in volts, f in kHz is input frequency, and k = 0.0011.———150300600µAdcµAdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎhttp://onsemi.com83

MC14017BSWITCHING CHARACTERISTICS (7.) (C L = 50 pF, T A = 25 C)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCharacteristicÎÎÎÎSymbolMin Typ (8.) ÎÎÎMaxÎÎÎÎUnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Rise and Fall Timet TLH , t THL = (1.5 ns/pF) C L + 25 nst TLH , t THL = (0.75 ns/pF) C L + 12.5 nst TLH , t THL = (0.55 ns/pF) C L + 9.5 nst TLH ,t THLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPropagation Delay TimeReset to Decode Outputt PLH , t PHL = (1.7 ns/pF) C L + 415 nst PLH , t PHL = (0.66 ns/PF) C L + 197 nst PLH , t PHL = (0.5 ns/pF) C L + 150 nst PLH ,t PHLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPropagation Delay TimeClock to C outt PLH , t PHL = (1.7 ns/pF) C L + 315 nst PLH , t PHL = (0.66 ns/pF) C L + 142 nst PLH ,t PHLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎt PLH , t PHL = (0.5 ns/pF) C L + 100 nsV DDVdc5.010155.010155.01015—————————1005040500230175400175125200100801000460350800350250nsnsnsPropagation Delay TimeClock to Decode Outputt PLH , t PHL = (1.7 ns/pF) C L + 415 nsÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎt PLH , t PHL = (0.66 ns/pF) C L + 197 nst PLH , t PHL = (0.5 ns/pF) C L + 150 nst PLH ,t PHLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTurn–Off Delay TimeReset to C outt PLH = (1.7 ns/pF) C L + 315 nst PLH = (0.66 ns/pF) C L + 142 nst PLH = (0.5 ns/pF) C L + 100 nst PLHÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎClock Pulse Widtht w(H)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎClock Frequencyf clÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎReset Pulse Widtht w(H)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎReset Removal Timet remÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎClock Input Rise and Fall Timet TLH ,t THLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎClock Enable Setup Timet suÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎClock Enable Removal Time5.010155.010155.010155.010155.010155.010155.01015——————25010075———50025019075027521050023017540017512512550355.0121625012595375135105No LimitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ7. The formulas given are for the typical characteristics only at 25 C.8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.t remÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5.010155.010153501501154202001401757552260100701000460350800350250———2.05.06.7————————————nsnsnsMHznsns—nsnshttp://onsemi.com84

MC14017BV DDV SSV DDV SSABS1S1CLOCKQ0ENABLEQ1Q2Q3Q4RESET Q5Q6Q7Q8Q9CLOCK C outI DV outEXTERNALPOWERSUPPLYDecodeOutputsCarryV GS =V DS =OutputSink Drive(S1 to A)Clock to 5thru 9(S1 to B)V DDV outOutputSource DriveClock todesiredoutputs(S1 to B)S1 to A– V DDV out – V DDV SSFigure 1. Typical Output Source and Output Sink Characteristics Test CircuitV DD500 µFI D0.01 µFCERAMICPULSEGENERATORCLOCKENABLERESETCLOCKQ0Q1Q2Q3Q4Q5Q6Q7Q8Q9C outf cC L C L C L C L C L C L C L C L C L C L C LV SSFigure 2. Typical Power Dissipation Test Circuithttp://onsemi.com85

MC14017BAPPLICATIONS INFORMATIONFigure 3 shows a technique for extending the number of decoded output states for the MC14017B. Decoded outputs aresequential within each stage and from stage to stage, with no dead time (except propagation delay).RESETCLOCKCEMC14017BQ0 Q1 ••• Q8 Q9RESETCLOCKCEMC14017BQ0Q1 • • • Q8 Q9RESETCLOCKCEMC14017BQ1 • • • Q8 Q99 DECODEDOUTPUTS8 DECODEDOUTPUTS8 DECODEDOUTPUTSCLOCKFIRST STAGE INTERMEDIATE STAGES LAST STAGEFigure 3. Counter ExpansionCLOCKCLOCKENABLEt remRESET20 nsQ0PcpNcpt PHLt PLH t PHLQ1t PLH t PHLQ2t PLH t PHL50%Q3t PLH t PHLQ4t PLHQ5t PLHQ610%Q7Q8Q9t PHLC outt PHLt PHL90%t TLHTHLt PLHTHLPLHt PLHt rem t su 20 ns 20 ns20 nst THLtPHLt THLt PHLt TLHtPLH20 nst PLHtt THLt TLH90%10% 50%TLHt TLHt THLt TLHt THLt THLt TLH90%V DD50%10% V SSV DDV SS20 nsV DDV SSt PLHV OHtV OLTLHt PHLt THLt THL t PHLt THLt TLHV OHV OLV OHV OLV OHV OLV OHV OLV OHV OLV OHV OLV OHV OLV OHV OLV OHV OLV OHV OLFigure 4. AC Measurement Definition and Functional Waveformshttp://onsemi.com86

The MC14018B contains five Johnson counter stages which areasynchronously presettable and resettable. The counters aresynchronous, and increment on the positive going edge of the clock.Presetting is accomplished by a logic 1 on the preset enable input.Data on the Jam inputs will then be transferred to their respective Qoutputs (inverted). A logic 1 on the reset input will cause all Q outputsto go to a logic 1 state.Division by any number from 2 to 10 can be accomplished byconnecting appropriate Q outputs to the data input, as shown in theFunction Selection table. Anti–lock gating is included in theMC14018B to assure proper counting sequence.• Fully Static Operation• Schmitt Trigger on Clock Input• Capable of Driving Two Low–power TTL Loads or One Low–powerSchottky TTL Load Over the Rated Temperature Range• Pin–for–Pin Replacement for CD4018Bhttp://onsemi.comPDIP–16P SUFFIXCASE 648SOIC–16D SUFFIXCASE 751BMARKINGDIAGRAMS161161MC14018BCPAWLYYWW14018BAWLYWWMAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 2.)Symbol Parameter Value UnitV DD DC Supply Voltage Range –0.5 to +18.0 VV in , V out Input or Output Voltage Range(DC or Transient)–0.5 to V DD + 0.5 VI in , I outP DInput or Output Current(DC or Transient) per PinPower Dissipation,per Package (Note 3.)±10 mA500 mWT A Ambient Temperature Range –55 to +125 °CT stg Storage Temperature Range –65 to +150 °CT LLead Temperature(8–Second Soldering)260 °C2. Maximum Ratings are those values beyond which damage to the devicemay occur.3. Temperature Derating:Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 CThis device contains protection circuitry to guard against damage due to highstatic voltages or electric fields. However, precautions must be taken to avoidapplications of any voltage higher than maximum rated voltages to thishigh–impedance circuit. For proper operation, V in and V out should be constrainedto the range V SS (V in or V out ) V DD .Unused inputs must always be tied to an appropriate logic voltage level (e.g.,either V SS or V DD ). Unused outputs must be left open.SOEIAJ–16F SUFFIXCASE 966A = Assembly LocationWL or L = Wafer LotYY or Y = YearWW or W = Work WeekORDERING INFORMATIONDevice Package ShippingMC14018BCP PDIP–16 2000/BoxMC14018BD SOIC–16 48/RailMC14018BDR2 SOIC–16 2500/Tape & Reel1. For ordering information on the EIAJ version ofthe SOIC packages, please contact your localON Semiconductor representative.161MC14018BAWLYWWMC14018BF SOEIAJ–16 See Note 1.MC14018BFEL SOEIAJ–16 See Note 1.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 387 Publication Order Number:MC14018B/D

MC14018BPIN ASSIGNMENTD in116V DDJAM 1215RJAM 2314CQ2413Q5Q1512JAM 5Q3611Q4JAM 3710PEV SS89JAM 4FUNCTIONAL TRUTH TABLEPreset JamClock Reset Enable Input Qn0 0 X Qn0 0 X D n *X 0 1 0 1X 0 1 1 0X 1 X X 1*D n is the Data input for that stage. Stage 1has Data brought out to Pin 1.http://onsemi.com88

MC14018BELECTRICAL CHARACTERISTICS (Voltages Referenced to V SS )ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΖ 55 C 25 C 125 C V DDÎÎÎÎÎÎÎÎÎÎCharacteristic ÎÎÎÎÎÎÎMinÎÎÎMaxÎÎÎÎ MinÎÎÎÎÎTyp (4.) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎMaxMaxÎÎÎUnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput VoltageV in = V DD or 0V in = 0 or V DD“0” LevelÎÎÎ ÎÎÎSymbol VdcV OL 5.0 —10 —15 —LevelÎÎÎΓ1” V OH 5.010154.959.9514.95ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput Voltage(V O = 4.5 or 0.5 Vdc)(V O = 9.0 or 1.0 Vdc)(V O = 13.5 or 1.5 Vdc)“0” LevelV IL0.050.050.05———0000.050.050.05ÎÎÎMin— 0.05 Vdc— 0.05— 0.05ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5.01015——————4.959.9514.955.01015———4.959.9514.95ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V O = 0.5 or 4.5 Vdc) “1” Level(V O = 1.0 or 9.0 Vdc)(V O = 1.5 or 13.5 Vdc)V IH5.010153.57.011ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ1.53.04.0——————3.57.0112.254.506.752.755.508.251.53.04.0——————3.57.011———1.53.04.0———VdcVdcVdcOutput Drive Current(V OH = 2.5 Vdc) Source(V OH = 4.6 Vdc)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V OH = 9.5 Vdc)(V OH = 13.5 Vdc)I OH5.05.01015– 3.0– 0.64– 1.6– 4.2————– 2.4– 0.51– 1.3– 3.4– 4.2– 0.88– 2.25– 8.8————– 1.7– 0.36– 0.9– 2.4————mAdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V OL = 0.4 Vdc) Sink(V OL = 0.5 Vdc)(V OL = 1.5 Vdc)I OL5.010150.641.64.2ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput Current ÎÎÎÎ I in ÎÎÎ15 ÎÎΗ 0.1ÎÎÎα ÎÎΗ ÎÎΗ 1.0ÎÎα ÎÎεAdc— ÎÎÎΗ ÎÎΗ ÎÎÎ5.0 ÎÎΗ ÎÎΗ ÎÎÎpFInput Capacitance(V in = 0)C in———0.511.33.40.882.258.8———0.360.92.4± 0.1 ÎÎα0.00001ÎÎÎÎÎÎÎ7.5———mAdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎQuiescent Current(Per Package)I DD5.01015———ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTotal Supply Current (5.) (6.)(Dynamic plus Quiescent,Per Package)(C L = 50 pF on all outputs, allbuffers switching)I T5.01015ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5.01020———0.0050.0100.0155.01020I T = (0.3 µA/kHz) f + I DDI T = (0.7 µA/kHz) f + I DDI T = (1.0 µA/kHz) f + I DD4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.5. The formulas given are for the typical characteristics only at 25 C.6. To calculate total supply current at loads other than 50 pF:I T (C L ) = I T (50 pF) + (C L – 50) Vfkwhere: I T is in µA (per package), C L in pF, V = (V DD – V SS ) in volts, f in kHz is input frequency, and k = 0.001.———150300600µAdcµAdcÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΗÎÎÎÎhttp://onsemi.com89

SWITCHING CHARACTERISTICS (7.) (C L = 50 pF, T A = 25 C)MC14018BÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCharacteristicSymbolÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMinTyp (8.) MaxÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Rise and Fall Timet TLH , t THL = (1.35 ns/pF) C L + 32 nst TLH , t THL = (0.6 ns/pF) C L + 20 nst TLH , t THL = (0.4 ns/pF) C L + 20 nst TLH , t THLV DDVdcAll TypesÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPropagation Delay TimeClock to Qt PLH , t PHL = (0.90 ns/pF) C L + 265 nsÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎt PLH , t PHL = (0.36 ns/pF) C L + 102 nst PLH , t PHL = (0.26 ns/pF) C L + 72 nsReset to Qt PLH = (0.90 ns/pF) C L + 325 nst PLH = (0.36 ns/pF) C L + 132 nst PLH = (0.26 ns/pF) C L + 81 nst PLH ,t PHLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPreset Enable to Qt PLH , t PHL = (0.90 ns/pF) C L + 325 nst PLH , t PHL = (0.36 ns/pF) C L + 132 nst PLH , t PHL = (0.26 ns/pF) C L + 81 nsÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSetup TimeData (Pin 1) to Clockt suÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎJam Inputs to Preset EnableÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎData (Jam Inputs)–to–PresetEnable Hold Timet hÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎClock Pulse Widtht WHÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎReset or Preset EnablePulse Widtht WHÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎClock Rise and Fall TimeÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎClock Pulse Frequencyt TLH , t THLf clÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5.010155.010155.010155.010155.010155.010155.010155.010155.010155.01015————————————2001008020010080540500480400200160290130110100504031012085370150100370150100000000270250240200100801456555No LimitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5.01015———2.56.58.020010080620240170740300200740300200———————————————1.253.254.07. The formulas given are for the typical characteristics only at 25 C.8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.UnitnsnsnsnsnsnsnsnsnsnsMHz20 ns 20 nsANY INPUT90%50%10%V DDV SSt PLHt PHLANY OUTPUT50%10%90%V OHV OLt TLHt THLFigure 1. Switching Time Waveformshttp://onsemi.com90

MC14018BTIMING DIAGRAM(Q5 Connected to Data Input)CLOCKRESETPRESET ENABLEJAM 1JAM 2JAM 3JAM 4JAM 5Q1Q2Q3Q4Q5DON’T CAREUNTIL PRESET ENABLEGOES HIGH10101010101010101010101010CounterModeDivide by 10Divide by 8Divide by 6Divide by 4Divide by 2Divide by 9Divide by 7Divide by 5Divide by 3FUNCTION SELECTIONConnectData Input(Pin 1) to:Q5Q4Q3Q2Q1Q5 • Q4Q4 • Q3Q3 • Q2Q2 • Q1CommentsNo externalcomponents needed.Gate package neededto provide ANDfunction. CounterSkips all 1’s stateLOGIC DIAGRAMJAM 1 JAM 2 JAM 3 JAM 4 JAM 5237912CLOCK 14DATA 1RESET 15CLOCKSHAPERSD QSD QSD QSD QSD QC C C C CQR P R P R P R P R PPRESET ENABLE 10V DD = PIN 16V SS = PIN 85 4 6 11 13Q1 Q2 Q3 Q4 Q5http://onsemi.com91

The MC14020B 14–stage binary counter is constructed with MOSP–channel and N–channel enhancement mode devices in a singlemonolithic structure. This part is designed with an input wave shapingcircuit and 14 stages of ripple–carry binary counter. The deviceadvances the count on the negative–going edge of the clock pulse.Applications include time delay circuits, counter controls, andfrequency–dividing circuits.• Fully Static Operation• Diode Protection on All Inputs• Supply Voltage Range = 3.0 Vdc to 18 Vdc• Capable of Driving Two Low–power TTL Loads or One Low–powerSchottky TTL Load Over the Rated Temperature Range• Buffered Outputs Available from stages 1 and 4 thru 14• Common Reset Line• Pin–for–Pin Replacement for CD4020BMAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 2.)Symbol Parameter Value UnitV DD DC Supply Voltage Range –0.5 to +18.0 VV in , V out Input or Output Voltage Range(DC or Transient)–0.5 to V DD + 0.5 VI in , I outP DInput or Output Current(DC or Transient) per PinPower Dissipation,per Package (Note 3.)±10 mA500 mWT A Ambient Temperature Range –55 to +125 °CT stg Storage Temperature Range –65 to +150 °CT LLead Temperature(8–Second Soldering)260 °C2. Maximum Ratings are those values beyond which damage to the devicemay occur.3. Temperature Derating:Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 CThis device contains protection circuitry to guard against damage due to highstatic voltages or electric fields. However, precautions must be taken to avoidapplications of any voltage higher than maximum rated voltages to thishigh–impedance circuit. For proper operation, V in and V out should be constrainedto the range V SS (V in or V out ) V DD .Unused inputs must always be tied to an appropriate logic voltage level (e.g.,either V SS or V DD ). Unused outputs must be left open.http://onsemi.comPDIP–16P SUFFIXCASE 648SOIC–16D SUFFIXCASE 751BTSSOP–16DT SUFFIXCASE 948FSOEIAJ–16F SUFFIXCASE 966A = Assembly LocationWL or L = Wafer LotYY or Y = YearWW or W = Work WeekORDERING INFORMATIONMARKINGDIAGRAMSDevice Package ShippingMC14020BCP PDIP–16 2000/BoxMC14020BD SOIC–16 48/RailMC14020BDR2 SOIC–16 2500/Tape & Reel161161161MC14020BCPAWLYYWW14020BAWLYWW1614020BALYWMC14020BAWLYWWMC14020BDT TSSOP–16 96/Rail1MC14020BF SOEIAJ–16 See Note 1.MC14020BFEL SOEIAJ–16 See Note 1.1. For ordering information on the EIAJ version ofthe SOIC packages, please contact your localON Semiconductor representative.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 392 Publication Order Number:MC14020B/D

MC14020BPIN ASSIGNMENTQ12116V DDQ13215Q11Q14314Q10Q6413Q8Q5512Q9Q7611RQ4710CV SS89Q1TRUTH TABLEClock Reset Output State0 No Change0 Advance to Next StateX 1 All Outputs are LowX = Don’t CareLOGIC DIAGRAMCLOCK10C QC Q RQ1 Q4 Q5 Q12 Q13 Q149 7 5 1 2 3C QC Q RC QC Q RC QC Q RC QC Q RCCRQRESET11Q6 = PIN 4Q7 = PIN 6Q8 = PIN 13Q9 = PIN 12Q10 = PIN 14Q11 = PIN 15V DD = PIN 16V SS = PIN 8http://onsemi.com93

MC14020BELECTRICAL CHARACTERISTICS (Voltages Referenced to V SS )ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΖ 55 C 25 C 125 C V DDÎÎÎÎÎÎÎÎÎÎCharacteristic ÎÎÎÎÎÎÎMinÎÎÎMaxÎÎÎÎ MinÎÎÎÎÎTyp (4.) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎMaxMaxÎÎÎUnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput VoltageV in = V DD or 0“0” Level“1” LevelÎÎÎ ÎÎÎSymbol VdcV OL 5.0 —10 —15 —ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎV in = 0 or V DDInput Voltage(V O = 4.5 or 0.5 Vdc)(V O = 9.0 or 1.0 Vdc)(V O = 13.5 or 1.5 Vdc)“0” LevelV OHV IL5.010154.959.9514.950.050.050.05———0000.050.050.05ÎÎÎMin— 0.05 Vdc— 0.05— 0.05ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5.01015——————4.959.9514.955.01015———4.959.9514.95ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V O = 0.5 or 4.5 Vdc)(V O = 1.0 or 9.0 Vdc)(V O = 1.5 or 13.5 Vdc)“1” LevelV IH5.010153.57.011ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ1.53.04.0——————3.57.0112.254.506.752.755.508.251.53.04.0——————3.57.011———1.53.04.0———VdcVdcVdcOutput Drive Current(V OH = 2.5 Vdc) Source(V OH = 4.6 Vdc)(V OH = 9.5 Vdc)(V OH = 13.5 Vdc)I OH5.05.01015– 3.0– 0.64– 1.6– 4.2ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΗ———– 2.4– 0.51– 1.3– 3.4– 4.2– 0.88– 2.25– 8.8————– 1.7– 0.36– 0.9– 2.4————mAdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V OL = 0.4 Vdc) Sink(V OL = 0.5 Vdc)(V OL = 1.5 Vdc)I OL5.010150.641.64.2ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput CurrentI in 15 — — ±0.00001± 0.1 — ± 1.0 µAdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput Capacitance(V in = 0)C in—————0.511.33.40.882.258.8±ÎÎÎÎ0.1— — 5.0———7.50.360.92.4—————mAdcpFÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎQuiescent Current(Per Package)I DD5.01015———ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTotal Supply Current (5.) (6.)(Dynamic plus Quiescent,Per Package)(C L = 50 pF on all outputs, allbuffers switching)I T5.01015ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5.01020———0.0050.0100.015ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5.01020I T = (0.42 µA/kHz)f + I DDI T = (0.85 µA/kHz)f + I DDI T = (1.43 µA/kHz)f + I DD4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.5. The formulas given are for the typical characteristics only at 25 C.6. To calculate total supply current at loads other than 50 pF:I T (C L ) = I T (50 pF) + (C L – 50) Vfkwhere: I T is in µA (per package), C L in pF, V = (V DD – V SS ) in volts, f in kHz is input frequency, and k = 0.001.———150300600µAdcµAdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎhttp://onsemi.com94

MC14020BPULSEGENERATORCLOCK500 µFCRV DD0.01 µFCERAMICFigure 1. Power Dissipation Test Circuitand WaveformI DQ1Q4Q nVSSC L20 ns 20 ns90%50%10%50% DUTY CYCLEC LV DDV SSC LPULSEGENERATORCRV DDV SSQ1Q4Q n C LC L20 ns 20 nsCLOCK 90%50%10%t WHt PLHQt TLH90%50%10%t THLt PHLFigure 2. Switching Time Test Circuitand WaveformsCLOCK1 2 4 8 16 32 64 128 256 512 1024 20484096819216,384RESETQ1Q4Q5Q6Q7Q8Q9Q10Q11Q12Q13Q14Figure 3. Timing Diagramhttp://onsemi.com96

The MC14022B is a four–stage Johnson octal counter with built–incode converter. High–speed operation and spike–free outputs areobtained by use of a Johnson octal counter design. The eight decodedoutputs are normally low, and go high only at their appropriate octaltime period. The output changes occur on the positive–going edge ofthe clock pulse. This part can be used in frequency divisionapplications as well as octal counter or octal decode displayapplications.• Fully Static Operation• DC Clock Input Circuit Allows Slow Rise Times• Carry Out Output for Cascading• Supply Voltage Range = 3.0 Vdc to 18 Vdc• Capable of Driving Two Low–power TTL Loads or One Low–powerSchottky TTL Load Over the Rated Temperature Range• Pin–for–Pin Replacement for CD4022B• Triple Diode Protection on All InputsMAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 1.)Symbol Parameter Value UnitV DD DC Supply Voltage Range –0.5 to +18.0 VV in , V out Input or Output Voltage Range(DC or Transient)–0.5 to V DD + 0.5 VI in , I outP DInput or Output Current(DC or Transient) per PinPower Dissipation,per Package (Note 2.)±10 mA500 mWT A Ambient Temperature Range –55 to +125 °CT stg Storage Temperature Range –65 to +150 °CT LLead Temperature(8–Second Soldering)260 °C1. Maximum Ratings are those values beyond which damage to the devicemay occur.2. Temperature Derating:Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 Chttp://onsemi.comPDIP–16P SUFFIXCASE 648SOIC–16D SUFFIXCASE 751BA = Assembly LocationWL or L = Wafer LotYY or Y = YearWW or W = Work WeekORDERING INFORMATIONMARKINGDIAGRAMSDevice Package ShippingMC14022BCP PDIP–16 2000/BoxMC14022BD SOIC–16 2400/BoxMC14022BDR2 SOIC–16 2500/Tape & Reel161161MC14022BCPAWLYYWW14022BAWLYWWThis device contains protection circuitry to guard against damage due to highstatic voltages or electric fields. However, precautions must be taken to avoidapplications of any voltage higher than maximum rated voltages to thishigh–impedance circuit. For proper operation, V in and V out should be constrainedto the range V SS (V in or V out ) V DD .Unused inputs must always be tied to an appropriate logic voltage level (e.g.,either V SS or V DD ). Unused outputs must be left open.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 397 Publication Order Number:MC14022B/D

MC14022BPIN ASSIGNMENTQ1116V DDQ0215RQ2314CQ5413CEQ6512C outNC611Q4Q3710Q7V SS89NCNC = NO CONNECTIONCLOCKCLOCKENABLEBLOCK DIAGRAM1413RESET 15V DD = PIN 16V SS = PIN 8NC = PIN 6, 9Q0Q1Q2Q3Q4Q5Q6Q7C out213711451012FUNCTIONAL TRUTH TABLE(Positive Logic)ClockClock Enable Reset Output=n0 X 0 nX 1 0 n0 0 n+1X 0 n1 0 n+1X 0 nX X 1 Q0X = Don’t Care. If n < 4 Carry = 1,Otherwise = 0.LOGIC DIAGRAM11 1 5 7Q4 Q1 Q6 Q3CLOCK1413CLOCKENABLEC QCD RQC QCD RQC QCD RQC QCD RQCARRY1215RESETV SSV DDQ0 Q5 Q2 Q72 4 3 10http://onsemi.com98

MC14022BELECTRICAL CHARACTERISTICS (Voltages Referenced to V SS )ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΖ 55 C 25 C ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCharacteristicOutput VoltageV in = V DD or 0“0” LevelV DDSymbol Vdc ÎÎÎÎÎÎMin V OL5.01015———125 ÎÎÎCÎÎÎMax UnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MaxÎÎÎÎÎÎÎÎÎMinÎÎÎMaxÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΓ1” LevelÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎV in = 0 or V DDInput Voltage(V O = 4.5 or 0.5 Vdc)(V O = 9.0 or 1.0 Vdc)(V O = 13.5 or 1.5 Vdc)“0” LevelV OHV IL5.010154.959.9514.95ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5.01015———0.050.050.05———Min———4.959.9514.95Typ (3.)0005.010150.050.050.05——————4.959.9514.95ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V O = 0.5 or 4.5 Vdc)(V O = 1.0 or 9.0 Vdc)(V O = 1.5 or 13.5 Vdc)“1” LevelV IH5.010153.57.011ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ1.53.04.0——————3.57.0112.254.506.752.755.508.251.53.04.0——————3.57.0110.050.050.05———1.53.04.0———VdcVdcVdcVdcOutput Drive Current(V OH = 2.5 Vdc) Source(V OH = 4.6 Vdc)(V OH = 9.5 Vdc)(V OH = 13.5 Vdc)I OH5.05.01015– 3.0– 0.64– 1.6– 4.2ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΗ———– 2.4– 0.51– 1.3– 3.4– 4.2– 0.88– 2.25– 8.8————– 1.7– 0.36– 0.9– 2.4————mAdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V OL = 0.4 Vdc) Sink(V OL = 0.5 Vdc)(V OL = 1.5 Vdc)I OL5.010150.641.64.2ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎInput CurrentI in 15 — ÎÎÎÎÎÎÎΗ±0.00001± 0.1 — ÎÎεAdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput Capacitance(V in = 0)C in—————0.511.33.40.882.258.8±ÎÎÎÎ0.1— — 5.0———7.50.360.92.4————mAdc±ÎÎÎ1.0— pFÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎQuiescent Current(Per Package)I DD5.01015———ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTotal Supply Current (4.) (5.)(Dynamic plus Quiescent,Per Package)(C L = 50 pF on all outputs, allbuffers switching)I T5.01015ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5.01020———0.0050.0100.015ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5.01020I T = (0.28 µA/kHz)f + I DDI T = (0.56 µA/kHz)f + I DDI T = (0.85 µA/kHz)f + I DD3. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.4. The formulas given are for the typical characteristics only at 25 C.5. To calculate total supply current at loads other than 50 pF:I T (C L ) = I T (50 pF) + (C L – 50) Vfkwhere: I T is in µA (per package), C L in pF, V = (V DD – V SS ) in volts, f in kHz is input frequency, and k = 0.00125.———150300600µAdcµAdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎhttp://onsemi.com99

MC14022BSWITCHING CHARACTERISTICS (6.) (C L = 50 pF, T A = 25 C)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCharacteristicÎÎÎÎSymbolMin Typ (7.) ÎÎÎMaxÎÎÎÎUnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Rise and Fall Timet TLH , t THL = (1.5 ns/pF) C L + 25 nst TLH , t THL = (0.75 ns/pF) C L + 12.5 nst TLH , t THL = (0.55 ns/pF) C L + 9.5 nst TLH ,t THLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPropagation Delay TimeReset to Decode Outputt PLH , t PHL = (1.7 ns/pF) C L + 415 nst PLH , t PHL = (0.66 ns/pF) C L + 197 nst PLH , t PHL = (0.5 ns/pF) C L + 150 nst PLH ,t PHLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPropagation Delay TimeClock to C outt PLH , t PHL = (1.7 ns/pF) C L + 315 nst PLH , t PHL = (0.66 ns/pF) C L + 142 nst PLH ,t PHLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎt PLH , t PHL = (0.5 ns/pF) C L + 100 nsV DDVdc5.010155.010155.01015—————————1005040500230175400175125200100801000460350800350250nsnsnsPropagation Delay TimeClock to Decode Outputt PLH , t PHL = (1.7 ns/pF) C L + 415 nsÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎt PLH , t PHL = (0.66 ns/pF) C L + 197 nst PLH , t PHL = (0.5 ns/pF) C L + 150 nst PLH ,t PHLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTurn–Off Delay TimeReset to C outt PLH = (1.7 ns/pF) C L + 315 nst PLH = (0.66 ns/pF) C L + 142 nst PLH = (0.5 ns/pF) C L + 100 nst PLHÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎClock Pulse Widtht WHÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎClock Frequencyf clÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎReset Pulse Widtht WHÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎReset Removal Timet remÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎClock Input Rise and Fall Timet TLH , t THLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎClock Enable Setup Timet suÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎClock Enable Removal Time5.010155.010155.010155.010155.010155.010155.01015——————25010075———5002501907502752102751259540017512512550355.0121625012595375135105No LimitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ6. The formulas given are for the typical characteristics only at 25 C.7. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.t remÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5.010155.010153501501154202001401757552260100701000460350800350250———2.05.06.7————————————nsnsnsMHznsns—nsnshttp://onsemi.com100

MC14022BV DDV DDV SSV SSS1ABCLOCKENABLERESETCLOCKQ0Q1Q2Q3Q4Q5Q6Q7C outV SSI DV outEXTERNALPOWERSUPPLYOutputsCarryV GS =V DS =OutputSink Drive(S1 to A)Clock to Q5thru Q7(S1 to B)V DDV outOutputSource DriveClock to desiredOutput(S1 to B)S1 to A– V DDV out – V DDFigure 1. Typical Output Source and Output Sink Characteristics Test CircuitV DD500 µFI D0.01 µFCERAMICPULSEGENERATORQ0Q1CLOCK Q2ENABLEQ3Q4RESET Q5Q6f Q7cCLOCK C outV C SS L C L C L C L C L C L C L C L C LFigure 2. Typical Power Dissipation Test CircuitAPPLICATIONS INFORMATIONFigure 3 shows a technique for extending the number of decoded output states for the MC14022B. Decoded outputs aresequential within each stage and from stage to stage, with no dead time (except propagation delay).CRCEMC14022BQ0 Q1 ••• Q6 Q7CRCEMC14022BQ0 Q1 ••• Q6 Q7CRCEMC14022BQ1 ••• Q6 Q77 DECODEDOUTPUTS6 DECODEDOUTPUTS6 DECODEDOUTPUTSCLOCKFIRST STAGE INTERMEDIATE STAGES LAST STAGEFigure 3. Counter Expansionhttp://onsemi.com101

MC14022Bt WH t WL90% V DDCLOCK50%10% V SSt rel t su 20 nsCLOCK20 nsV DDENABLEV SSt 20 ns 20 ns rem20 nsV DDRESETV SSt t PHLPLHt PLHQ0V OH50%Vt PLH t OLPHL t THL90% 50% V OHQ110%V OLt PLH t PHL t TLHV OHQ2V OLt PLH t PHL t TLHV OHQ3V OLt PLH t PHL t TLHV OHQ4Vt PLH t OLPHLt TLH tPHLV OHQ5V OLt TLH t THLtt PLHt TLHt THLPHLV OHQ6V OLt PLHt PHLV OHQ7V OLt PHLt TLH t THLt PLHC out t PHLV OHV OLtTLHt THLFigure 4. AC Measurement Definition and Functional Waveformshttp://onsemi.com102

The MC14024B is a 7–stage ripple counter with short propagationdelays and high maximum clock rates. The Reset input has standardnoise immunity, however the Clock input has increased noiseimmunity due to Hysteresis. The output of each counter stage isbuffered.• Diode Protection on All Inputs• Output Transitions Occur on the Falling Edge of the Clock Pulse• Supply Voltage Range = 3.0 Vdc to 18 Vdc• Capable of Driving Two Low–power TTL Loads or One Low–powerSchottky TTL Load Over the Rated Temperature Range• Pin–for–Pin Replacement for CD4024BMAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 2.)Symbol Parameter Value UnitV DD DC Supply Voltage Range –0.5 to +18.0 VV in , V out Input or Output Voltage Range(DC or Transient)–0.5 to V DD + 0.5 VI in , I outP DInput or Output Current(DC or Transient) per PinPower Dissipation,per Package (Note 3.)±10 mA500 mWT A Ambient Temperature Range –55 to +125 °CT stg Storage Temperature Range –65 to +150 °CT LLead Temperature(8–Second Soldering)260 °C2. Maximum Ratings are those values beyond which damage to the devicemay occur.3. Temperature Derating:Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 CThis device contains protection circuitry to guard against damage due to highstatic voltages or electric fields. However, precautions must be taken to avoidapplications of any voltage higher than maximum rated voltages to thishigh–impedance circuit. For proper operation, V in and V out should be constrainedto the range V SS (V in or V out ) V DD .Unused inputs must always be tied to an appropriate logic voltage level (e.g.,either V SS or V DD ). Unused outputs must be left open.http://onsemi.comPDIP–14P SUFFIXCASE 646SOIC–14D SUFFIXCASE 751ASOEIAJ–14F SUFFIXCASE 965A = Assembly LocationWL or L = Wafer LotYY or Y = YearWW or W = Work WeekORDERING INFORMATIONMARKINGDIAGRAMSDevice Package ShippingMC14024BCP PDIP–14 2000/BoxMC14024BD SOIC–14 2750/BoxMC14024BDR2 SOIC–14 2500/Tape & Reel14MC14024BF SOEIAJ–14 See Note 1.1141141MC14024BCPAWLYYWW14024BAWLYWWMC14024BAWLYWWMC14024BFEL SOEIAJ–14 See Note 1.1. For ordering information on the EIAJ version ofthe SOIC packages, please contact your localON Semiconductor representative.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 3103 Publication Order Number:MC14024B/D

MC14024BTRUTH TABLEClock Reset State0 0 No Change0 1 All Outputs Low1 0 No Change1 1 All Outputs Low0 No Change1 All Outputs Low0 Advance One Count1 All Outputs LowPIN ASSIGNMENTCLOCK114V DDRESET213NCQ7312Q1Q6411Q2Q5510NCQ469Q3V SS78NCV DD = PIN 14V SS = PIN 7NC = NO CONNECTIONLOGIC DIAGRAM1CLOCKCQCQCQCQ2RESETRQRQRQRQ12Q111Q24Q63Q7Q3 = PIN 9Q4 = PIN 6Q5 = PIN 5http://onsemi.com104

MC14024BELECTRICAL CHARACTERISTICS (Voltages Referenced to V SS )ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΖ 55 C 25 C ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCharacteristicV DDSymbol ÎÎÎVdc ÎÎÎÎÎÎMin 125 ÎÎÎCÎÎÎMin UnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMin Typ (4.) MaxÎÎÎÎ MaxMaxÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput VoltageV in = V DD or 0V in = 0 or V DD“0” LevelV OL5.01015LevelÎÎÎΓ1” V OH 5.01015———4.959.9514.95ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput Voltage(V O = 4.5 or 0.5 Vdc)(V O = 9.0 or 1.0 Vdc)(V O = 13.5 or 1.5 Vdc)“0” LevelV ILÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5.01015———0.050.050.05——————4.959.9514.950005.010150.050.050.05——————4.959.9514.95ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V O = 0.5 or 4.5 Vdc) “1” Level(V O = 1.0 or 9.0 Vdc)(V O = 1.5 or 13.5 Vdc)V IH5.010153.57.011ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ1.53.04.0——————3.57.0112.254.506.752.755.508.251.53.04.0——————3.57.0110.050.050.05———1.53.04.0———VdcVdcVdcVdcOutput Drive Current(V OH = 2.5 Vdc) Source(V OH = 4.6 Vdc)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V OH = 9.5 Vdc)(V OH = 13.5 Vdc)I OH5.05.01015– 3.0– 0.64– 1.6– 4.2————– 2.4– 0.51– 1.3– 3.4– 4.2– 0.88– 2.25– 8.8————– 1.7– 0.36– 0.9– 2.4————mAdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V OL = 0.4 Vdc) Sink(V OL = 0.5 Vdc)(V OL = 1.5 Vdc)I OL5.010150.641.64.2ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput Current ÎÎÎÎ I in ÎÎÎ15 ÎÎΗ 0.1ÎÎÎα ÎÎΗ ÎÎΗ 1.0ÎÎα ÎÎεAdc— ÎÎÎΗ ÎÎΗ ÎÎÎ5.0 ÎÎΗ ÎÎΗ ÎÎÎpFInput Capacitance(V in = 0)C in———0.511.33.40.882.258.8———0.360.92.4± 0.1 ÎÎα0.00001ÎÎÎÎÎÎÎ7.5———mAdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎQuiescent Current(Per Package)I DD5.01015———ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTotal Supply Current (5.) (6.)(Dynamic plus Quiescent,Per Package)(C L = 50 pF on all outputs, allbuffers switching)I T5.01015ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5.01020———0.0050.0100.0155.01020I T = (0.31 µA/kHz) f + I DDI T = (0.60 µA/kHz) f + I DDI T = (1.89 µA/kHz) f + I DD4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.5. The formulas given are for the typical characteristics only at 25 C.6. To calculate total supply current at loads other than 50 pF:I T (C L ) = I T (50 pF) + (C L – 50) Vfkwhere: I T is in µA (per package), C L in pF, V = (V DD – V SS ) in volts, f in kHz is input frequency, and k = 0.001.———150300600µAdcµAdcÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΗÎÎÎÎhttp://onsemi.com105

SWITCHING CHARACTERISTICS (7.) (C L = 50 pF, T A = 25 C)MC14024BÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCharacteristicSymbolMinTyp (8.) MaxUnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Rise and Fall Timet TLH , t THL = (1.5 ns/pF) C L + 25 nst TLH , t THL = (0.75 ns/pF) C L + 12.5 nst TLH , t THL = (0.55 ns/pF) C L + 9.5 nst TLH ,t THLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPropagation Delay TimeClock to Q1t PLH , t PHL = (1.7 ns/pF) C L + 295 nst PLH , t PHL = (0.66 ns/pF) C L + 117 nsÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎt PLH , t PHL = (0.5 ns/pF) C L + 85 nsClock to Q7t PLH , t PHL = (1.7 ns/pF) C L + 915 nst PLH , t PHL = (0.66 ns/pF) C L + 367 nst PLH , t PHL = (0.5 ns/pF) C L + 275 nsReset to Q nt PLH , t PHL = (1.7 ns/pF) C L + 415 nst PLH , t PHL = (0.66 ns/pF) C L + 217 nsÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎt PLH , t PHL = (0.5 ns/pF) C L + 155 nst PLH ,t PHLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎClock Pulse Widtht WHÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎReset Pulse Widtht WHÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎReset Removal Timet remÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎClock Input Rise and Fall Timet TLH , t THLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput Pulse FrequencyÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ7. The formulas given are for the typical characteristics only at 25 C.8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.f clÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎV DD5.010155.010155.010155.010155.010155.010155.010155.010155.01015————————————500165125600350260625190145——————1005040380150110100040030050025018020060403752001502507550———2.58.012200100806002301752000750565800400300—————————1.08.02001.03.04.0nsnsnsnsnssmsµsMHzhttp://onsemi.com106

MC14024BV DDV DDV OL = V outV DDV OH = V outCQ nCQ nRI OHRI OLCOUNT Q n TO ALOGIC “1” LEVEL.V SSEXTERNALPOWERSUPPLYV SSEXTERNALPOWERSUPPLYFigure 1. Typical Output SourceCharacteristics Test CircuitFigure 2. Typical Output SinkCharacteristics Test CircuitV DD500 µF0.01 µFCERAMICPULSEGENERATORfCRI DC LC LC LC LC LC LC LQ1Q2Q3Q4Q5Q6Q7V SSFigure 3. Power Dissipation Test Circuithttp://onsemi.com107

MC14024BCLOCK (1)RESET (2)Q1 (12)Q2 (11)Q3 (9)Q4 (6)Q5 (5)Q6 (4)Q7 (3)tWLtWH150%2 4 8 16 32 64 128 255tremtPLH190%10%tTLHtPLH2tTLHtPHL150%tPHL2tTHL90%10%50%tPLH3tPHL3tTHL50%tTLHtPHL4tTHLtPLH450%tTLHtPLH5tPHL5tTHL50%tPHL6tTLHtTHLtPLH650%90%10%tTLHtPLH7tPHL7tTHLtTLHtTHLInput t TLH and t THL = 20 ns50%tR1tR2tR3tR4tR5tR6tR7VDDV SSV DDVSSVOHVOLVOHV OLVOHVOLVOHV OLV OHVOLVOHVOLVOHVOLFigure 4. Functional Waveformshttp://onsemi.com108

The MC14027B dual J–K flip–flop has independent J, K, Clock (C),Set (S) and Reset (R) inputs for each flip–flop. These devices may beused in control, register, or toggle functions.• Diode Protection on All Inputs• Supply Voltage Range = 3.0 Vdc to 18 Vdc• Logic Swing Independent of Fanout• Logic Edge–Clocked Flip–Flop Design —Logic state is retained indefinitely with clock level either high or low;information is transferred to the output only on the positive–goingedge of the clock pulse• Capable of Driving Two Low–power TTL Loads or One Low–powerSchottky TTL Load Over the Rated Temperature Range• Pin–for–Pin Replacement for CD4027BMAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 2.)Symbol Parameter Value UnitV DD DC Supply Voltage Range –0.5 to +18.0 VV in , V out Input or Output Voltage Range(DC or Transient)–0.5 to V DD + 0.5 VI in , I outP DInput or Output Current(DC or Transient) per PinPower Dissipation,per Package (Note 3.)±10 mA500 mWT A Ambient Temperature Range –55 to +125 °CT stg Storage Temperature Range –65 to +150 °CT LLead Temperature(8–Second Soldering)260 °C2. Maximum Ratings are those values beyond which damage to the devicemay occur.3. Temperature Derating:Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 CThis device contains protection circuitry to guard against damage due to highstatic voltages or electric fields. However, precautions must be taken to avoidapplications of any voltage higher than maximum rated voltages to thishigh–impedance circuit. For proper operation, V in and V out should be constrainedto the range V SS (V in or V out ) V DD .Unused inputs must always be tied to an appropriate logic voltage level (e.g.,either V SS or V DD ). Unused outputs must be left open.http://onsemi.comPDIP–16P SUFFIXCASE 648SOIC–16D SUFFIXCASE 751BSOEIAJ–16F SUFFIXCASE 966A = Assembly LocationWL or L = Wafer LotYY or Y = YearWW or W = Work WeekORDERING INFORMATIONMARKINGDIAGRAMSDevice Package ShippingMC14027BCP PDIP–16 2000/BoxMC14027BD SOIC–16 2400/BoxMC14027BDR2 SOIC–16 2500/Tape & Reel161161161MC14027BCPAWLYYWW14027BAWLYWWMC14027BAWLYWWMC14027BF SOEIAJ–16 See Note 1.MC14027BFEL SOEIAJ–16 See Note 1.1. For ordering information on the EIAJ version ofthe SOIC packages, please contact your localON Semiconductor representative.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 3109 Publication Order Number:MC14027B/D

MC14027BInputsTRUTH TABLEOutputs*C † J K S R Q ‡ n Q n+1 Q n+11 X 0 0 0 1 0X 0 0 0 1 1 00 X 0 0 0 0 1X 1 0 0 1 0 11 1 0 0 Qo Qo QoX X 0 0 X Q n Q nX X X 1 0 X 1 0X X X 0 1 X 0 1X X X 1 1 X 1 1X = Don’t Care‡ = Present State† = Level Change * = Next StateNoChangePIN ASSIGNMENTQ A116V DDQ A215Q BC A314Q BR A413C BK A512R BJ A611K BS A710J BV SS89S BBLOCK DIAGRAM76JSQ13C5KRQ24910JSQ1513C11KRQ1412V DD = PIN 16V SS = PIN 8http://onsemi.com110

MC14027BELECTRICAL CHARACTERISTICS (Voltages Referenced to V SS )ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΖ 55 C 25 C 125 C V DDÎÎÎÎÎÎÎÎÎÎCharacteristic ÎÎÎÎÎÎÎMinÎÎÎMaxÎÎÎÎ MinÎÎÎÎÎTyp (4.) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎMaxMaxÎÎÎUnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput VoltageV in = V DD or 0V in = 0 or V DD“0” LevelÎÎÎ ÎÎÎSymbol VdcV OL 5.0 —10 —15 —LevelÎÎÎΓ1” V OH 5.010154.959.9514.95ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput Voltage(V O = 4.5 or 0.5 Vdc)(V O = 9.0 or 1.0 Vdc)(V O = 13.5 or 1.5 Vdc)“0” LevelV IL0.050.050.05———0000.050.050.05ÎÎÎMin— 0.05 Vdc— 0.05— 0.05ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5.01015——————4.959.9514.955.01015———4.959.9514.95ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V O = 0.5 or 4.5 Vdc) “1” Level(V O = 1.0 or 9.0 Vdc)(V O = 1.5 or 13.5 Vdc)V IH5.010153.57.011ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ1.53.04.0——————3.57.0112.254.506.752.755.508.251.53.04.0——————3.57.011———1.53.04.0———VdcVdcVdcOutput Drive Current(V OH = 2.5 Vdc) Source(V OH = 4.6 Vdc)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V OH = 9.5 Vdc)(V OH = 13.5 Vdc)I OH5.05.01015– 3.0– 0.64– 1.6– 4.2————– 2.4– 0.51– 1.3– 3.4– 4.2– 0.88– 2.25– 8.8————– 1.7– 0.36– 0.9– 2.4————mAdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V OL = 0.4 Vdc) Sink(V OL = 0.5 Vdc)(V OL = 1.5 Vdc)I OL5.010150.641.64.2ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput Current ÎÎÎÎ I in ÎÎÎ15 ÎÎΗ 0.1ÎÎÎα ÎÎΗ ÎÎΗ 1.0ÎÎα ÎÎεAdc— ÎÎΗ ÎÎΗ ÎÎΗ ÎÎΗ ÎÎÎpFInput Capacitance(V in = 0)C in———0.511.33.40.882.258.8———0.360.92.4± 0.1 ÎÎα0.00001ÎÎÎÎÎÎÎ7.5———mAdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎQuiescent Current(Per Package)I DD5.01015———ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTotal Supply Current (5.) (6.)(Dynamic plus Quiescent,Per Package)(C L = 50 pF on all outputs, allbuffers switching)I T5.01015ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ1.02.04.0———0.0020.0040.0061.02.04.0I T = (0.8 µA/kHz) f + I DDI T = (1.6 µA/kHz) f + I DDI T = (2.4 µA/kHz) f + I DD4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.5. The formulas given are for the typical characteristics only at 25 C.6. To calculate total supply current at loads other than 50 pF:I T (C L ) = I T (50 pF) + (C L – 50) Vfkwhere: I T is in µA (per package), C L in pF, V = (V DD – V SS ) in volts, f in kHz is input frequency, and k = 0.002.———3060120µAdcµAdcÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΗÎÎÎÎ 5.0ÎÎÎÎhttp://onsemi.com111

SWITCHING CHARACTERISTICS (7.) (C L = 50 pF, T A = 25 C)MC14027BÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCharacteristicSymbolMinTyp (8.) MaxUnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Rise and Fall Timet TLH , t THL = (1.5 ns/pF) C L + 25 nst TLH , t THL = (0.75 ns/pF) C L + 12.5 nst TLH , t THL = (0.55 ns/pF) C L + 12.5 nst TLH ,t THLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPropagation Delay Times**Clock to Q, Qt PLH , t PHL = (1.7 ns/pF) C L + 90 nst PLH , t PHL = (0.66 ns/pF) C L + 42 nsÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎt PLH , t PHL = (0.5 ns/pF) C L + 25 nst PLH ,t PHLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSet to Q, Qt PLH , t PHL = (1.7 ns/pF) C L + 90 nst PLH , t PHL = (0.66 ns/pF) C L + 42 nsÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎt PLH , t PHL = (0.5 ns/pF) C L + 25 nsReset to Q, Qt PLH , t PHL = (1.7 ns/pF) C L + 265 nst PLH , t PHL = (0.66 ns/pF) C L + 67 nst PLH , t PHL = (0.5 ns/pF) C L + 50 nsÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎV DD5.010155.010155.010155.01015————————————1005040175755017575503501007520010080350150100350150100450200150nsnsSetup Timest suÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎHold Timest hÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎClock Pulse Widtht WH , t WLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎClock Pulse Frequencyf clÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎClock Pulse Rise and Fall Timet TLH , t THLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎRemoval TimesSett remÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎResetSet and Reset Pulse Widtht WHÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5.010155.010155.010155.010155.0101551015510155.010151405035140503533011075——————9045355025202501007070251770251716555383.09.013———1053– 30– 15– 107. The formulas given are for the typical characteristics only at 25 C.8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.1255035—————————1.54.56.5155.04.0—————————nsnsnsMHzµsnsnsÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎhttp://onsemi.com112

MC14027B20 ns 20 nsV90%DDJ 50%10%V SS20 ns 20 nsV DDK90%t su 50%10%tsuV SS th20 ns 20 ns90%V DDC50%10%V SSt WH t WL1f clt PLHt PHLV90%OHQ50%10%V OLt TLHt THLInputs R and S low.For the measurement of t WH , I/f cl , and P Dthe Inputs J and K are kept high.20 ns 20 ns90%SET OR50%RESET10%t w t rem20 ns 20 ns90%CLOCK50%10%Q or QtPLHt PHL50%t wV DDV SSV DDV SSV OHV OLFigure 1. Dynamic Signal Waveforms(J, K, Clock, and Output)Figure 2. Dynamic Signal Waveforms(Set, Reset, Clock, and Output)LOGIC DIAGRAM(1/2 of Device Shown)SCQJCCKCCCRCCQCCChttp://onsemi.com113

The MC14028B decoder is constructed so that an 8421 BCD codeon the four inputs provides a decimal (one–of–ten) decoded output,while a 3–bit binary input provides a decoded octal (one–of–eight)code output with D forced to a logic “0”. Expanded decoding such asbinary–to–hexadecimal (one–of–16), etc., can be achieved by usingother MC14028B devices. The part is useful for code conversion,address decoding, memory selection control, demultiplexing, orreadout decoding.• Diode Protection on All Inputs• Supply Voltage Range = 3.0 Vdc to 18 Vdc• Capable of Driving Two Low–power TTL Loads or One Low–powerSchottky TTL Load Over the Rated Temperature Range• Positive Logic Design• Low Outputs on All Illegal Input Combinations• Similar to CD4028B.http://onsemi.comPDIP–16P SUFFIXCASE 648SOIC–16D SUFFIXCASE 751BMARKINGDIAGRAMS161161MC14028BCPAWLYYWW14028BAWLYWWMAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 2.)Symbol Parameter Value UnitV DD DC Supply Voltage Range –0.5 to +18.0 VV in , V out Input or Output Voltage Range(DC or Transient)–0.5 to V DD + 0.5 VSOEIAJ–16F SUFFIXCASE 966161MC14028BAWLYWWI in , I outP DInput or Output Current(DC or Transient) per PinPower Dissipation,per Package (Note 3.)±10 mA500 mWA = Assembly LocationWL or L = Wafer LotYY or Y = YearWW or W = Work WeekT A Ambient Temperature Range –55 to +125 °CT stg Storage Temperature Range –65 to +150 °CT LLead Temperature(8–Second Soldering)260 °C2. Maximum Ratings are those values beyond which damage to the devicemay occur.3. Temperature Derating:Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 CThis device contains protection circuitry to guard against damage due to highstatic voltages or electric fields. However, precautions must be taken to avoidapplications of any voltage higher than maximum rated voltages to thishigh–impedance circuit. For proper operation, V in and V out should be constrainedto the range V SS (V in or V out ) V DD .Unused inputs must always be tied to an appropriate logic voltage level (e.g.,either V SS or V DD ). Unused outputs must be left open.ORDERING INFORMATIONDevice Package ShippingMC14028BCP PDIP–16 2000/BoxMC14028BD SOIC–16 2400/BoxMC14028BDR2 SOIC–16 2500/Tape & ReelMC14028BF SOEIAJ–16 See Note 1.MC14028BFEL SOEIAJ–16 See Note 1.1. For ordering information on the EIAJ version ofthe SOIC packages, please contact your localON Semiconductor representative.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 3114 Publication Order Number:MC14028B/D

MC14028BPIN ASSIGNMENTQ4116V DDQ2215Q3Q0314Q1Q7413BQ9512CQ5611DQ6710AV SS89Q8TRUTH TABLED C B A Q9Q8Q7Q6Q5Q4Q3Q2Q1Q00 0 0 0 0 0 0 0 0 0 0 0 0 10 0 0 1 0 0 0 0 0 0 0 0 1 00 0 1 0 0 0 0 0 0 0 0 1 0 00 0 1 1 0 0 0 0 0 0 1 0 0 00 1 0 0 0 0 0 0 0 1 0 0 0 00 1 0 1 0 0 0 0 1 0 0 0 0 00 1 1 0 0 0 0 1 0 0 0 0 0 00 1 1 1 0 0 1 0 0 0 0 0 0 01 0 0 0 0 1 0 0 0 0 0 0 0 01 0 0 1 1 0 0 0 0 0 0 0 0 01 0 1 0 0 0 0 0 0 0 0 0 0 01 0 1 1 0 0 0 0 0 0 0 0 0 01 1 0 0 0 0 0 0 0 0 0 0 0 01 1 0 1 0 0 0 0 0 0 0 0 0 01 1 1 0 0 0 0 0 0 0 0 0 0 01 1 1 1 0 0 0 0 0 0 0 0 0 0BLOCK DIAGRAM8421BCDINPUTS3–BITBINARYINPUTS10131211ABCDQ0Q1Q2Q3Q4Q5Q6Q7Q8Q9314215167495OCTALDECODEDOUTPUTSDECIMALDECODEDOUTPUTSV DD = PIN 16V SS = PIN 8http://onsemi.com115

MC14028BELECTRICAL CHARACTERISTICS (Voltages Referenced to V SS )ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΖ 55 C 25 C 125 C V DDÎÎÎÎÎÎÎÎÎÎCharacteristic ÎÎÎÎÎÎÎMinÎÎÎMaxÎÎÎÎ MinÎÎÎÎÎTyp (4.) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎMaxMaxÎÎÎUnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput VoltageV in = V DD or 0“0” Level“1” LevelÎÎÎSymbol ÎÎÎVdcV OL5.01015———ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎV in = 0 or V DDInput Voltage(V O = 4.5 or 0.5 Vdc)(V O = 9.0 or 1.0 Vdc)(V O = 13.5 or 1.5 Vdc)“0” LevelV OH5.010154.959.9514.950.050.050.05———0000.050.050.05ÎÎÎMin— 0.05 Vdc— 0.05— 0.05ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎV IL5.01015——————4.959.9514.955.01015———4.959.9514.95ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V O = 0.5 or 4.5 Vdc)(V O = 1.0 or 9.0 Vdc)(V O = 1.5 or 13.5 Vdc)“1” LevelV IH5.010153.57.011ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ1.53.04.0——————3.57.0112.254.506.752.755.508.251.53.04.0——————3.57.011———1.53.04.0———VdcVdcVdcOutput Drive Current(V OH = 2.5 Vdc) Source(V OH = 4.6 Vdc)(V OH = 9.5 Vdc)(V OH = 13.5 Vdc)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎI OH5.05.01015– 3.0– 0.64– 1.6– 4.2ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΗ———– 2.4– 0.51– 1.3– 3.4– 4.2– 0.88– 2.25– 8.8————– 1.7– 0.36– 0.9– 2.4————mAdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V OL = 0.4 Vdc) Sink(V OL = 0.5 Vdc)(V OL = 1.5 Vdc)I OL5.010150.641.64.2ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎInput CurrentI in 15 — ÎÎÎÎÎÎÎΗ±0.00001± 0.1 — ÎÎεAdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput Capacitance(V in = 0)C in—————0.511.33.40.882.258.8±ÎÎÎÎ0.1— — 5.0———7.50.360.92.4————mAdc±ÎÎÎ1.0— pFÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎQuiescent Current(Per Package)I DD5.01015———ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTotal Supply Current (5.) (6.)(Dynamic plus Quiescent,Per Package)(C L = 50 pF on all outputs, allbuffers switching)I T5.01015ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5.01020———0.0050.0100.015ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5.01020I T = (0.3 µA/kHz) f + I DDI T = (0.6 µA/kHz) f + I DDI T = (0.9 µA/kHz) f + I DD4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.5. The formulas given are for the typical characteristics only at 25 C.6. To calculate total supply current at loads other than 50 pF:I T (C L ) = I T (50 pF) + (C L – 50) Vfkwhere: I T is in µA (per package), C L in pF, V = (V DD – V SS ) in volts, f in kHz is input frequency, and k = 0.001.———150300600µAdcµAdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSWITCHING CHARACTERISTICS (7.) (C L = 50 pF, T A = 25 C)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCharacteristicSymbolMinTyp (8.) Max UnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Rise and Fall Timet TLH , t THL = (1.5 ns/pF) C L + 25 nst TLH , t THL = (0.75 ns/pF) C L + 12.5 nst TLH , t THL = (0.55 ns/pF) C L + 9.5 nst TLH ,t THLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPropagation Delay Timet PLH , t PHL = (1.7 ns/pF) C L + 215 nst PLH , t PHL = (0.66 ns/pF) C L + 97 nst PLH , t PHL = (0.5 ns/pF) C L + 65 nst PLH ,t PHLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ7. The formulas given are for the typical characteristics only at 25 C.8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎV DD5.010155.01015——————10050403001309020010080600260180nsnshttp://onsemi.com116

MC14028BInputs B, C, and Dswitching in respectto a BCD code.20 ns 20 ns90%INPUT A50%10%1/fV DDV SSAll outputs connectedto respective C L loads.f in respect to a systemclock.Inputs A, B, and D low.INPUT C10%t PLH20 ns 20 ns90%50%t PHLV DDV SSQ410%90%50%V OHV OLt TLHt THLFigure 1. Dynamic Signal WaveformsLOGIC DIAGRAMQ0ABCDQ1Q2Q3Q4Q5Q6Q7Q8Q9http://onsemi.com117

MC14028BAPPLICATIONS INFORMATIONExpanded decoding can be performed by using theMC14028B and other CMOS Integrated Circuits. Thecircuit in Figure 2 converts any 4–bit code to a decimal orhexadecimal code. The accompanying table shows the inputbinary combinations, the associated “output numbers” thatgo “high” when selected, and the “redefined outputnumbers” needed for the proper code. For example: For thecombination DCBA = 0111 the output number 7 is redefinedfor the 4–bit binary, 4–bit gray, excess–3, or excess–3 graycodes as 7, 5, 4, or 2, respectively. Figure 3 shows a 6–bitbinary 1–of–64 decoder using nine MC14028B circuits andtwo MC14069UB inverters.The MC14028B can be used in decimal digit displays,such as, neon readouts or incandescent projection indicatorsas shown in Figure 4.INPUTSD C B AD C B A D C B AMC14028BMC14028BQ9 Q0 Q9 Q015 – 8 15 – 0OUTPUT NUMBERSFigure 2. Code Conversion Circuit and Truth TableCode and RedefinedOutput NumbersHexadecimalDecimalInputsOutput NumbersD C B A 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 04–BitBinary4–BitGray0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 00 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 10 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 3 0 2 20 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 3 2 0 3 30 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 4 7 1 4 40 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 5 6 2 30 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 6 4 3 1 40 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 7 5 4 21 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 8 15 51 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 9 14 6 51 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 10 12 7 9 61 0 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 11 13 8 51 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 12 8 9 5 61 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 13 9 6 7 71 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14 11 8 8 81 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 10 7 9 9Excess–3Excess–3GrayAiken4221http://onsemi.com118

MC14028BINPUTSA B C D E F INHIBIT(NO SELECTION)A B C –DMC14028BQ0Q9A B C DMC14028BQ0 Q9A B C DMC14028BQ0 Q9A B C DMC14028BQ0 Q9A B C DMC14028BQ0 Q9A B C DMC14028BQ0 Q9A B C DMC14028BQ0 Q9A B C DMC14028BQ0 Q9A B C DMC14028BQ0 Q90 7 8 15 16 23 24 31 32 39 40 47 48 55 56 63*1/6 MC14069UB 64 OUTPUTS (SELECTED OUTPUT IS HIGH)Figure 3. Six–Bit Binary 1–of–64 DecoderABCDMC14028BQ0Q1Q2Q3Q4Q5Q6Q7Q8Q99APPROPRIATEVOLTAGENEONDISPLAY0OR9 2 1 0APPROPRIATEVOLTAGEINCANDESCENTDISPLAYFigure 4. Decimal Digit Display Applicationhttp://onsemi.com119

The MC14029B Binary/Decade up/down counter is constructedwith MOS P–channel and N–channel enhancement mode devices in asingle monolithic structure. The counter consists of type D flip–flopstages with a gating structure to provide toggle flip–flop capability.The counter can be used in either Binary or BCD operation. Thiscomplementary MOS counter finds primary use in up/down anddifference counting and frequency synthesizer applications where lowpower dissipation and/or high noise immunity is desired. It is alsouseful in A/D and D/A conversion and for magnitude and signgeneration.• Diode Protection on All Inputs• Supply Voltage Range = 3.0 Vdc to 18 Vdc• Internally Synchronous for High Speed• Logic Edge–Clocked Design — Count Occurs on Positive GoingEdge of Clock• Asynchronous Preset Enable Operation• Capable of Driving Two Low–power TTL Loads or One Low–powerSchottky TTL Load Over the Rated Temperature Range• Pin for Pin Replacement for CD4029BMAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 2.)Symbol Parameter Value UnitV DD DC Supply Voltage Range –0.5 to +18.0 VV in , V out Input or Output Voltage Range(DC or Transient)–0.5 to V DD + 0.5 VI in , I outP DInput or Output Current(DC or Transient) per PinPower Dissipation,per Package (Note 3.)±10 mA500 mWT A Ambient Temperature Range –55 to +125 °CT stg Storage Temperature Range –65 to +150 °CT LLead Temperature(8–Second Soldering)260 °C2. Maximum Ratings are those values beyond which damage to the devicemay occur.3. Temperature Derating:Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 CThis device contains protection circuitry to guard against damage due to highstatic voltages or electric fields. However, precautions must be taken to avoidapplications of any voltage higher than maximum rated voltages to thishigh–impedance circuit. For proper operation, V in and V out should be constrainedto the range V SS (V in or V out ) V DD .Unused inputs must always be tied to an appropriate logic voltage level (e.g.,either V SS or V DD ). Unused outputs must be left open.http://onsemi.comPDIP–16P SUFFIXCASE 648SOIC–16D SUFFIXCASE 751BSOEIAJ–16F SUFFIXCASE 966A = Assembly LocationWL or L = Wafer LotYY or Y = YearWW or W = Work WeekORDERING INFORMATIONMARKINGDIAGRAMSDevice Package ShippingMC14029BCP PDIP–16 2000/BoxMC14029BD SOIC–16 2400/BoxMC14029BDR2 SOIC–16 2500/Tape & Reel1. For ordering information on the EIAJ version ofthe SOIC packages, please contact your localON Semiconductor representative.161161161MC14029BCPAWLYYWW14029BAWLYWWMC14029BAWLYWWMC14029BF SOEIAJ–16 See Note 1.MC14029BFEL SOEIAJ–16 See Note 1.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 3120 Publication Order Number:MC14029B/D

MC14029BCarry InTRUTH TABLEUp/DownPresetEnableAction1 X 0 No Count0 1 0 Count Up0 0 0 Count DownX X 1 PresetX = Don’t CarePIN ASSIGNMENTPE 1 16 V DDQ3 2 15 CLKP3 3 14 Q2P0 4 13 P2C in 5 12 P1Q0 6 11 Q1C out 7 10 U/DV SS 8 9 B/DELECTRICAL CHARACTERISTICS (Voltages Referenced to V SS )ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΖ 55 C 25 C 125 C ÎÎÎÎÎÎÎÎÎÎCharacteristicÎÎÎÎV DDÎÎÎMin Typ (4.) ÎÎÎÎÎMinÎÎÎ ÎÎÎÎÎÎÎÎÎMaxÎÎÎÎÎÎÎÎÎMaxUnitMaxÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput VoltageV in = V DD or 0“0” Level“1” LevelÎÎÎ Symbol VdcV OL 5.0 — 0.0510 — 0.0515 — 0.05ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎV in = 0 or V DDV OH5.010154.959.9514.95———0000.050.050.05ÎÎÎMin— 0.05 Vdc— 0.05— 0.05ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput Voltage“0” Level(V O = 4.5 or 0.5 Vdc)(V O = 9.0 or 1.0 Vdc)(V O = 13.5 or 1.5 Vdc)V IL5.01015———ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΗ——1.53.04.04.959.9514.95———5.010152.254.506.75———1.53.04.04.959.9514.95——————1.53.04.0VdcVdc(V O = 0.5 or 4.5 Vdc)(V O = 1.0 or 9.0 Vdc)(V O = 1.5 or 13.5 Vdc)“1” LevelV IH5.010153.57.011ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΗ——3.57.0112.755.508.25———3.57.011———VdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Drive Current(V OH = 2.5 Vdc) Source(V OH = 4.6 Vdc)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V OH = 9.5 Vdc)(V OH = 13.5 Vdc)I OH5.05.01015– 3.0– 0.64– 1.6– 4.2————– 2.4– 0.51– 1.3– 3.4– 4.2– 0.88– 2.25– 8.8————– 1.7– 0.36– 0.9– 2.4————mAdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V OL = 0.4 Vdc) Sink(V OL = 0.5 Vdc)(V OL = 1.5 Vdc)I OL5.010150.641.64.2ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput Current ÎÎÎÎ I in ÎÎÎ15 ÎÎΗ 0.1ÎÎÎα ÎÎΗ ÎÎΗ 1.0ÎÎα ÎÎεAdc— ÎÎΗ ÎÎΗ ÎÎΗ ÎÎΗ ÎÎÎpFInput Capacitance(V in = 0)C in———0.511.33.40.882.258.8———0.360.92.4± 0.1 ÎÎα0.00001ÎÎÎÎÎÎÎ7.5———mAdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎQuiescent Current(Per Package)I DD5.01015———ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTotal Supply Current (5.) (6.)(Dynamic plus Quiescent,Per Package)(C L = 50 pF on all outputs, allbuffers switching)I T5.01015ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5.01020———0.0050.0100.0155.01020I T = (0.58 µA/kHz) f + I DDI T = (1.20 µA/kHz) f + I DDI T = (1.70 µA/kHz) f + I DD4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.5. The formulas given are for the typical characteristics only at 25 C.6. To calculate total supply current at loads other than 50 pF:I T (C L ) = I T (50 pF) + (C L – 50) Vfkwhere: I T is in µA (per package), C L in pF, V = (V DD – V SS ) in volts, f in kHz is input frequency, and k = 0.001.———150300600µAdcµAdcÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΗÎÎÎÎ 5.0ÎÎÎÎhttp://onsemi.com121

SWITCHING CHARACTERISTICS (7.) (C L = 50 pF, T A = 25 C)MC14029BAll TypesÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCharacteristicSymbolÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMinTyp (8.) MaxÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Rise and Fall Timet TLH , t THL = (1.5 ns/pF) C L + 25 nst TLH , t THL = (0.75 ns/pF) C L + 12.5 nst TLH , t THL = (0.55 ns/pF) C L + 9.5 nst TLH ,t THLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPropagation Delay TimeClk to Qt PLH , t PHL = (1.7 ns/pF) C L + 230 nst PLH , t PHL = (0.66 ns/pF) C L + 97 nst PLH , t PHL = (0.5 ns/pF) C L + 75 nst PLH ,t PHLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎClk to C outt PLH , t PHL = (1.7 ns/pF) C L + 230 nst PLH , t PHL = (0.66 ns/pF) C L + 97 nst PLH , t PHL = (0.5 ns/pF) C L + 75 nst PLH ,t PHLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎV DD5.010155.010155.01015—————————1005040200100902501308520010080400200180500260190UnitnsnsnsC in to C outt PLH , t PHL = (1.7 ns/pF) C L + 95 nst PLH , t PHL = (0.66 ns/pF) C L + 47 nst PLH , t PHL = (0.5 ns/pF) C L + 35 nst PLH ,t PHLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPE to Qt PLH , t PHL = (1.7 ns/pF) C L + 230 nst PLH , t PHL = (0.66 ns/pF) C L + 97 nst PLH , t PHL = (0.5 ns/pF) C L + 75 nst PLH ,t PHLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5.010155.01015——————175505023510080360120100470200160nsnsÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPE to C outt PLH , t PHL = (1. 7 ns/pF) C L + 465 nst PLH , t PHL = (0.66 ns/pF) C L + 192 nst PLH , t PHL = (0.5 ns/pF) C L + 125 nst PLH ,t PHLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5.01015———320145105640290210nsÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎClock Pulse Widtht W(cl)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎClock Pulse Frequencyf clÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPreset Removal TimeThe Preset Signal must be low prior to a positive–goingtransition of the clock.t remÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎClock Rise and Fall Timet r(cl)t f(cl)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCarry In Setup Timet suÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎUp/Down Setup TimeÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎBinary/Decade Setup TimeÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPreset Enable Pulse WidthÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ7. The formulas given are for the typical characteristics only at 25 C.8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.t WÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5.010155.010155.010155.0101 55.010155.010155.010155.010151808060———1608060———150604034014010032014010013070509040304.08.010804030———75302017070501607050653525———2.04.05.0———1554————————————nsMHznsµsnsnsnsnsÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎhttp://onsemi.com122

MC14029BV DD500 pF I D0.01 µFCERAMICPULSEGENERATORPEC inB/DU/DCLKP0P1P2P3Q0Q1Q2Q3C outC LC LC LC LC L20 ns 20 nsCLK 50%90%10%VARIABLEWIDTHV DDV SSFigure 1. Power Dissipation Test Circuit and WaveformV DDPROGRAMMABLEPULSEGENERATORPEC inB/DU/DCLKP0P1P2P3V SSQ0Q1Q2C LQ3C outC LC LC LC Lt WCARRY IN ORUP/DOWNOR BINARY/DECADECLOCKPRESET ENABLEQ0 OR CARRY OUTt su t rem1/f cl50%50%t WC out ONLY20 nst TLH90%10% 10%90%t PLHt THL t PHLt PLHV DDV SSV DDV SSV DDV SSV OHV OLFigure 2. Switching Time Test Circuit and Waveformshttp://onsemi.com123

MC14029BTIMING DIAGRAMCLOCKCARRY INUP/DOWNBINARY/DECADEPEP0P1P2P3Q0Q1Q2Q3CARRY OUTCOUNT 0 1 2 3 4 5 6 7 8 9 8 7 6 5 4 3 2 1 0 0 9 6 7 0Q3 Q2 Q1 Q0C out MC14029BC inU/DMSDB/DPEP3 P2 P1 P0 CLKQ3 Q2 Q1 Q0C outC inU/D MC14029BB/DPEP3 P2 P1 P0 CLKQ3 Q2 Q1 Q0C out MC14029BC inU/DLSDB/DPEP3 P2 P1 P0 CLKOUTPUTINPUTCLOCKV“1” DDV“2” DD“3”V DD V DDCLOCKC out 1 (LSD)C out 2C out 3 (MSD)PECOUNT123122121120119101100991110910123122*t W 900 ns @ V DD = 5 VFigure 3. Divide by N BCD Down Counter and Timing Diagram(Shown for N = 123)http://onsemi.com124

MC14029BLOGIC DIAGRAMBINARY/DECADEPRESET ENABLECARRY INUP/DOWNCLOCK91510154 P0 12 P1 13 P2 3 P3PETEP0Q0PETEP1Q1PETEP2Q2PETEP3Q3CLK Q0CLK Q1CLK Q2CLK Q36 Q01 Q114 Q22 Q37CARRY OUThttp://onsemi.com125

The MC14040B 12–stage binary counter is constructed with MOSP–channel and N–channel enhancement mode devices in a singlemonolithic structure. This part is designed with an input wave shapingcircuit and 12 stages of ripple–carry binary counter. The deviceadvances the count on the negative–going edge of the clock pulse.Applications include time delay circuits, counter controls, andfrequency–driving circuits.• Fully Static Operation• Diode Protection on All Inputs• Supply Voltage Range = 3.0 Vdc to 18 Vdc• Capable of Driving Two Low–power TTL Loads or One Low–powerSchottky TTL Load Over the Rated Temperature Range• Common Reset Line• Pin–for–Pin Replacement for CD4040BMAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 2.)Symbol Parameter Value UnitV DD DC Supply Voltage Range –0.5 to +18.0 VV in , V out Input or Output Voltage Range(DC or Transient)–0.5 to V DD + 0.5 VI in , I outP DInput or Output Current(DC or Transient) per PinPower Dissipation,per Package (Note 3.)±10 mA500 mWT A Ambient Temperature Range –55 to +125 °CT stg Storage Temperature Range –65 to +150 °CT LLead Temperature(8–Second Soldering)260 °C2. Maximum Ratings are those values beyond which damage to the devicemay occur.3. Temperature Derating:Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 CThis device contains protection circuitry to guard against damage due to highstatic voltages or electric fields. However, precautions must be taken to avoidapplications of any voltage higher than maximum rated voltages to thishigh–impedance circuit. For proper operation, V in and V out should be constrainedto the range V SS (V in or V out ) V DD .Unused inputs must always be tied to an appropriate logic voltage level (e.g.,either V SS or V DD ). Unused outputs must be left open.http://onsemi.comPDIP–16P SUFFIXCASE 648SOIC–16D SUFFIXCASE 751BTSSOP–16DT SUFFIXCASE 948FSOEIAJ–16F SUFFIXCASE 966A = Assembly LocationWL or L = Wafer LotYY or Y = YearWW or W = Work WeekORDERING INFORMATIONMARKINGDIAGRAMSDevice Package ShippingMC14040BCP PDIP–16 2000/BoxMC14040BD SOIC–16 2400/BoxMC14040BDR2 SOIC–16 2500/Tape & Reel161161161MC14040BCPAWLYYWW14040BAWLYWW16MC14040BAWLYWWMC14040BDT TSSOP–16 96/Rail114040BALYWMC14040BF SOEIAJ–16 See Note 1.MC14040BFEL SOEIAJ–16 See Note 1.1. For ordering information on the EIAJ version ofthe SOIC packages, please contact your localON Semiconductor representative.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 3126 Publication Order Number:MC14040B/D

MC14040BPIN ASSIGNMENTQ12116V DDQ6215Q11Q5314Q10Q7413Q8Q4512Q9Q3611RQ2710CV SS89Q1TRUTH TABLEClock Reset Output State0 No Change0 Advance to next stateX 1 All Outputs are lowX = Don’t CareLOGIC DIAGRAMQ1 Q2 Q3 Q10 Q11 Q129 7 6 14 15 1CLOCK10C Q C Q C QC Q C Q C QC Q C Q C QC Q C Q CRRRRRRRESET11Q4 = PIN 5Q5 = PIN 3Q6 = PIN 2Q7 = PIN 4Q8 = PIN 13Q9 = PIN 12V DD = PIN 16V SS = PIN 8http://onsemi.com127

MC14040BELECTRICAL CHARACTERISTICS (Voltages Referenced to V SS )ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΖ 55 C 25 C 125 C V DDÎÎÎÎÎÎÎÎÎÎCharacteristic ÎÎÎÎÎÎÎMinÎÎÎMaxÎÎÎÎ MinÎÎÎÎÎTyp (4.) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎMaxMaxÎÎÎUnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput VoltageV in = V DD or 0“0” Level“1” LevelÎÎÎ ÎÎÎSymbol VdcV OL 5.0 —10 —15 —ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎV in = 0 or V DDInput Voltage(V O = 4.5 or 0.5 Vdc)(V O = 9.0 or 1.0 Vdc)(V O = 13.5 or 1.5 Vdc)“0” LevelV OHV IL5.010154.959.9514.950.050.050.05———0000.050.050.05ÎÎÎMin— 0.05 Vdc— 0.05— 0.05ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5.01015——————4.959.9514.955.01015———4.959.9514.95ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V O = 0.5 or 4.5 Vdc)(V O = 1.0 or 9.0 Vdc)(V O = 1.5 or 13.5 Vdc)“1” LevelV IH5.010153.57.011ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ1.53.04.0——————3.57.0112.254.506.752.755.508.251.53.04.0——————3.57.011———1.53.04.0———VdcVdcVdcOutput Drive Current(V OH = 2.5 Vdc) Source(V OH = 4.6 Vdc)(V OH = 9.5 Vdc)(V OH = 13.5 Vdc)I OH5.05.01015– 3.0– 0.64– 1.6– 4.2ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΗ———– 2.4– 0.51– 1.3– 3.4– 4.2– 0.88– 2.25– 8.8————– 1.7– 0.36– 0.9– 2.4————mAdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V OL = 0.4 Vdc) Sink(V OL = 0.5 Vdc)(V OL = 1.5 Vdc)I OL5.010150.641.64.2ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎInput CurrentI in 15 — ÎÎÎÎÎÎÎΗ±0.00001± 0.1 — ÎÎεAdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput Capacitance(V in = 0)C in—————0.511.33.40.882.258.8±ÎÎÎÎ0.1— — 5.0———7.50.360.92.4————mAdc±ÎÎÎ1.0— pFÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎQuiescent Current(Per Package)I DD5.01015———ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTotal Supply Current (5.) (6.)(Dynamic plus Quiescent,Per Package)(C L = 50 pF on all outputs, allbuffers switching)I T5.01015ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5.01020———0.0050.0100.015ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5.01020I T = (0.42 µA/kHz) f + I DDI T = (0.85 µA/kHz) f + I DDI T = (1.43 µA/kHz) f + I DD4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.5. The formulas given are for the typical characteristics only at 25 C.6. To calculate total supply current at loads other than 50 pF:I T (C L ) = I T (50 pF) + (C L – 50) Vfkwhere: I T is in µA (per package), C L in pF, V = (V DD – V SS ) in volts, f in kHz is input frequency, and k = 0.001.———150300600µAdcµAdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎhttp://onsemi.com128

MC14040BSWITCHING CHARACTERISTICS (7.) (C L = 50 pF, T A = 25 C)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCharacteristicÎÎÎÎSymbolMin Typ (8.) ÎÎÎMaxÎÎÎÎUnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Rise and Fall TimeT TLH , T THL = (1.5 ns/pF) C L + 25 nsT TLH , T THL = (0.75 ns/pF) C L + 12.5 nsT TLH , T THL = (0.55 ns/pF) C L + 9.5 nst TLH ,t THLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPropagation Delay TimeClock to Q1t PHL , t PLH = (1.7 ns/pF) C L + 315 nst PHL , t PLH = (0.66 ns/pF) C L + 137 nst PHL , t PLH = (0.5 ns/pF) C L + 95 nst PLH ,t PHLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎClock to Q12t PHL , t PLH = (1.7 ns/pF) C L + 2415 nst PHL , t PLH = (0.66 ns/pF) C L + 867 nst PHL , t PLH = (0.5 ns/pF) C L + 475 nsÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPropagation Delay TimeReset to Q nt PHL = (1.7 ns/pF) C L + 485 nst PHL = (0.86 ns/pF) C L + 182 nst PHL = (0.5 ns/pF) C L + 145 nst PHLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎV DDVdc5.010155.010155.01015—————————100504026011580162572050020010080520230160325014401000ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎClock Pulse Widtht WHÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎClock Pulse Frequencyf clÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎClock Rise and Fall Timet TLH , t THLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎReset Pulse Widtht WHÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5.010155.010155.010155.01015———385150115———37015511514055382.17.010.0No LimitReset Removal Timet rem5.0 130 65 —10 50 25 —15 30 15 —7. The formulas given are for the typical characteristics only at 25 C.8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5.0101596036027032012080740310230———1.53.54.5———nsnsnsnsnsMHznsnsns500 µF0.01 µFCERAMICPULSEGENERATORCV DDQ1Q2C LC LV C SS LPULSEGENERATORCRI DQ1Q2Q nV DDV SSC LC LRQ nCLOCKC L20 ns 20 ns90%50%10%50% DUTY CYCLEV DDV SSCLOCKQ20 ns 20 ns90%50%10%t PLHt WHt PHL90%50%10%tTLH t THLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎFigure 1. Power Dissipation Test Circuitand WaveformFigure 2. Switching Time Test Circuitand Waveformshttp://onsemi.com129

MC14040BCLOCK1 2 4 8 16 32 64 128 256 512 1024 2048 4096RESETQ1Q2Q3Q4Q5Q6Q7Q8Q9Q10Q11Q12Figure 3. Timing DiagramAPPLICATIONS INFORMATIONTIME–BASE GENERATORA 60 Hz sinewave obtained through a 1.0 Megohmresistor connected directly to a standard 120 Vac power lineis applied to the clock input of the MC14040B. By selectingoutputs Q5, Q10, Q11, and Q12 division by 3600 isaccomplished. The MC14012B decodes the counteroutputs, produces a single output pulse, and resets the binarycounter. The resulting output frequency is 1.0 pulse/minute.V DD120 Vac60 Hz1.0 M≥ 20 pFMC14040BC Q5Q10Q11R Q121/2MC14012B1/2MC14012B1.0 PULSE/MINUTEOUTPUTV SShttp://onsemi.com130

The MC14042B Quad Transparent Latch is constructed with MOSP–channel and N–channel enhancement mode devices in a singlemonolithic structure. Each latch has a separate data input, but all fourlatches share a common clock. The clock polarity (high or low) used tostrobe data through the latches can be reversed using the polarityinput. Information present at the data input is transferred to outputs Qand Q during the clock level which is determined by the polarity input.When the polarity input is in the logic “0” state, data is transferredduring the low clock level, and when the polarity input is in the logic“1” state the transfer occurs during the high clock level.• Buffered Data Inputs• Common Clock• Clock Polarity Control• Q and Q Outputs• Double Diode Input Protection• Supply Voltage Range = 3.0 Vdc to 1 8 Vdc• Capable of Driving Two Low–power TTL Loads or One Low–powerSchottky TTL Load Over the Rated Temperature RangeMAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 2.)Symbol Parameter Value UnitV DD DC Supply Voltage Range –0.5 to +18.0 VV in , V out Input or Output Voltage Range(DC or Transient)–0.5 to V DD + 0.5 VI in , I outInput or Output Current(DC or Transient) per Pin±10 mAhttp://onsemi.comPDIP–16P SUFFIXCASE 648SOIC–16D SUFFIXCASE 751BSOEIAJ–16F SUFFIXCASE 966A = Assembly LocationWL or L = Wafer LotYY or Y = YearWW or W = Work WeekMARKINGDIAGRAMS161161161MC14042BCPAWLYYWW14042BAWLYWWMC14042BAWLYWWP DPower Dissipation,per Package (Note 3.)500 mWORDERING INFORMATIONT A Ambient Temperature Range –55 to +125 °CT stg Storage Temperature Range –65 to +150 °CT LLead Temperature(8–Second Soldering)260 °C2. Maximum Ratings are those values beyond which damage to the devicemay occur.3. Temperature Derating:Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 CThis device contains protection circuitry to guard against damage due to highstatic voltages or electric fields. However, precautions must be taken to avoidapplications of any voltage higher than maximum rated voltages to thishigh–impedance circuit. For proper operation, V in and V out should be constrainedto the range V SS (V in or V out ) V DD .Unused inputs must always be tied to an appropriate logic voltage level (e.g.,either V SS or V DD ). Unused outputs must be left open.Device Package ShippingMC14042BCP PDIP–16 2000/BoxMC14042BD SOIC–16 2400/BoxMC14042BDR2 SOIC–16 2500/Tape & ReelMC14042BF SOEIAJ–16 See Note 1.MC14042BFEL SOEIAJ–16 See Note 1.MC14042BFR1 SOEIAJ–16 See Note 1.MC14042BFR2 SOEIAJ–16 See Note 1.1. For ordering information on the EIAJ version ofthe SOIC packages, please contact your localON Semiconductor representative.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 3131 Publication Order Number:MC14042B/D

MC14042BPIN ASSIGNMENTQ3116V DDQ0215Q3Q0314D3D0413D2CLOCK512Q2POLARITY611Q2D1710Q1V SS89Q1TRUTH TABLEClock Polarity Q0 0 Data1 0 Latch1 1 Data0 1 LatchLOGIC DIAGRAMCLOCKPOLARITY56D04LATCH1Q02Q03D17LATCH2Q110Q19V DD = PIN 16V SS = PIN 8D213D314LATCH3LATCH4Q211Q212Q31Q315http://onsemi.com132

MC14042BELECTRICAL CHARACTERISTICS (Voltages Referenced to V SS )ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΖ 55 C 25 C 125 C V DDÎÎÎÎÎÎÎÎÎÎCharacteristic ÎÎÎÎÎÎÎMinÎÎÎMaxÎÎÎÎ MinÎÎÎÎÎTyp (4.) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎMaxMaxÎÎÎUnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput VoltageV in = V DD or 0“0” Level“1” LevelÎÎÎ ÎÎÎSymbol VdcV OL 5.0 —10 —15 —ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎV in = 0 or V DDInput Voltage(V O = 4.5 or 0.5 Vdc)(V O = 9.0 or 1.0 Vdc)(V O = 13.5 or 1.5 Vdc)“0” LevelV OHV IL5.010154.959.9514.950.050.050.05———0000.050.050.05ÎÎÎMin— 0.05 Vdc— 0.05— 0.05ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5.01015——————4.959.9514.955.01015———4.959.9514.95ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V O = 0.5 or 4.5 Vdc)(V O = 1.0 or 9.0 Vdc)(V O = 1.5 or 13.5 Vdc)“1” LevelV IH5.010153.57.011ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ1.53.04.0——————3.57.0112.254.506.752.755.508.251.53.04.0——————3.57.011———1.53.04.0———VdcVdcVdcOutput Drive Current(V OH = 2.5 Vdc) Source(V OH = 4.6 Vdc)(V OH = 9.5 Vdc)(V OH = 13.5 Vdc)I OH5.05.01015– 3.0– 0.64– 1.6– 4.2ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΗ———– 2.4– 0.51– 1.3– 3.4– 4.2– 0.88– 2.25– 8.8————– 1.7– 0.36– 0.9– 2.4————mAdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V OL = 0.4 Vdc) Sink(V OL = 0.5 Vdc)(V OL = 1.5 Vdc)I OL5.010150.641.64.2ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎInput CurrentI in 15 — ÎÎÎÎÎÎÎΗ±0.00001± 0.1 — ÎÎεAdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput Capacitance(V in = 0)C in—————0.511.33.40.882.258.8±ÎÎÎÎ0.1— — 5.0———7.50.360.92.4————mAdc±ÎÎÎ1.0— pFÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎQuiescent Current(Per Package)I DD5.01015———ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTotal Supply Current (5.) (6.)(Dynamic plus Quiescent,Per Package)(C L = 50 pF on all outputs allbuffers switching)I T5.01015ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ1.02.04.0———0.0020.0040.006ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ1.02.04.0I T = (1.0 µA/kHz) f + I DDI T = (2.0 µA/kHz) f + I DDI T = (3.0 µA/kHz) f + I DD4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.5. The formulas given are for the typical characteristics only at 25 C.6. To calculate total supply current at loads other than 50 pF:I T (C L ) = I T (50 pF) + (C L – 50) Vfkwhere: I T is in µA (per package), C L in pF, V = (V DD – V SS ) in volts, f in kHz is input frequency, and k = 0.004.———3060120µAdcµAdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎhttp://onsemi.com133

SWITCHING CHARACTERISTICS (7.) (C L = 50 pF, T A = 25 C)MC14042BÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCharacteristicSymbolMinTyp (8.) MaxUnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Rise and Fall Timet TLH , t THL = (1.5 ns/pF) C L + 25 nst TLH , t THL = (0.75 ns/pF) C L + 12.5 nsÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎt TLH , t THL = (0.55 ns/pF) C L + 9.5 nsPropagation Delay Time, D to Q, Qt PLH , t PHL = (1.7 ns/pF) C L + 135 nst PLH , t PHL = (0.66 ns/pF) C L + 57 nst TLH ,t THLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎt PLH , t PHL = (0.5 ns/pF) C L + 35 nst PLH ,t PHLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPropagation Delay Time, Clock to Q, Qt PLH , t PHL = (1.7 ns/pF) C L + 135 nst PLH , t PHL = (0.66 ns/pF) C L + 57 nst PLH , t PHL = (0.5 ns/pF) C L + 35 nst PLH ,t PHLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎClock Pulse Widtht WHÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎClock Pulse Rise and Fall Timet TLH ,t THLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎHold Timet hÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSetup Timet suÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ7. The formulas given are for the typical characteristics only at 25 C.ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.V DD5.010155.010155.010155.010155.010155.010155.01015—————————30010080———10050405030251005040220906022090601505040———50252000020010080440180120440180120———155.04.0——————nsnonsnsµsnsnsV DDV SSPULSEGENERATOR 156471314For Power Dissipation test, each outputis loaded with capacitance C L .16CLOCKPOLARITYD0D1D2D38Q0Q0Q1Q1Q2Q2Q3Q32310911121151f20 ns 20 ns90%50%10%DATA INPUTt PLHt PHL90%50%10%Q OUTPUTt TLHt THLt PHLQ OUTPUT90%50%10%t THL t TLHFigure 1. AC and Power Dissipation Test Circuit and Timing Diagram(Data to Output)http://onsemi.com134

MC14042BV DD16PULSEGENERATOR 1PULSEGENERATOR 256471314CLOCKPOLARITYD0D1D2D3Q0Q0Q1Q1Q2Q2Q3Q3231091112115NOTE: C L connected to output under test.8V SS20* ns 20 nsCLOCK INPUTP.G. 190%20 ns10%50%t WH90%50%DATA INPUTP.G. 2Q OUTPUT90%t PLHt suth50%10%*Input clock rise time is 20 ns except for maximum rise time test.Figure 2. AC Test Circuit and Timing Diagram(Clock to Output)http://onsemi.com135

Quad R–S LatchesThe MC14043B and MC14044B quad R–S latches are constructedwith MOS P–channel and N–channel enhancement mode devices in asingle monolithic structure. Each latch has an independent Q outputand set and reset inputs. The Q outputs are gated through three–statebuffers having a common enable input. The outputs are enabled with alogical “1” or high on the enable input; a logical “0” or lowdisconnects the latch from the Q outputs, resulting in an open circuit atthe Q outputs.• Double Diode Input Protection• Three–State Outputs with Common Enable• Outputs Capable of Driving Two Low–power TTL Loads or OneLow–Power Schottky TTL Load Over the Rated Temperature Range• Supply Voltage Range = 3.0 Vdc to 18 VdcMAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 2.)Symbol Parameter Value UnitV DD DC Supply Voltage Range –0.5 to +18.0 VV in , V out Input or Output Voltage Range(DC or Transient)–0.5 to V DD + 0.5 VI in , I outP DInput or Output Current(DC or Transient) per PinPower Dissipation,per Package (Note 3.)±10 mA500 mWT A Ambient Temperature Range –55 to +125 °CT stg Storage Temperature Range –65 to +150 °CT LLead Temperature(8–Second Soldering)260 °C2. Maximum Ratings are those values beyond which damage to the devicemay occur.3. Temperature Derating:Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 CThis device contains protection circuitry to guard against damage due to highstatic voltages or electric fields. However, precautions must be taken to avoidapplications of any voltage higher than maximum rated voltages to thishigh–impedance circuit. For proper operation, V in and V out should be constrainedto the range V SS (V in or V out ) V DD .Unused inputs must always be tied to an appropriate logic voltage level (e.g.,either V SS or V DD ). Unused outputs must be left open.http://onsemi.comPDIP–16P SUFFIXCASE 648SOIC–16D SUFFIXCASE 751BSOEIAJ–16F SUFFIXCASE 966XX = Specific Device CodeA = Assembly LocationWL or L = Wafer LotYY or Y = YearWW or W = Work WeekORDERING INFORMATIONMARKINGDIAGRAMS16Device Package ShippingMC14043BCP PDIP–16 2000/BoxMC14043BD SOIC–16 2400/BoxMC14043BDR2 SOIC–16 2500/Tape & Reel1161161MC140XXBCPAWLYYWW140XXBAWLYWWMC140XXBAWLYWWMC14043BF SOEIAJ–16 See Note 1.MC14043BFEL SOEIAJ–16 See Note 1.MC14044BCP PDIP–16 2000/BoxMC14044BD SOIC–16 2400/BoxMC14044BDR2 SOIC–16 2500/Tape & Reel1. For ordering information on the EIAJ version ofthe SOIC packages, please contact your localON Semiconductor representative.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 3136 Publication Order Number:MC14043B/D

MC14043B, MC14044BPIN ASSIGNMENTMC14043BMC14044BQ3116V DDQ3116V DDQ0215R3NC215S3R0314S3S0314R3S0413NCR0413Q0E512S2E512R2S1611R2R1611S2R1710Q2S1710Q2V SS89Q1V SS89Q1NC = NO CONNECTIONMC14043BMC14044BS0 4 32Q013Q0R0R0 4 3S0S169Q1R169Q17R112S210Q2V DD = PIN 16V SS = PIN 8NC = PIN 137S112R210Q2V DD = PIN 16V SS = PIN 8NC = PIN 211R211S214S31Q3TRUTH TABLES R EQ14R31Q3TRUTH TABLES R E Q15R35ENABLEX X 0001101011111X = Don’t CareHighImpedanceNo Change01115S35ENABLEX X 0001101011111X = Don’t CareHighImpedance010No Changehttp://onsemi.com137

MC14043B, MC14044BELECTRICAL CHARACTERISTICS (Voltages Referenced to V SS )ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΖ 55 C 25 C 125 C V DDÎÎÎÎÎÎÎÎÎÎCharacteristic ÎÎÎÎÎÎÎMinÎÎÎMaxÎÎÎÎ MinÎÎÎÎÎTyp (4.) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎMaxMaxÎÎÎUnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput VoltageV in = V DD or 0“0” Level“1” LevelÎÎÎ ÎÎÎSymbol VdcV OL 5.0 —10 —15 —ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎV in = 0 or V DDInput Voltage(V O = 4.5 or 0.5 Vdc)(V O = 9.0 or 1.0 Vdc)(V O = 13.5 or 1.5 Vdc)“0” LevelV OHV IL5.010154.959.9514.950.050.050.05———0000.050.050.05ÎÎÎMin— 0.05 Vdc— 0.05— 0.05ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5.01015——————4.959.9514.955.01015———4.959.9514.95ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V O = 0.5 or 4.5 Vdc)(V O = 1.0 or 9.0 Vdc)(V O = 1.5 or 13.5 Vdc)“1” LevelV IH5.010153.57.011ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ1.53.04.0——————3.57.0112.254.506.752.755.508.251.53.04.0——————3.57.011———1.53.04.0———VdcVdcVdcOutput Drive Current(V OH = 2.5 Vdc) Source(V OH = 4.6 Vdc)(V OH = 9.5 Vdc)(V OH = 13.5 Vdc)I OH5.05.01015– 3.0– 0.64– 1.6– 4.2ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΗ———– 2.4– 0.51– 1.3– 3.4– 4.2– 0.88– 2.25– 8.8————– 1.7– 0.36– 0.9– 2.4————mAdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V OL = 0.4 Vdc) Sink(V OL = 0.5 Vdc)(V OL = 1.5 Vdc)I OL5.010150.641.64.2ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎInput CurrentI in 15 — ÎÎÎÎÎÎÎΗ±0.00001± 0.1 — ÎÎεAdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput Capacitance(V in = 0)C in—————0.511.33.40.882.258.8±ÎÎÎÎ0.1— — 5.0———7.50.360.92.4————mAdc±ÎÎÎ1.0— pFÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎQuiescent Current(Per Package)I DD5.01015———ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTotal Supply Current (5.) (6.)(Dynamic plus Quiescent,Per Package)(C L = 50 pF on all outputs allbuffers switching)I T5.01015ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ1.02.04.0———0.0020.0040.006ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ1.02.04.0I T = (0.58 µA/kHz) f + I DDI T = (1.15 µA/kHz) f + I DDI T = (1.73 µA/kHz) f + I DD———3060120µAdcµAdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎThree–State Output LeakageÎÎÎI ÎÎÎÎTL 15 0.1ÎÎÎΗ ± — — ± 3.0ÎÎÎ µAdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCurrent0.0001ÎÎÎα ± ÎÎÎ0.14. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.5. The formulas given are for the typical characteristics only at 25 C.6. To calculate total supply current at loads other than 50 pF:I T (C L ) = I T (50 pF) + (C L – 50) VfkÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎwhere: I T is in µA (per package), C L in pF, V = (V DD – V SS ) in volts, f in kHz is input frequency, and k = 0.004.http://onsemi.com138

MC14043B, MC14044BSWITCHING CHARACTERISTICS (7.) (C L = 50 pF, T A = 25 C)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCharacteristicSymbolMin Typ (8.) Max UnitOutput Rise Timet TLH = (1.35 ns/pF) C L + 32.5 nst TLH = (0.60 ns/pF) C L + 20 nst TLH = (0.40 ns/pF) C L + 20 nsOutput Fall Timet THL = (1.35 ns/pF) C L + 32.5 nst THL = (0.60 ns/pF) C L + 20 nst THL = (0.40 ns/pF) C L + 20 nst TLHÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎt THLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPropagation Delay Timet PLH = (0.90 ns/pF) C L + 130 nst PLH = (0.36 ns/pF) C L + 57 nsÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎt PLH = (0.26 ns/pF) C L + 47 nst PHL = (0.90 ns/pF) C L + 130 nst PHL = (0.90 ns/pF) C L + 57 nst PHL = (0.26 ns/pF) C L + 47 nsSet, Set Pulse Widtht PLHt PHLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎt WÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎReset, Reset Pulse Widtht WÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎThree–State Enable/Disable Delayt PLZ ,t PHZ ,t PZL ,t PZHÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ7. The formulas given are for the typical characteristics only at 25 C.8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎV DDVdc5.010155.010155.010155.010155.010155.010155.01015————————————2001007020010070———100504010050401757560175756080403080403015080552001008020010080350175120350175120——————300160110nsnsnsnsnsnsns90%SET 10%RESETQMC14043B20 ns 20 ns20 ns 20 ns90%50%10%t THL10%t PHL50%t TLH90%50%t PLHAC WAVEFORMSV DDV SSV DDV SSV OHV OLMC14044B20 ns 20 nsV DD90%50%SET10%V SS20 ns 20 ns90%V DDRESET50%10% V SSt TLHt THLV OH90%Q50%10%V OLt PLH t PHLhttp://onsemi.com139

MC14043B, MC14044BTHREE–STATE ENABLE/DISABLE DELAYSSet, Reset, Enable, and Switch Conditions for 3–State TestsMC14043B MC14044BTest Enable S1 S2 Q S R S Rt PZH Open Closed A V DD V SS V SS V DDt PZL Closed Open B V SS V DD V DD V SSt PHZ Open Closed A V DD V SS V SS V DDt PLZ Closed Open B V SS V DD V DD V SSTOOUTPUTUNDERTESTC L50 pF1 kV DDS1S2V SSENABLE50%t PZHQ A 10%t PZLQ Bt PHZ90%t PLZ10%V DDV SSV DDV OLV OHV SShttp://onsemi.com140

The MC14046B phase locked loop contains two phase comparators,a voltage–controlled oscillator (VCO), source follower, and zenerdiode. The comparators have two common signal inputs, PCA in andPCB in . Input PCA in can be used directly coupled to large voltagesignals, or indirectly coupled (with a series capacitor) to small voltagesignals. The self–bias circuit adjusts small voltage signals in the linearregion of the amplifier. Phase comparator 1 (an exclusive OR gate)provides a digital error signal PC1 out , and maintains 90° phase shift atthe center frequency between PCA in and PCB in signals (both at 50%duty cycle). Phase comparator 2 (with leading edge sensing logic)provides digital error signals, PC2 out and LD, and maintains a 0°phase shift between PCA in and PCB in signals (duty cycle isimmaterial). The linear VCO produces an output signal VCO outwhose frequency is determined by the voltage of input VCO in and thecapacitor and resistors connected to pins C1 A , C1 B , R1, and R2. Thesource–follower output SF out with an external resistor is used wherethe VCO in signal is needed but no loading can be tolerated. The inhibitinput Inh, when high, disables the VCO and source follower tominimize standby power consumption. The zener diode can be used toassist in power supply regulation.Applications include FM and FSK modulation and demodulation,frequency synthesis and multiplication, frequency discrimination,tone decoding, data synchronization and conditioning,voltage–to–frequency conversion and motor speed control.• Buffered Outputs Compatible with MHTL and Low–Power TTL• Diode Protection on All Inputs• Supply Voltage Range = 3.0 to 18 V• Pin–for–Pin Replacement for CD4046B• Phase Comparator 1 is an Exclusive Or Gate and is Duty Cycle Limited• Phase Comparator 2 switches on Rising Edges and is not Duty CycleLimitedMAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 2.)Symbol Parameter Value UnitV DD DC Supply Voltage Range –0.5 to +18.0 VV in Input Voltage Range (All Inputs) –0.5 to V DD + 0.5 VI in DC Input Current, per Pin ±10 mAP DPower Dissipation,per Package (Note 3.)500 mWT A Operating Temperature Range –55 to +125 °CT stg Storage Temperature Range –65 to +150 °C2. Maximum Ratings are those values beyond which damage to the devicemay occur.3. Temperature Derating:Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 Chttp://onsemi.comPDIP–16P SUFFIXCASE 648SOIC–16DW SUFFIXCASE 751GSOEIAJ–16F SUFFIXCASE 966A = Assembly LocationWL or L = Wafer LotYY or Y = YearWW or W = Work WeekORDERING INFORMATIONMARKINGDIAGRAMS16Device Package ShippingMC14046BCP PDIP–16 2000/BoxMC14046BDW SOIC–16 2350/BoxMC14046BDWR2 SOIC–16 1000/Tape & Reel1. For ordering information on the EIAJ version ofthe SOIC packages, please contact your localON Semiconductor representative.1611161MC14046BCPAWLYYWW14046BAWLYYWWMC14046BAWLYWWMC14046BF SOEIAJ–16 See Note 1.MC14046BFEL SOEIAJ–16 See Note 1.This device contains protection circuitry to guardagainst damage due to high static voltages or electricfields. However, precautions must be taken to avoid applicationsof any voltage higher than maximum ratedvoltages to this high–impedance circuit. For properoperation, V in and V out should be constrained to therange V SS (V in or V out ) V DD .Unused inputs must always be tied to an appropriatelogic voltage level (e.g., either V SS or V DD ). Unused outputsmust be left open.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 5141 Publication Order Number:MC14046B/D

MC14046BBLOCK DIAGRAMPIN ASSIGNMENTV DD = PIN 16V SS = PIN 8PCA in 14PCB inVCO inINH395SELF BIASCIRCUITV SSPHASECOMPARATOR 1PHASECOMPARATOR 2VOLTAGECONTROLLEDOSCILLATOR(VCO)SOURCE FOLLOWER2 PC1 out13 PC2 out1 LD4 VCO out11 R112 R26 C1 A7 C1 B10 SF out15 ZENERLDPC1 outPCB inVCO outINHC1 AC1 BV SS12345678161514131211109V DDZENERPCA inPC2 outR2R1SF outVCO inELECTRICAL CHARACTERISTICS (Voltages Referenced to V SS )ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎV DDÎÎÎÎÎΖ 55 C 25 C 125 C CharacteristicMin MaxMin TypUnitÎÎÎÎÎÎÎÎÎÎÎÎÎV ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOL 5.0 — 0.05 — 0 0.05 — 0.05 VdcOutput VoltageV in = V DD or 0“0” LevelÎÎÎ ÎÎÎSymbol Vdc10 —15 —ÎÎÎ ÎÎÎ ÎÎÎMax Min 0.05 — 0.050.05 — 0.05ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎV OH ÎÎÎ5.0ÎÎÎÎ4.95ÎÎΗÎÎÎÎ4.95ÎÎÎ5.0ÎÎΗÎÎÎ4.95ÎÎΗVdcÎÎÎV in = 0 or V DDInput Voltage (4.)(V O = 4.5 or 0.5 Vdc)(V O = 9.0 or 1.0 Vdc)(V O = 13.5 or 1.5 Vdc)“1” Level“0” LevelV IL10155.010159.9514.95———ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V O = 0.5 or 4.5 Vdc) “1” ÎÎÎLevel V IH 5.0ÎÎÎÎ3.5 ÎÎÎ ÎÎΗ ÎÎÎÎ3.5ÎÎÎ2.75 — ÎÎÎ 3.5ÎÎÎ —ÎÎÎÎÎÎ VdcÎÎÎÎÎÎÎÎÎÎÎ(V O ÎÎÎÎ=ÎÎÎ1.0ÎÎÎorÎÎÎ9.0ÎÎÎVdc)ÎÎÎ10ÎÎÎÎ7.0ÎÎΗÎÎÎ ÎÎÎ7.0 5.50 — 7.0 —(V O = 1.5 or 13.5 Vdc)1511ÎÎÎÎÎÎÎÎÎÎÎOutput Drive CurrentÎÎÎI ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎOH mAdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V OH = 2.5 Vdc) Source(V OH = 4.6 Vdc)(V OH = 9.5 Vdc)(V OH = 13.5 Vdc)5.05.01015– 1.2– 0.25– 0.62– 1.8ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V OL = 0.4 Vdc) Sink(V OL = 0.5 Vdc)(V OL = 1.5 Vdc)I OL5.010150.641.64.2ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ0.050.05——1.53.04.0———————9.9514.95———11– 1.0– 0.2– 0.5– 1.50010152.254.506.758.25– 1.7– 0.36– 0.9– 3.5——1.53.04.0—————9.9514.95———11– 0.7– 0.14– 0.35ÎÎÎÎÎÎÎÎÎÎÎInput CurrentI in± 0.1 ÎÎΗ 15ÎÎα0.00001 —ÎÎÎα 0.1 — ± µAdcÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎ1.0ÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput Capacitance— — ÎÎÎ ÎÎÎ ÎÎÎÎÎΗ ÎÎÎ — — — pFÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎC inÎÎÎÎÎÎÎÎÎÎÎQuiescent ÎÎÎCurrentI DD ÎÎÎ5.0 ÎÎÎΗ ÎÎÎ ÎÎÎ5.0 ÎÎÎΗ 0.005 ÎÎÎ 5.0 ÎÎΗ ÎÎÎ150ÎÎεAdc(Per Package) InhÎÎÎÎÎÎÎÎÎÎÎ= PCA in = V DD ,ÎÎÎ10ÎÎÎÎÎΗÎÎÎ10ÎÎÎΗÎÎÎ0.010ÎÎÎÎ10ÎÎΗÎÎÎ ÎÎÎ300Zener = VCO in = 0 V, PCB in = V DDor 0 V, I out = 0 µATotal Supply Current (5.)(Inh = “0”, f o = 10 kHz, C L = 50 pF,R1 = 1.0 MΩ, R2 = R SF = ∞,15————0.511.33.40.882.258.8———– 1.10.360.92.4ÎÎÎ5.0 ÎÎÎ7.5ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎand 50% Duty Cycle)I T5.010154. Noise immunity specified for worst–case input combination.Noise Margin for both “1” and “0” level = 1.0 Vdc min @ V DD = 5.0 Vdc2.0 Vdc min @ V DD = 10 Vdc2.5 Vdc min @ V DD = 15 VdcÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ20—0.01520I T = (1.46 µA/kHz) f + I DDI T = (2.91 µA/kHz) f + I DDI T = (4.37 µA/kHz) f + I DD5. To Calculate Total Current in General:VCO in – 1.65I T 2.2 x V DD. + V DD – 1.35.3/4 VCO in – 1.65 3/4+ 1.6 x. . + 1 x 10 –3 (C L + 9) V DD f +R1R2R SF1 x 10 –1 V 100% Duty Cycle of PCA in2 DD.. + IQ100where: I T in µA, C L in pF, VCO in , V DD in Vdc, f in kHz, andR1, R2, R SF in MΩ, C L on VCO out .———1.53.04.0————————600VdcmAdcmAdchttp://onsemi.com142

MC14046BELECTRICAL CHARACTERISTICS (6.) (C L = 50 pF, T A = 25°C)CharacteristicMinimum ÎÎÎÎMaximumÎÎÎV DDVdc Device ÎÎÎÎTypical ÎÎÎDevice UnitsSymbolÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎt TLH ÎÎÎÎ ÎÎÎÎÎÎnsÎÎÎÎÎÎÎÎÎOutput Rise Timet TLH = (3.0 ns/pF) C L + 30 nst TLH = (1.5 ns/pF) C L + 15 nst TLH = (1.1 ns/pF) C L + 10 nsÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎt THL ÎÎÎÎ ÎÎÎÎÎÎnsÎÎÎÎÎÎÎÎÎOutput Fall Timet THL = (1.5 ns/pF) C L + 25 nst THL = (0.75 ns/pF) C L + 12.5 nst THL = (0.55 ns/pF) C L + 9.5 nsPHASE COMPARATORS 1 and 2Input Resistance — PCA inÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎRÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎin 5.01.02.0—MΩ5.010155.010151015——————0.20.1180906510050370.40.23501501101757555——ÎÎÎÎÎÎÎÎÎÎÎÎÎÎΗ PCB in R inÎÎÎÎÎ15 ÎÎÎÎ150 ÎÎÎÎ1500 ÎÎÎÎ — MΩÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMinimum Input SensitivityÎÎÎÎ V ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎin 5.0 — 200 300 mV p–pAC Coupled — PCA inC series = 1000 pF, f = 50 kHzÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΗÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5 to 15See Noise ImmunityDC Coupled — PCA in , PCB in1015——4007006001050ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVOLTAGE CONTROLLED OSCILLATOR (VCO)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMaximumÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎFrequencyf max 5.0 0.5 0.7 — MHz(VCO in = V DD , C1 = 50 pFR1 = 5.0 kΩ, and R2 = ∞)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTemperature — Frequency Stability—ÎÎÎÎÎ5.0ÎÎÎΗÎÎÎÎ0.12ÎÎÎΗÎÎÎ%/ CÎÎÎÎ(R2 = ∞ )ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΗ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ%Linearity (R2 = ∞ )(VCO in = 2.5 V ± 0.3 V, R1 > 10 kΩ)(VCO in = 5.0 V ± 2.5 V, R1 > 400 kΩ)(VCO in = 7.5 V ± 5.0 V, R1 ≥ 1000 kΩ)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Duty CycleÎÎÎÎ — ÎÎÎÎÎ — ÎÎÎÎ 50 ÎÎÎÎ — ÎÎÎ %ÎÎÎÎInput Resistance — VCO in101510155.010151.01.4—————1.41.90.040.0151.01.01.0———————5 to ÎÎÎÎ15ÎÎÎÎ1500 MΩR in 15 ÎÎÎÎ150 ÎÎÎÎÎÎÎÎΗ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSOURCE–FOLLOWERÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΗ 5.0VÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOffset Voltage(VCO in minus SF out , RSF > 500 kΩ)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎLinearityÎÎÎÎ — ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ%(VCO in = 2.5 V ± 0.3 V, R SF > 50 kΩ)(VCO in = 5.0 V ± 2.5 V, R SF > 50 kΩ)(VCO in = 7.5 V ± 5.0 V, R SF > 50 kΩ)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ10155.01015——————1.651.651.650.10.60.82.22.22.2———ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎZENER DIODEÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎZener Voltage (I ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎz = 50 µA)— 6.7 7.0 VV Z7.3 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎDynamic Resistance (I z = 1.0 ÎÎÎÎmA)R ÎÎÎÎÎZ ÎÎÎΗ ÎÎÎΗ ÎÎÎÎ100 ÎÎΗ Ω6. The formula given is for the typical characteristics only.ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎhttp://onsemi.com143

MC14046BInput StagePCA inXXPHASE COMPARATOR 100 0111 10PC1 out 0 1Input StagePHASE COMPARATOR 2000000PCA inXXPCB in01 1010 0101 101111113–StatePC2 out 0 1Output DisconnectedLD (Lock Detect) 0 10Refer to Waveforms in Figure 3.Figure 1. Phase Comparators State DiagramsCharacteristicNo signal on input PCA in .Using Phase Comparator 1VCO in PLL system adjusts to centerfrequency (f 0 ).Using Phase Comparator 2ÎÎÎÎÎÎÎÎÎÎÎVCO in PLL system adjusts to minimumfrequency (f min ).ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPhase angle between PCA in and PCB in .90° at center frequency (f 0 ), approaching0 and 180° at ends of lock range (2f L )Always 0 in lock (positive rising edges).ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎLocks on harmonics of center frequency.YesNoÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSignal input noise rejection.HighLowLock frequency range (2f L ).The frequency range of the input signal on which the loop will stay locked if it wasinitially in lock; 2f L = full VCO frequency range = f max – f min .ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCapture frequency range (2f C ).The frequency range of the input signal on which the loop will lock if it was initiallyout of lock.ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎDepends on low–pass filter characteristics(see Figure 3). f C f Lf C = f LÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCenter frequency (f 0 ).The frequency of VCO out , when VCO in = 1/2 V DDÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVCO output frequency (f).f min =1(V CO input = V SS )R 2 (C 1 + 32 pF)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎNote: These equations are intended to bea design guide. Since calculated componentvalues may be in error by as much as aÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎfactor of 4, laboratory experimentation maybe required for fixed designs. Part to partÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎWhere: 10K R 1 1 M10K RÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ2 1 Mfrequency variation with identical passive100pF C 1 .01 µFcomponents is typically less than ± 20%.1f max =R1 (C 1 + 32 pF)+ f min(V CO input = V DD )ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎFigure 2. Design InformationÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎhttp://onsemi.com144ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MC14046B9 SOURCE 10FOLLOWERR SFSF outPCA in 14@ FREQUENCY f′3PCB inPHASECOMPARATORVCO inEXTERNAL2 OR 139LOW–PASSVCO4PC1 out FILTER11 12 6 7ORCI A CI BPC2 out R1 R2CIEXTERNAL÷ NCOUNTERVCO out@ FREQUENCY Nf′ = f(a)INPUTR3C2OUTPUT2fC12 2fLR3 C2Typical Low–Pass Filters(a)INPUTR3R4C2OUTPUTTypically:R4 C2 6Nfmax –N2 f(R3 3, 000) C2 100Nffmax2–R 4 C2∆ f = f max – f minNOTE: Sometimes R3 is split into two series resistors each R3 ÷ 2. A capacitor C C is then placed from the midpoint to ground. The value forC C should be such that the corner frequency of this network does not significantly affect ω n . In Figure B, the ratio of R3 to R4 sets thedamping, R4 (0.1)(R3) for optimum results.Definitions:N = Total division ratio in feedback loopKφ = V DD /π for Phase Comparator 1Kφ = V DD /4 π for Phase Comparator 2KVCO 2 f VCOVDD –2V2 for a typical design ωfrn(at phase detector input)10ζ 0.707Filter An 2 KKVCONR 3C2 N n2K KVCOF(s) 1R 3 C 2 S 1LOW–PASS FILTERFilter BK KVCOn 2 NC 2(R3 R4) 0.5 n (R 3 C 2 NK KVCO )R3C2S 1F(s) S(R 3 C 2 R 4 C 2 ) 1WaveformsPhase Comparator 1 Phase Comparator 2PCA inV DDV SSPCA inV DDV SSPCB inPC1 outVCO inV OHV OLV OHV OLV OHV OLPCB inPC2 outVCO inNote: for further information, see:(1) F. Gardner, “Phase–Lock Techniques”, John Wiley and Son, New York, 1966.(2) G. S. Moschytz, “Miniature RC Filters Using Phase–Locked Loop”, BSTJ, May, 1965.(3) Garth Nash, “Phase–Lock Loop Design Fundamentals”, AN–535, Motorola Inc.(4) A. B. Przedpelski, “Phase–Locked Loop Design Articles”, AR254, reprinted by Motorola Inc.LDV OHV OLV OHV OLV OHV OLV OHV OLFigure 3. General Phase–Locked Loop Connections and Waveformshttp://onsemi.com145

The MC14049B Hex Inverter/Buffer and MC14050B NoninvertingHex Buffer are constructed with MOS P–Channel and N–Channelenhancement mode devices in a single monolithic structure. Thesecomplementary MOS devices find primary use where low powerdissipation and/or high noise immunity is desired. These devicesprovide logic level conversion using only one supply voltage, V DD .The input–signal high level (V IH ) can exceed the V DD supplyvoltage for logic level conversions. Two TTL/DTL loads can be drivenwhen the devices are used as a CMOS–to–TTL/DTL converter (V DD= 5.0 V, V OL 0.4 V, I OL ≥ 3.2 mA).Note that pins 13 and 16 are not connected internally on thesedevices; consequently connections to these terminals will not affectcircuit operation.• High Source and Sink Currents• High–to–Low Level Converter• Supply Voltage Range = 3.0 V to 18 V• V IN can exceed V DD• Meets JEDEC B Specifications• Improved ESD Protection On All InputsMAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 2.)Symbol Parameter Value UnitV DD DC Supply Voltage Range –0.5 to +18.0 VV in Input Voltage Range(DC or Transient)–0.5 to +18.0 VV outI inI outP DOutput Voltage Range(DC or Transient)Input Current(DC or Transient) per PinOutput Current(DC or Transient) per PinPower Dissipation,per Package (Note 3.)(Plastic)(SOIC)–0.5 to V DD + 0.5 V±10 mA±45 mA825740T A Ambient Temperature Range –55 to +125 °CT stg Storage Temperature Range –65 to +150 °CT LLead Temperature(8–Second Soldering)mW260 °C2. Maximum Ratings are those values beyond which damage to the devicemay occur.3. Temperature Derating: See Figure 3.This device contains protection circuitry to protect the inputs against damagedue to high static voltages or electric fields referenced to the V SS pin only. Extraprecautions must be taken to avoid applications of any voltage higher than themaximum rated voltages to this high–impedance circuit. For proper operation, theranges V SS ≤ V in ≤ 18 V and V SS ≤ V out ≤ V DD are recommended.Unused inputs must always be tied to an appropriate logic voltage level (e.g.,either V SS or V DD ). Unused outputs must be left open.http://onsemi.comPDIP–16P SUFFIXCASE 648SOIC–16D SUFFIXCASE 751BTSSOP–16DT SUFFIXCASE 948FSOEIAJ–16F SUFFIXCASE 9661XX = Specific Device CodeA = Assembly LocationWL or L = Wafer LotYY or Y = YearWW or W = Work WeekORDERING INFORMATIONMARKINGDIAGRAMS16116MC140XXBCPAWLYYWW140XXBAWLYWW1 16Device Package ShippingMC14049BCP PDIP–16 2000/BoxMC14049BD SOIC–16 2400/BoxMC14049BDR2 SOIC–16 2500/Tape & Reel1. For ordering information on the EIAJ version ofthe SOIC packages, please contact your localON Semiconductor representative.16MC140XXBAWLYWWMC14049BF SOEIAJ–16 See Note 1.MC14050BCP PDIP–16 2000/BoxMC14050BD SOIC–16 2400/BoxMC14050BDR2 SOIC–16 2500/Tape & ReelMC14050BDTEL TSSOP–16 2000/Tape & ReelMC14050BF SOEIAJ–16 See Note 1.MC14050BFEL SOEIAJ–16 See Note 1.1140XXBALYW© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 3146 Publication Order Number:MC14049B/D

MC14049B, MC14050BPIN ASSIGNMENTV DD116NCOUT A215OUT FIN A314IN FOUT B413NC512OUT EIN BLOGIC DIAGRAMOUT C611IN EIN C710OUT DV SS89IN DMC14049BMC14050B3232545476769109101112111214 15NC = PIN 13, 16V SS = PIN 8V DD = PIN 114 15NC = PIN 13, 16V SS = PIN 8V DD = PIN 1http://onsemi.com147

MC14049B, MC14050BELECTRICAL CHARACTERISTICS (Voltages Referenced to V SS )ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΖ 55 C + 25 C + 125 C V DDÎÎÎÎÎÎÎÎÎÎCharacteristic ÎÎÎÎÎÎÎMinÎÎÎMaxÎÎÎÎ MinÎÎÎÎÎTyp (4.) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎMaxMaxÎÎÎUnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput VoltageV in = V DD“0” Level“1” LevelÎÎÎ ÎÎÎSymbol VdcV OL 5.0 —10 —15 —ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎV in = 0Input Voltage “0” Level(V O = 4.5 Vdc)(V O = 9.0 Vdc)(V O = 13.5 Vdc)V OHV IL5.010154.959.9514.950.050.050.05———0000.050.050.05ÎÎÎMin— 0.05 Vdc— 0.05— 0.05ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5.01015——————4.959.9514.955.01015———4.959.9514.95ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V O = 0.5 Vdc)(V O = 1.0 Vdc)(V O = 1.5 Vdc)“1” LevelV IH5.010153.57.011ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ1.53.04.0——————3.57.0112.254.506.752.755.508.251.53.04.0——————3.57.011———1.53.04.0———VdcVdcVdcOutput Drive Current(V OH = 2.5 Vdc) Source(V OH = 9.5 Vdc)(V OH = 13.5 Vdc)I OH5.01015– 1.6– 1.6– 4.7ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΗ——– 1.25– 1.30– 3.75– 2.5– 2.6– 10———– 1.0– 1.0– 3.0———mAdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V OL = 0.4 Vdc) Sink(V OL = 0.5 Vdc)(V OL = 1.5 Vdc)I OL5.010153.751030ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΗ——3.28.0246.01640——2.66.619———mAdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput Current ÎÎÎÎ I inÎÎÎ 15 ÎÎΗ ÎÎÎ ± 0.1ÎÎÎÎ — ÎÎÎ ÎÎÎ — ÎÎÎ ± 1.0ÎÎÎ µAdcÎÎÎÎÎÎÎÎÎÎInput Capacitance (V in = ÎÎÎÎÎÎ0)ÎÎΗ ÎÎÎ —ÎÎÎΗ ÎÎΗ ÎÎÎÎ10 ÎÎÎ20 ÎÎΗ ÎÎΗ pFC inQuiescent Current (Per ÎÎÎÎPackage) I DD 5.01015———± 0.1 ÎÎα0.00001ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTotal Supply Current (5.) (6.)(Dynamic plus Quiescent,per package)(C L = 50 pF on all outputs, allÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎbuffers switchingI T5.010151.02.04.0———0.0020.0040.006ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ1.02.04.0I T = (1.8 µA/kHz) f + I DDI T = (3.5 µA/kHz) f + I DDI T = (5.3 µA/kHz) f + I DD4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.5. The formulas given are for the typical characteristics only at + 25 C6. To calculate total supply current at loads other than 50 pF:I T (C L ) = I T (50 pF) + (C L – 50) VfkWhere: I T is in µA (per Package), C L in pF, V = (V DD – V SS ) in volts, f in kHz is input frequency and k = 0.002.———3060120µAdcµAdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎhttp://onsemi.com148

MC14049B, MC14050BAC SWITCHING CHARACTERISTICS (7.) (C L = 50 pF, T A = + 25 C)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCharacteristicÎÎÎÎSymbolMin Typ (8.) ÎÎÎMaxÎÎÎÎUnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Rise Timet TLH = (0.7 ns/pF) C L + 65 nst TLH = (0.25 ns/pF) C L + 37.5 nst TLH = (0.2 ns/pF) C L + 30 nst TLHÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Fall Timet THL = (0.2 ns/pF) C L + 30 nst THL = (0.06 ns/pF) C L + 17 nst THL = (0.04 ns/pF) C L + 13 nst THLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPropagation Delay Timet PLH = (0.33 ns/pF) C L + 63.5 nst PLH = (0.19 ns/pF) C L + 30.5 nst PLH = (0.06 ns/pF) C L + 27 nst PLHÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPropagation Delay Timet PHL = (0.2 ns/pF) C L + 30 nst PHL = (0.1 ns/pF) C L + 15 nst PHL = (0.05 ns/pF) C L + 12.5 nst PHLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ7. The formulas given are for the typical characteristics only at 25 C.8. Data labeled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎV DDVdc5.010155.010155.010155.01015————————————100504040201580403040201516080606040301408060804030nsnsnsnsMC14049B MC14050B MC14049B MC14050BV DDV DDV DDV DD1111I OH I OLI OLV OH V OLV OLV SS8 V8SS8 V SSV8 SSI OHV OHV DS = V OH – V DDV DD = V OL0160I OH , OUTPUT SOURCE CURRNT (mAdc)–10–20–30–40V GS = 10 VdcV GS = 15 VdcV GS = 5.0 VdcMAXIMUM CURRENT LEVELI OL , OUTPUT SINK CURRENT (mAdc)1208040V GS = 15 VdcV GS = 10 VdcMAXIMUM CURRENT LEVELV GS = 5.0 Vdc–50– 10 – 8.0 – 6.0 – 4.0 – 2.0 0V DS , DRAIN–TO–SOURCE VOLTAGE (Vdc)Figure 1. Typical Output Source Characteristics0 0 2.0 4.0 6.0 8.0 10V DS , DRAIN–TO–SOURCE VOLTAGE (Vdc)Figure 2. Typical Output Sink Characteristicshttp://onsemi.com149

MC14049B, MC14050BP D , MAXIMUM POWER DISSIPATION (mW)PER PACKAGE120011001000900825800740700600500400300200100025(P) PDIP(D) SOIC50 75 100 125T A , AMBIENT TEMPERATURE (°C)150175175 mW (P)120 mW (D)Figure 3. Ambient Temperature Power Derating20 ns 20 nsV DDINPUT90%50%10%V DDV SSPULSEGENERATOR1#V in8 V SS#Invert on MC14049B onlyC LV outt PHLOUTPUTMC14049Bt PLHt PHLOUTPUTMC14050Bt TLH90%50%10%t THL90%50%10%t PLHt TLHt PHLV OHV OLV OHV OLt THLFigure 4. Switching Time Test Circuit and Waveformshttp://onsemi.com150

The MC14049UB hex inverter/buffer is constructed with MOSP–channel and N–channel enhancement mode devices in a singlemonolithic structure. This complementary MOS device finds primaryuse where low power dissipation and/or high noise immunity isdesired. This device provides logic–level conversion using only onesupply voltage, V DD . The input–signal high level (V IH ) can exceed theV DD supply voltage for logic–level conversions. Two TTL/DTLLoads can be driven when the device is used as CMOS–to–TTL/DTLconverters (V DD = 5.0 V, V OL 0.4 V, I OL ≥ 3.2 mA). Note that pins13 and 16 are not connected internally on this device; consequentlyconnections to these terminals will not affect circuit operation.• High Source and Sink Currents• High–to–Low Level Converter• Supply Voltage Range = 3.0 V to 18 V• Meets JEDEC UB Specifications• V IN can exceed V DD• Improved ESD Protection on All InputsMAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 2.)Symbol Parameter Value UnitV DD DC Supply Voltage Range –0.5 to +18.0 VV in Input Voltage Range(DC or Transient)–0.5 to +18.0 VV outI inI outP DOutput Voltage Range(DC or Transient)Input Current(DC or Transient) per PinOutput Current(DC or Transient) per PinPower Dissipation,per Package (Note 3.)PlasticSOIC–0.5 to V DD +0.5 V±10 mA+45 mA825740T A Ambient Temperature Range –55 to +125 °CT stg Storage Temperature Range –65 to +150 °CT LLead Temperature(8–Second Soldering)mW260 °C2. Maximum Ratings are those values beyond which damage to the devicemay occur.3. Temperature Derating:All Packages: See Figure 4.This device contains circuitry to protect the inputs against damage due to highstatic voltages or electric fields referenced to the V SS pin, only. Extra precautionsmust be taken to avoid applications of any voltage higher than the maximum ratedvoltages to this high–impedance circuit. For proper operation, the ranges V SS V in 18 V and V SS V out V DD are recommended.Unused inputs must always be tied to an appropriate logic voltage level (e.g.,either V SS or V DD ). Unused outputs must be left open.http://onsemi.comPDIP–16P SUFFIXCASE 648SOIC–16D SUFFIXCASE 751BTSSOP–16DT SUFFIXCASE 948FSOEIAJ–16F SUFFIXCASE 966A = Assembly LocationWL or L = Wafer LotYY or Y = YearWW or W = Work WeekORDERING INFORMATIONMARKINGDIAGRAMSDevice Package ShippingMC14049UBCP PDIP–16 2000/BoxMC14049UBD SOIC–16 2400/BoxMC14049UBDR2 SOIC–16 2500/Tape & Reel1. For ordering information on the EIAJ version ofthe SOIC packages, please contact your localON Semiconductor representative.16MC14049UBCPAWLYYWW116116114049UAWLYWWMC14049UAWLYWWMC14049UBDT TSSOP–16 96/RailMC14049UBDTR2 TSSOP–16162500/Tape & ReelMC14049UBF SOEIAJ–16 See Note 1.MC14049UBFEL SOEIAJ–16 See Note 1.114049UALYW© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 3151 Publication Order Number:MC14049UB/D

MC14049UBPIN ASSIGNMENTV DD 1 16 NCOUT A 2 15 OUT FLOGIC DIAGRAMMC14049UB32CIRCUIT SCHEMATIC(1/6 OF CIRCUIT SHOWN)V DDIN AOUT B341413IN FNC54MC14049UBIN BNC = NO CONNECTIONOUT C561211OUT EIN E76IN C710OUT D910V SS89IN D111214 15NC = PIN 13, 16V SS = PIN 8V DD = PIN 1V SSELECTRICAL CHARACTERISTICS (Voltages Referenced to V SS )ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΖ 55 C 25 C 125 C V DDÎÎÎÎÎÎÎÎÎÎCharacteristic ÎÎÎÎÎÎÎMinÎÎÎMaxÎÎÎÎ MinÎÎÎÎÎTyp (4.) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎMaxMaxÎÎÎUnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput VoltageV in = V DD or 0“0” Level“1” LevelÎÎÎ ÎÎÎSymbol VdcV OL 5.0 —10 —15 —ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎV in = 0 or V DDInput Voltage(V O = 4.5 Vdc)(V O = 9.0 Vdc)(V O = 13.5 Vdc)“0” LevelV OHV IL5.010154.959.9514.950.050.050.05———0000.050.050.05ÎÎÎMin— 0.05 Vdc— 0.05— 0.05ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5.01015——————4.959.9514.955.01015———4.959.9514.95ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V O = 0.5 Vdc)(V O = 1.0 Vdc)(V O = 1.5 Vdc)“1” LevelV IH5.010154.08.012.5ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ1.02.02.5——————4.08.012.52.254.506.752.755.508.251.02.02.5——————4.08.012.5———1.02.02.5———VdcVdcVdcOutput Drive Current(V OH = 2.5 Vdc) Source(V OH = 9.5 Vdc)(V OH = 13.5 Vdc)I OH5.01015– 1.6– 1.6– 4.7ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΗ——– 1.25– 1.3– 3.75– 2.5– 2.6– 10———– 1.0– 1.0– 3.0———mAdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V OL = 0.4 Vdc) Sink(V OL = 0.5 Vdc)(V OL = 1.5 Vdc)I OL5.010153.751030ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΗ——3.28.0246.01640———2.66.619———mAdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput Current ÎÎÎÎ I inÎÎÎ 15 ÎÎΗ ÎÎÎ ± 0.1ÎÎÎÎ — ÎÎÎ ÎÎÎ — ÎÎÎ ± 1.0ÎÎÎ µAdcÎÎÎÎÎÎÎÎÎÎInput Capacitance (V in = ÎÎÎÎÎÎ0)ÎÎΗ ÎÎÎ —ÎÎÎΗ ÎÎΗ ÎÎÎÎ10 ÎÎÎ20 ÎÎΗ ÎÎΗ pFQuiescent Current(Per Package)C inI DD5.01015———± 0.1 ÎÎα0.00001ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTotal Supply Current (5.) (6.)(Dynamic plus Quiescent,Per Package)(C L = 50 pF on all outputs, allÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎbuffers switching)I T5.010151.02.04.0———0.0020.0040.006ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ1.02.04.0I T = (1.8 µA/kHz) f + I DDI T = (3.5 µA/kHz) f + I DDI T = (5.3 µA/kHz) f + I DD4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.5. The formulas given are for the typical characteristics only at 25 C.6. To calculate total supply current at loads other than 50 pF:I T (C L ) = I T (50 pF) + (C L – 50) Vfkwhere: I T is in µA (per package), C L in pF, V = (V DD – V SS ) in volts, f in kHz is input frequency, and k = 0.002.———3060120µAdcµAdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎhttp://onsemi.com152

MC14049UBSWITCHING CHARACTERISTICS (7.) (C L = 50 pF, T A = 25 C)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCharacteristicÎÎÎÎSymbolMin Typ (8.) ÎÎÎMaxÎÎÎÎUnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Rise Timet TLH = (0.8 ns/pF) C L + 60 nst TLH = (0.3 ns/pF) C L + 35 nst TLH = (0.27 ns/pF) C L + 26.5 nst TLHÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Fall Timet THL = (0.3 ns/pF) C L + 25 nst THL = (0.12 ns/pF) C L + 14 nst THL = (0.1 ns/pF) C L + 10 nst THLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPropagation Delay Timet PLH = (0.38 ns/pF) C L + 61 nst PLH = (0.20 ns/pF) C L + 30 nst PLH = (0.11 ns/pF) C L + 24.5 nst PLHÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPropagation Delay Timet PHL = (0.38 ns/pF) C L + 11 nst PHL = (0.12 ns/PF) C L + 9 nst PHL = (0.11 ns/pF) C L + 4.5 nst PHLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ7. The formulas given are for the typical characteristics only at 25 C.8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎV DDVdc5.010155.010155.010155.01015————————————1005040402015804030301510160100606040301206550603020nsnsnsns18V out , OUTPUT VOLTAGE (Vdc)15105V DD = 15 VdcV DD = 10 VdcV DD = 5 Vdc–55°C+125°C510V in , INPUT VOLTAGE (Vdc)1518Figure 1. Typical Voltage Transfer Characteristics versus Temperaturehttp://onsemi.com153

MC14049UBV DD1V DD18V SSI OHV OHV DS = V OH – V DD8V SSI OLV OLV DD = V OL0160I OH , OUTPUT SOURCE CURRNT (mAdc)–10–20–30–40V GS = 10 VdcV GS = 15 VdcV GS = 5.0 VdcMAXIMUM CURRENT LEVELI OL , OUTPUT SINK CURRENT (mAdc)1208040V GS = 15 VdcV GS = 10 VdcMAXIMUM CURRENT LEVELV GS = 5.0 Vdc–50– 10 – 8.0 – 6.0 – 4.0 – 2.0 0V DS , DRAIN–TO–SOURCE VOLTAGE (Vdc)Figure 2. Typical Output Source Characteristics0 0 2.0 4.0 6.0 8.0 10V DS , DRAIN–TO–SOURCE VOLTAGE (Vdc)Figure 3. Typical Output Sink CharacteristicsV DD1P D , MAXIMUM POWER DISSIPATION (mW)PER PACKAGE120011001000900825800740700600500400300200100025(P) PDIP(D) SOIC50 75 100 125T A , AMBIENT TEMPERATURE (°C)150175175 mW (P)120 mW (D)PULSEGENERATORV in8V SS20 ns 20 nsINPUTt PHLOUTPUT90%50%10%90%50%10%t THLC Lt PLHt TLHV outV DDV SSV OHV OLFigure 4. Ambient Temperature Power DeratingFigure 5. Switching Time Test Circuitand Waveformshttp://onsemi.com154

The MC14051B, MC14052B, and MC14053B analog multiplexersare digitally–controlled analog switches. The MC14051B effectivelyimplements an SP8T solid state switch, the MC14052B a DP4T, andthe MC14053B a Triple SPDT. All three devices feature low ONimpedance and very low OFF leakage current. Control of analogsignals up to the complete supply voltage range can be achieved.• Triple Diode Protection on Control Inputs• Switch Function is Break Before Make• Supply Voltage Range = 3.0 Vdc to 18 Vdc• Analog Voltage Range (V DD – V EE ) = 3.0 to 18 VNote: V EE must be V SS• Linearized Transfer Characteristics• Low–noise – 12 nV/√Cycle, f ≥ 1.0 kHz Typical• Pin–for–Pin Replacement for CD4051, CD4052, and CD4053• For 4PDT Switch, See MC14551B• For Lower R ON , Use the HC4051, HC4052, or HC4053 High–SpeedCMOS DevicesMAXIMUM RATINGS (Note 1.)Symbol Parameter Value UnitV DD DC Supply Voltage (Referencedto V EE , V SS ≥ V EE )–0.5 to +18.0 VV in , V outI inInput or Output Voltage Range(DC or Transient) (Referen–ced to V SS for Control Inputsand V EE for Switch I/O)Input Current (DC or Transient)per Control Pin–0.5 to V DD + 0.5 V±10 mAI SW Switch Through Current ±25 mAP DPower Dissipation,per Package (Note 2.)500 mWT A Ambient Temperature Range –55 to +125 °CT stg Storage Temperature Range –65 to +150 °CT LLead Temperature(8–Second Soldering)260 °C1. Maximum Ratings are those values beyond which damage to the devicemay occur.2. Temperature Derating:Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 Chttp://onsemi.comPDIP–16P SUFFIXCASE 648SOIC–16D SUFFIXCASE 751BTSSOP–16DT SUFFIXCASE 948FSOEIAJ–16F SUFFIXCASE 966MARKINGDIAGRAMS16XX = Specific Device CodeA = Assembly LocationWL or L = Wafer LotYY or Y = YearWW or W = Work Week1161161MC140XXBCPAWLYYWW140XXBAWLYWW16ORDERING INFORMATION140XXBALYWMC140XXBAWLYWWSee detailed ordering and shipping information in the packagedimensions section on page 163 of this data sheet.1This device contains protection circuitry to guard against damage due to highstatic voltages or electric fields. However, precautions must be taken to avoidapplications of any voltage higher than maximum rated voltages to thishigh–impedance circuit. For proper operation, V in and V out should be constrainedto the range V SS (V in or V out ) V DD .Unused inputs must always be tied to an appropriate logic voltage level (e.g.,either V SS , V EE or V DD ). Unused outputs must be left open.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 3155 Publication Order Number:MC14051B/D

MC14051B, MC14052B, MC14053BMC14051B8–Channel AnalogMultiplexer/DemultiplexerMC14052BDual 4–Channel AnalogMultiplexer/DemultiplexerMC14053BTriple 2–Channel AnalogMultiplexer/DemultiplexerCONTROLSSWITCHESIN/OUT611109131415121524INHIBITABCX0X1XX2X3X4X5X6X73COMMONOUT/INCONTROLSSWITCHESIN/OUT6109121415111524INHIBITABX0X1X2X3Y0Y1Y2Y3XY133COMMONSOUT/INCONTROLSSWITCHESIN/OUT61110912132153INHIBITABCX0X1Y0Y1Z0Z1XYZ14154COMMONSOUT/INV DD = PIN 16V SS = PIN 8V EE = PIN 7V DD = PIN 16V SS = PIN 8V EE = PIN 7V DD = PIN 16V SS = PIN 8V EE = PIN 7Note: Control Inputs referenced to V SS , Analog Inputs and Outputs reference to V EE . V EE must be ≤ V SS .X4X6XX7X5INHV EEV SSPIN ASSIGMENTMC14051B MC14052B MC14053B121615V DDX2Y0Y2121615V DDX2Y1Y01216153 14 X1Y 3 14 X1Z1 3 144 13 X0Y3 4 13 XZ 4 135 12 X3Y1 5 12 X0Z0 5 126 11 AINH 6 11 X3INH 6 117 10 BV EE 7 10 AV EE 7 108 9 CV SS 8 9 BV SS 8 9V DDYXX1X0ABChttp://onsemi.com156

– 55 ÎÎÎÎÎÎÎC 25 ÎÎÎÎÎC125 C ÎÎMC14051B, MC14052B, MC14053BELECTRICAL CHARACTERISTICSCharacteristicSymbol ÎÎV DD ÎÎÎÎÎÎÎTest ÎÎÎConditions ÎÎMaxTyp (3.) ÎÎÎÎÎMax UnitSUPPLY REQUIREMENTS (Voltages Referenced to V EE )ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎV DDV DD – 3.0 ≥ V SS ≥ V EEÎÎÎ ÎÎΗ VPower Supply VoltageRange18 ÎÎÎÎÎ3.0 ÎÎ18ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMinÎÎÎMinÎÎÎÎMaxÎÎÎ MinÎÎÎQuiescent Current PerPackageI DD5.01015Control Inputs:V in = V SS or V DD ,Switch I/O: V EE V I/OV DD , and ∆V switch 500 mV (4.)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTotal Supply Current(Dynamic PlusQuiescent, Per PackageI D(AV)5.01015T A = 25 C only (Thechannel component,(V in – V out )/R on , isnot included.)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(0.36 µA/kHz) f + I ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎDD ÎÎCONTROL INPUTS — INHIBIT, A, B, C (Voltages Referenced to V SS )Low–Level ÎÎÎÎInput Voltage V IL 5.0 R on = per spec,10 I off = per spec15ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎHigh–Level Input Voltage V IH 5.01015ÎÎÎÎR on = per spec,I off = per spec———5.01020Typical———0.0050.0100.0155.01020(0.07 µA/kHz) f + I DD(0.20 µA/kHz) f + I DDÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput Leakage Current15 — — —ÎÎÎÎÎÎεAÎÎÎÎÎÎÎÎÎÎInput CapacitanceI inC inV in = 0 or V DD———3.57.0111.53.04.0——————3.57.0112.254.506.752.755.508.25— — — —ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ1.53.04.0—————————3.57.0111503006001.53.04.0———±ÎÎ0.1ÎÎα0.00001 ±ÎÎÎ0.1ÎÎ1.0ÎÎÎ5.0ÎÎÎ7.5 pFµAµAVV— —ÎÎ ÎÎΗÎÎÎÎÎÎÎ 3.0ÎÎÎ3.0ÎÎÎÎ18ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSWITCHES IN/OUT AND COMMONS OUT/IN — X, Y, Z (Voltages Referenced to V EE )V I/OPeak–to–Peak VoltageInto or Out of the SwitchÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎRecommendedÎÎΗÎÎÎChannel On or Off 0 V DD 0 — V DDÎÎÎÎÎÎÎ0ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΗÎÎÎÎÎÎÎChannel On ÎÎÎ 0 ÎÎÎ0ÎÎÎΗ ÎÎÎ 600ÎÎÎ 0 ÎÎÎmVRecommended Static orDynamic Voltage Acrossthe Switch (4.) (Figure 5)∆V switch ÎÎ600 ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Offset VoltageÎÎÎÎV OO — ÎÎÎÎÎÎÎÎÎV in = 0 V, No Load — — — 10 — — ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎΗ µVÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎON ResistanceR on5.01015∆V switch 500 mV (4.)V in = V IL or V IH(Control), and V in =0 to V DD (Switch)V DDV PP300 ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ∆ON Resistance BetweenAny Two Channels in theSame Package∆R on5.01015ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOff–Channel LeakageÎÎÎÎI ÎÎÎÎ ÎÎÎoff 15 V in = V IL or VÎÎÎIH— — — nAÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎCurrent (Figure 10)(Control) Channel toChannel or Any OneChannel——————800400220705045——————± 100 ÎÎ250120802510101050500280705045——————12005203001359565± 0.05 ± 100 ±1000 ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎCapacitance, Switch I/O C ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎI/OInhibit = V DD— — 10 — —ÎÎÎÎ ÎÎΗ pFÎÎ ÎÎΗÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCapacitance, Common O/I C ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎO/I — Inhibit = V DDÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎpF—ÎÎÎÎÎÎÎÎÎÎ(MC14051B)ÎΗ ÎΗÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΗ ÎÎÎ60 ÎÎÎÎÎΗÎÎÎÎÎÎÎÎÎΗ ÎΗ(MC14052B)— — — 32 — — —(MC14053B)— — — 17 — — —Capacitance, Feedthrough(Channel Off)C I/O——Pins Not AdjacentPins AdjacentÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ3. Data labeled “Typ” is not to be used for design purposes, but is intended as an indication of the IC’s potential performance.4. For voltage drops across the switch (∆V switch ) > 600 mV ( > 300 mV at high temperature), excessive V DD current may be drawn, i.e. theÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎcurrent out of the switch may contain both V DD and switch input components. The reliability of the device will be unaffected unless theMaximum Ratings are exceeded. (See first page of this data sheet.)——————0.150.47——————ΩΩpFhttp://onsemi.com157

MC14051B, MC14052B, MC14053BELECTRICAL CHARACTERISTICS (5.) (C L = 50 pF, T A = 25 C) (V EE V SS unless otherwise indicated)CharacteristicSymbolV DD – V EEVdcTyp (6.)All Types Max UnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPropagation Delay TimesÎÎÎÎÎ(Figure ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ6)ÎÎÎÎÎ ÎÎÎÎÎtÎÎÎPLH , t PHL nsÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSwitch Input to Switch Output (R L = 10 kΩ)MC14051t PLH , t PHL = (0.17 ns/pF) C L + 26.5 nst PLH , t PHL = (0.08 ns/pF) C L + 11 nst PLH , t PHL = (0.06 ns/pF) C L + 9.0 nsÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMC14052t PLH , t PHL = (0.17 ns/pF) C L + 21.5 nst PLH , t PHL = (0.08 ns/pF) C L + 8.0 nst PLH , t PHL = (0.06 ns/pF) C L + 7.0 nsÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMC14053ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎt PLH , t PHL = (0.17 ns/pF) C L + 16.5 nst PLH , t PHL = (0.08 ns/pF) C L + 4.0 nst PLH , t PHL = (0.06 ns/pF) C L + 3.0 nsÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInhibit to Output (R L = 10 kΩ, V EE = V SS )ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput “1” orÎÎÎÎΓ0”ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎto High Impedance, ort PZH , t PZLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎHigh Impedance to “1” or “0” LevelMC14051Bt PHZ , t PLZ ,ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMC14052BÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMC14053BÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎControl Input ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎto OutputÎÎÎÎÎ(R L =ÎÎÎÎÎ10ÎÎÎÎÎkΩ,ÎÎÎÎÎVÎÎÎEE = V SS )t PLH , t PHL nsÎÎÎÎÎÎÎÎÎÎÎÎÎMC14051BÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMC14052BÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMC14053BÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSecond Harmonic DistortionÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(R L = 10KΩ, f = 1 ÎÎÎÎΗÎÎÎÎÎ10kHz) ÎÎÎÎÎ0.07ÎÎÎÎΗÎÎÎ%V in = 5 V PP ÎÎÎÎÎBandwidth ÎÎÎÎÎ(Figure ÎÎÎÎÎ7)ÎÎÎÎÎBWÎÎÎÎÎ10 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ17 — MHz(R L = 1 kΩ, V in = 1/2 (V DD –V EE ) p–p, C LÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ= 50pFÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ20 Log (V out /V in ) = – 3 dB)Off Channel Feedthrough ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎAttenuation (Figure 7)— 10 ÎÎÎÎÎÎÎÎÎΖ 50 ÎÎÎÎÎÎÎΗ dBÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎR L = 1KΩ, V in = 1/2 (V DD – V EE ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ) p–pf in = 4.5 MHz — MC14051Bf in = 30 MHz — MC14052Bf in = 55 MHz — MC14053BÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎChannel Separation (Figure 8)—ÎÎÎÎÎ ÎÎÎÎÎ10ÎÎÎÎΖ 50ÎÎÎÎΗÎÎÎdB(R L = 1 kΩ, V in = 1/2 (V DD –V EE ) p–p,f in = 3.0 MHzÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCrosstalk, Control Input to Common O/I (Figure 9)—ÎÎÎÎÎ ÎÎÎÎÎ10ÎÎÎÎÎ75ÎÎÎÎΗÎÎÎmV(R 1 = 1 kΩ, R L = 10 kΩControl t TLH = t THL = 20 ns, Inhibit = V SS )5. The formulas given are for the typical characteristics only at 25 C.6. Data labelled “Typ” is not lo be used for design purposes but In intended as an indication of the IC’s potential performance.ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5.010155.010155.010155.010155.010155.010155.010155.010155.01015351512301210258.06.03501701403001551252751401103601601203251309030012080904030753025652015700340280600310250550280220720320240650260180600240160nsnsnsnsnsnsnsÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎhttp://onsemi.com158

MC14051B, MC14052B, MC14053BIN/OUTV DDV DDV EEV DD V DDV EEOUT/INLEVELCONVERTEDCONTROLIN/OUTOUT/INCONTROLFigure 1. Switch Circuit SchematicControl InputsSelectTRUTH TABLEON SwitchesInhibit C* B A MC14051B MC14052B MC14053B0 0 0 0 X0 Y0 X0 Z0 Y0 X00 0 0 1 X1 Y1 X1 Z0 Y0 X10 0 1 0 X2 Y2 X2 Z0 Y1 X00 0 1 1 X3 Y3 X3 Z0 Y1 X10 1 0 0 X4 Z1 Y0 X00 1 0 1 X5 Z1 Y0 X10 1 1 0 X6 Z1 Y1 X00 1 1 1 X7 Z1 Y1 X11 x x x None None None*Not applicable for MC14052x = Don’t CareINH 6A11B10C 9X0 13X1 14X2 15X3 12X4 1X5 5X6 2X7 4BINARY TO 1–OF–8LEVELDECODER WITHCONVERTERINHIBIT8 V SS 7 V EE16 V DD3XFigure 2. MC14051B Functional Diagram16 V DDINH 6A10B 9LEVELCONVERTERBINARY TO 1–OF–4DECODER WITHINHIBITINH 6A11B10C 916 V DDLEVELCONVERTERBINARY TO 1–OF–2DECODER WITHINHIBITX0 12X1 14X2 15X3 11Y0 1Y1 5Y2 2Y3 48 V SS 7 V EE13 X3 YX0 12X1 13Y0 2Y1 1Z0 5Z1 38 V SS 7 V EE14 X15 Y4 ZFigure 3. MC14052B Functional DiagramFigure 4. MC14053B Functional Diagramhttp://onsemi.com159

MC14051B, MC14052B, MC14053BTEST CIRCUITSON SWITCHCONTROLSECTIONOF ICVLOADPULSEGENERATORABCINHR L C LV outSOURCEV DD V EE V EE V DDFigure 5. ∆V Across SwitchFigure 6. Propagation Delay Times,Control and Inhibit to OutputV inA, B, and C inputs used to turn ONor OFFthe switch under test.ABCV outV SSINHR L C L = 50 pFABCINHONOFFR LV outR LC L = 50 pFV DD – V EE2Figure 7. Bandwidth and Off–ChannelFeedthrough AttenuationV DD – V EE2Figure 8. Channel Separation(Adjacent Channels Used For Setup)V inOFF CHANNEL UNDER TESTV DDABCV outCONTROLSECTIONOF ICOTHERCHANNEL(S)V EEV EEINHR LC L = 50 pFV DDR1COMMONV EEV DDFigure 9. Crosstalk, Control Input toCommon O/IFigure 10. Off Channel LeakageNOTE: See also Figures 7 and 8 in the MC14016Bdata sheet.http://onsemi.com160

MC14051B, MC14052B, MC14053B10 kV DDV EE = V SSKEITHLEY 160DIGITALMULTIMETERV DD1 kΩRANGEX–YPLOTTERFigure 11. Channel Resistance (R ON ) Test Circuit350TYPICAL RESISTANCE CHARACTERISTICS350R ON , “ON” RESISTANCE (OHMS)30025020015010050T A = 125°C25°C–55°CR ON , “ON” RESISTANCE (OHMS)30025020015010050T A = 125°C25°C–55°C0– 10 – 8.0 – 6.0 – 4.0 – 2.0 0 0.2 4.0 6.0 8.0 10V in , INPUT VOLTAGE (VOLTS)Figure 12. V DD = 7.5 V, V EE = – 7.5 V0– 10 – 8.0 – 6.0 – 4.0 – 2.0 0 0.2 4.0 6.0 8.0 10V in , INPUT VOLTAGE (VOLTS)Figure 13. V DD = 5.0 V, V EE = – 5.0 VR ON , “ON” RESISTANCE (OHMS)700600500400300200100T A = 125°C25°C–55°CR ON , “ON” RESISTANCE (OHMS)35030025020015010050T A = 25°CV DD = 2.5 V5.0 V7.5 V0– 10 – 8.0 – 6.0 – 4.0 – 2.0 0 0.2 4.0 6.0 8.0 10V in , INPUT VOLTAGE (VOLTS)Figure 14. V DD = 2.5 V, V EE = – 2.5 V0– 10 – 8.0 – 6.0 – 4.0 – 2.0 0 0.2 4.0 6.0 8.0 10V in , INPUT VOLTAGE (VOLTS)Figure 15. Comparison at 25°C, V DD = –V EEhttp://onsemi.com161

MC14051B, MC14052B, MC14053BAPPLICATIONS INFORMATIONFigure A illustrates use of the on–chip level converterdetailed in Figures 2, 3, and 4. The 0–to–5 V Digital Controlsignal is used to directly control a 9 V p–p analog signal.The digital control logic levels are determined by V DDand V SS . The V DD voltage is the logic high voltage; the V SSvoltage is logic low. For the example, V DD = + 5 V = logichigh at the control inputs; V SS = GND = 0 V = logic low.The maximum analog signal level is determined by V DDand V EE . The V DD voltage determines the maximumrecommended peak above V SS . The V EE voltagedetermines the maximum swing below V SS . For theexample, V DD – V SS = 5 V maximum swing above V SS ;V SS – V EE = 5 V maximum swing below V SS . The exampleshows a ± 4.5 V signal which allows a 1/2 volt margin at eachpeak. If voltage transients above V DD and/or below V EE areanticipated on the analog channels, external diodes (Dx) arerecommended as shown in Figure B. These diodes should besmall signal types able to absorb the maximum anticipatedcurrent surges during clipping.The absolute maximum potential difference betweenV DD and V EE is 18.0 V. Most parameters are specified up to15 V which is the recommended maximum differencebetween V DD and V EE .Balanced supplies are not required. However, V SS mustbe greater than or equal to V EE . For example, V DD = + 10V, V SS = + 5 V, and V EE – 3 V is acceptable. See the Tablebelow.+ 5 V – 5 VV DD V SS V EE+ 4.5 V+5 VEXTERNALCMOSDIGITALCIRCUITRY9 V p–pANALOG SIGNAL0–TO–5 V DIGITALCONTROL SIGNALSSWITCHI/OINHIBIT,A, B, CMC14051BMC14052BMC14053BCOMMONO/I9 V p–pANALOG SIGNALGND– 4.5 VFigure A. Application ExampleV DDV DDD XD XANALOGI/OCOMMONO/ID XD XV EEV EEFigure B. External Germanium or Schottky Clipping DiodesPOSSIBLE SUPPLY CONNECTIONSÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎV DDV SSV EEControl InputsLogic High/Logic LowIn VoltsMaximum Analog Signal RangeIn VoltsÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎIn Volts In Volts In Volts+ 8 ÎÎÎÎÎ ÎÎÎÎ0 –ÎÎÎÎÎÎÎ8 +ÎÎÎÎÎÎÎÎÎ8/0 + 8 to – 8 = 16 V p–pÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ+ ÎÎÎÎÎ5 ÎÎÎÎ0 – ÎÎÎÎÎÎÎ12 + ÎÎÎÎÎÎÎÎÎ5/0 + 5 to – 12 = 17 V p–pÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ+ ÎÎÎÎÎ5 ÎÎÎÎ0 ÎÎÎÎÎÎÎ0 + ÎÎÎÎÎÎÎÎÎ5/0 + 5 to 0 = 5 V p–pÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ+ ÎÎÎÎÎ5 ÎÎÎÎ0 – ÎÎÎÎÎÎÎ5 + ÎÎÎÎÎÎÎÎÎ5/0 + 5 to – 5 = 10 V p–pÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ+ ÎÎÎÎÎ10 + ÎÎÎÎ5 – ÎÎÎÎÎÎÎ5 + 10/ + ÎÎÎÎÎÎÎÎÎ5 + 10 to – 5 = 15 V p–pÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎhttp://onsemi.com162ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MC14051B, MC14052B, MC14053BORDERING & SHIPPING INFORMATION:Device Package ShippingMC14051BCP PDIP–16 2000 Units per BoxMC14051BD SOIC–16 48 Units per RailMC14051BDR2 SOIC–16 2500 Units / Tape & ReelMC14051BDT TSSOP–16 96 Units per RailMC14051BDTEL TSSOP–16 2000 Units / Tape & ReelMC14051BDTR2 TSSOP–16 2500 Units / Tape & ReelMC14051BF SOEIAJ–16 See Note 7.MC14051BFEL SOEIAJ–16 See Note 7.MC14052BCP PDIP–16 2000 Units per BoxMC14052BD SOIC–16 48 Units per RailMC14052BDR2 SOIC–16 2500 Units / Tape & ReelMC14052BDT TSSOP–16 96 Units per RailMC14052BDTR2 TSSOP–16 2500 Units / Tape & ReelMC14052BF SOEIAJ–16 See Note 7.MC14052BFEL SOEIAJ–16 See Note 7.ORDERING & SHIPPING INFORMATION:MC14053BCP PDIP–16 2000 Units per BoxMC14053BD SOIC–16 48 Units per RailMC14053BDR2 SOIC–16 2500 Units / Tape & ReelMC14053BDT TSSOP–16 96 Units per RailMC14053BDTEL TSSOP–16 2000 Units / Tape & ReelMC14053BDTR2 TSSOP–16 2500 Units / Tape & ReelMC14053BF SOEIAJ–16 See Note 7.MC14053BFEL SOEIAJ–16 See Note 7.7. For ordering information on the EIAJ version of the SOICpackages, please contact your local ON Semiconductor representative.http://onsemi.com163

The MC14060B is a 14–stage binary ripple counter with an on–chiposcillator buffer. The oscillator configuration allows design of eitherRC or crystal oscillator circuits. Also included on the chip is a resetfunction which places all outputs into the zero state and disables theoscillator. A negative transition on Clock will advance the counter tothe next state. Schmitt trigger action on the input line permits veryslow input rise and fall times. Applications include time delay circuits,counter controls, and frequency dividing circuits.• Fully static operation• Diode Protection on All Inputs• Supply Voltage Range = 3.0 V to 18 V• Capable of Driving Two Low–power TTL Loads or One Low–powerSchottky TTL Load Over the Rated Temperature Range• Buffered Outputs Available from Stages 4 Through 10 and12 Through 14• Common Reset Line• Pin–for–Pin Replacement for CD4060BMAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 2.)Symbol Parameter Value UnitV DD DC Supply Voltage Range –0.5 to +18.0 VV in , V out Input or Output Voltage Range(DC or Transient)–0.5 to V DD + 0.5 VI in , I outP DInput or Output Current(DC or Transient) per PinPower Dissipation,per Package (Note 3.)±10 mA500 mWT A Ambient Temperature Range –55 to +125 °CT stg Storage Temperature Range –65 to +150 °CT LLead Temperature(8–Second Soldering)260 °C2. Maximum Ratings are those values beyond which damage to the devicemay occur.3. Temperature Derating:Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 CThis device contains protection circuitry to guard against damage due to highstatic voltages or electric fields. However, precautions must be taken to avoidapplications of any voltage higher than maximum rated voltages to thishigh–impedance circuit. For proper operation, V in and V out should be constrainedto the range V SS (V in or V out ) V DD .Unused inputs must always be tied to an appropriate logic voltage level (e.g.,either V SS or V DD ). Unused outputs must be left open.http://onsemi.comPDIP–16P SUFFIXCASE 648SOIC–16D SUFFIXCASE 751BTSSOP–16DT SUFFIXCASE 948FSOEIAJ–16F SUFFIXCASE 966A = Assembly LocationWL or L = Wafer LotYY or Y = YearWW or W = Work WeekORDERING INFORMATIONMARKINGDIAGRAMSDevice Package ShippingMC14060BCP PDIP–16 2000/BoxMC14060BD SOIC–16 2400/BoxMC14060BDR2 SOIC–16 2500/Tape & Reel161161161MC14060BCPAWLYYWW14060BAWLYWW16MC14060BAWLYWWMC14060BDT TSSOP–16 96/RailMC14060BDTR2 TSSOP–16 2500/Tape & ReelMC14060BF SOEIAJ–16 See Note 1.MC14060BFEL SOEIAJ–16 See Note 1.114060BALYW1. For ordering information on the EIAJ version ofthe SOIC packages, please contact your localON Semiconductor representative.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 3164 Publication Order Number:MC14060B/D

MC14060BPIN ASSIGNMENTQ12116V DDQ13215Q10Q14314Q8Q6413Q9Q5512RESETQ7611CLOCKQ4710OUT 1V SS89OUT 2TRUTH TABLEClock Reset Output StateLNo ChangeL Advance to next stateX H All Outputs are lowX = Don’t CareLOGIC DIAGRAM91011OUT 2OUT 1CLOCKCQCQQ4 Q5 Q12 Q13 Q147 51 2 3CQCQCQCQC QRC QRC QRC QRC QRC QR12RESETQ6 = PIN 4Q7 = PIN 6Q8 = PIN 14Q9 = PIN 13Q10 = PIN 15 V DD = PIN 16V SS = PIN 8http://onsemi.com165

MC14060BELECTRICAL CHARACTERISTICS (Voltages Referenced to V SS )ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎV – 55ÎÎÎÎÎÎÎÎC25ÎÎÎÎÎC125 ÎÎÎÎÎÎÎÎÎÎCÎÎÎÎDDCharacteristicMax Min Typ (4.)UnitMinÎÎÎ MaxÎÎÎMinÎÎÎÎÎÎÎÎÎÎÎÎÎOutput VoltageV in = V DD or 0“0” LevelÎÎÎ Symbol VdcV OL 5.0 —10 —15 —ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎV in = 0 or V DDLevelÎÎÎΓ1” V OH 5.010154.959.9514.95ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput Voltage(V O = 4.5 or 0.5 V)(V O = 9.0 or 1.0 V)“0” LevelV IL5.01015———0.050.050.05———000ÎÎÎMax0.05 — 0.050.05 — 0.050.05 — 0.05ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V O = 13.5 or 1.5 V)———1.53.04.04.959.9514.95———5.010152.254.506.75———1.53.04.04.959.9514.95——————1.53.04.0VVV(V O = 0.5 or 4.5 V) “1” Level(V O = 1.0 or 9.0 V)(V O = 1.5 or 13.5 V)V IH5.010153.57.011.0ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΗ——3.57.011.02.755.508.25———3.57.011.0———VÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput Voltage“0” Level(V O = 4.5 Vdc) (For Input 11(V O = 9.0 Vdc) and Output 10)(V O = 13.5 Vdc)V IL5.01015———ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ1.02.02.5———2.254.506.751.02.02.5———1.02.02.5VdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V O = 0.5 Vdc) “1” Level(V O = 1.0 Vdc)(V O = 1.5 Vdc)V IH5.010154.08.012.5ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΗ——4.08.012.52.755.508.25———4.08.012.5———VdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Drive Current(V OH = 2.5 V) (Except Source(V OH = 4.6 V) Pins 9 and 10)ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V OH = 9.5 V)(V OH = 13.5 V)I OH5.05.01015– 3.0– 0.64– 1.6– 4.2————– 2.4– 0.51– 1.3– 3.4– 4.2– 0.88– 2.25– 8.8————– 1.7– 0.36– 0.9– 2.4————mA(V OL = 0.4 V) Sink(V OL = 0.5 V)(V OL = 1.5 V)I OL5.010150.641.64.2ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎInput CurrentI in 15 — — — µAÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput Capacitance (V in = 0)— — — — 5.0 7.5 — — pFQuiescent Current(Per Package)C inI DD5.01015——————0.511.33.40.882.258.8———0.360.92.4———± 0.1 ±0.00001ÎÎα 0.1 ± 1.0 ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ5.0 — 0.005 5.0 — 150 µA10 — 0.010 10 — 30020 — 0.015 20 — 600ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTotal Supply Current (5.) (6.)(Dynamic plus Quiescent,Per Package)(C L = 50 pF on all outputs,all buffers switching)I T5.01015I T = (0.25 µA/kHz) f + I DDI T = (0.54 µA/kHz) f + I DDI T = (0.85 µA/kHz) f + I DDÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.5. The formulas given are for the typical characteristics only at 25 C.6. To calculate total supply current at loads other than 50 pF:ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎI T (C L ) = I T (50 pF) + (C L – 50) Vfkwhere: I T is in µA (per package), C L in pF, V = (V DD – V SS ) in volts, f in kHz is input frequency, and k = 0.002.mAµAÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎhttp://onsemi.com166

MC14060BSWITCHING CHARACTERISTICS (C L = 50 pF, T A = 25 C)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCharacteristicÎÎÎÎSymbolMin Typ (7.) ÎÎÎMaxÎÎÎÎUnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Rise Time (Counter Outputs)t TLHÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Fall Time (Counter Outputs)t THLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPropagation Delay TimeClock to Q4t PLHt PHLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎClock to Q14ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎClock Pulse Widtht wHÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎClock Pulse Frequencyf φÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎClock Rise and Fall Timet TLHt THLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎReset Pulse Widtht wÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPropagation Delay TimeReset to Ont PHLV DDVdc5.010155.010155.010155.010155.010155.010155.01015————————————1004030———4025205030204151751251.50.70.465302051417No LimitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ7. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.5.010155.010151206040———401510170806020010080200100807403002002.71.31.0———3.5812———350160100nsnsnsµsnsMHznsnsnsÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPULSEGENERATORV DD500 µF I D 0.01 µFCLOCKNCNCQ4OUT1 Q5OUT2 QnRV SSC LC LC LPULSEGENERATORCLOCKCLOCKNCNC20 nsV DDQ4OUT1 Q5OUT2QnRV SSC LC LC L90%50%10%20 nsCLOCK90%50%10%20 ns 20 ns50% DUTY CYCLEV DDV SSQt TLHt PLH90%50%10%t WHt THLt PHLFigure 1. Power Dissipation Test Circuitand WaveformFigure 2. Switching Time Test Circuitand Waveformshttp://onsemi.com167

MC14060BCLOCK 11f12.3 RtcCtcRESETR S10 OUT 1 9 OUT 2R tcC tcif 1 kHz ≤ f ≤ 100 kHzand 2R tc < R S < 10R tc(f in Hz, R in ohms, C in farads)The formula may vary for other frequencies. Recommendedmaximum value for the resistors in 1 MΩ.Figure 3. Oscillator Circuit Using RC ConfigurationTYPICAL RC OSCILLATOR CHARACTERISTICSFREQUENCY DEVIATION (%)8.04.00– 4.0– 8.0–12R TC = 56 kΩC = 1000 pF–16–55 –251.0 V5.0 VV DD = 15 VR S = 0, f = 10.15 kHz @ V DD = 10, T A =25°CR S = 120 kΩ, f = 7.8 kHz @ V DD = 10 V, T A =25°C0 25 50 75T A , AMBIENT TEMPERATURE (°C)Figure 4. RC Oscillator Stability100125f, OSCILLATOR FREQUENCY (kHz)1005020105210.5f AS A FUNCTIONOF C(R TC = 56 kΩ)(R S = 120 k)V DD = 10 Vf AS A FUNCTIONOF R TC(C = 1000 pF)(R S ≈ 2R TC )0.20.11.0 k 10 k 100 k 1.0 MR TC , RESISTANCE (OHMS)0.0001 0.001 0.01 0.1C, CAPACITANCE (µF)Figure 5. RC Oscillator Frequency as aFunction of R TC and CÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCLOCK500 kHz11CharacteristicCircuitC S C T C S20RESET 10 OUT 19 OUT 2Crystal CharacteristicsResonant Frequency50018MEquivalent Resistance, R S 1.0External Resistor/Capacitor ValuesR OR O47C T8232 kHzCircuitUnitÎÎÎ ÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎ326.2kHzkΩÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎ75082kΩpFÎÎÎ ÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ20 pFFigure 6. Typical Crystal Oscillator CircuitFrequencyÎÎÎStabilityFrequency Changes as aFunction of V DD (T A = 25 C)V DD Change from 5.0 V to 10 V + 6.0V DD Change from 10 V to 15 V + 2.0Frequency Change as a Functionof Temperature (V DD = 10 V)T A Change from – 55 C to + 100+25 C Complete Oscillator (8.)T A Change from + 25 C to – 160+125 C Complete Oscillator (8.)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ+ 2.0+ 2.0ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ+ 120ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΖ 560ppmppmppmppmÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ8. Complete oscillator includes crystal, capacitors, and resistors.Figure 7. Typical Data for Crystal Oscillator CircuitÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎhttp://onsemi.com168

The MC14066B consists of four independent switches capable ofcontrolling either digital or analog signals. This quad bilateral switchis useful in signal gating, chopper, modulator, demodulator andCMOS logic implementation.The MC14066B is designed to be pin–for–pin compatible with theMC14016B, but has much lower ON resistance. Input voltage swingsas large as the full supply voltage can be controlled via eachindependent control input.• Triple Diode Protection on All Control Inputs• Supply Voltage Range = 3.0 Vdc to 18 Vdc• Linearized Transfer Characteristics• Low Noise — 12 nV/√Cycle, f ≥ 1.0 kHz typical• Pin–for–Pin Replacement for CD4016, CD4016, MC14016B• For Lower R ON , Use The HC4066 High–Speed CMOS DeviceMAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 2.)Symbol Parameter Value UnitV DD DC Supply Voltage Range –0.5 to +18.0 VV in , V out Input or Output Voltage Range(DC or Transient)–0.5 to V DD + 0.5 VI inInput Current (DC or Transient)per Control Pin±10 mAI SW Switch Through Current ±25 mAP DPower Dissipation,per Package (Note 3.)500 mWT A Ambient Temperature Range –55 to +125 °CT stg Storage Temperature Range –65 to +150 °CT LLead Temperature(8–Second Soldering)260 °C2. Maximum Ratings are those values beyond which damage to the devicemay occur.3. Temperature Derating:Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 CThis device contains protection circuitry to guard against damage due to highstatic voltages or electric fields. However, precautions must be taken to avoidapplications of any voltage higher than maximum rated voltages to thishigh–impedance circuit. For proper operation, V in and V out should be constrainedto the range V SS (V in or V out ) V DD .Unused inputs must always be tied to an appropriate logic voltage level (e.g.,either V SS or V DD ). Unused outputs must be left open.http://onsemi.comA = Assembly LocationWL or L = Wafer LotYY or Y = YearWW or W = Work WeekORDERING INFORMATIONDevice Package ShippingMC14066BCP PDIP–14 2000/BoxMC14066BD SOIC–14 55/RailMC14066BDR2 SOIC–14 2500/Tape & ReelMC14066BDTMC14066BFPDIP–14P SUFFIXCASE 646SOIC–14D SUFFIXCASE 751ATSSOP–14DT SUFFIXCASE 948GSOEIAJ–14F SUFFIXCASE 965TSSOP–14SOEIAJ–14MARKINGDIAGRAMS141141141MC14066BCPAWLYYWW14066BAWLYWW14114066BALYWMC14066BAWLYWW96/RailMC14066BDTEL TSSOP–14 2000/Tape & ReelMC14066BDTR2 TSSOP–14 2500/Tape & ReelSee Note 1.MC14066BFEL SOEIAJ–14 See Note 1.1. For ordering information on the EIAJ version ofthe SOIC packages, please contact your localON Semiconductor representative.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 3169 Publication Order Number:MC14066B/D

MC14066BPIN ASSIGNMENTIN 1114V DDOUT 1213CONTROL 1OUT 2312CONTROL 4IN 2411IN 4CONTROL 2510OUT 4CONTROL 369OUT 3V SS78IN 313CONTROL 11IN 15CONTROL 24IN 26CONTROL 38IN 312CONTROL 4BLOCK DIAGRAM11IN 42OUT 13OUT 29OUT 310OUT 4V DD = PIN 14V SS = PIN 7LOGIC DIAGRAM AND TRUTH TABLE(1/4 OF DEVICE SHOWN)IN/OUTCONTROLControl Switch0=V SS OFF1=V DD ONOUT/INLogic Diagram RestrictionsV SS ≤ V in ≤ V DDV SS ≤ V out ≤ V DDCIRCUIT SCHEMATIC(1/4 OF CIRCUIT SHOWN)V DDV DDV DDV SSV DDV DD V DD V DDCMOSINPUT300 ΩV SSV SShttp://onsemi.com170

V DD ÎÎÎÎÎÎΖ55 ÎÎÎÎÎÎÎC 25 ÎÎÎÎÎC125 C ÎÎMC14066BELECTRICAL CHARACTERISTICSCharacteristicSymbol ÎÎTest Conditions ÎÎÎTyp (4.) ÎÎÎÎÎÎMin ÎÎMax UnitSUPPLY REQUIREMENTS (Voltages Referenced to V EE )ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎV DDÎÎΗ ÎÎÎ18 VPower Supply VoltageRange18 ÎÎÎÎÎ3.0 ÎÎ18ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMinÎÎÎ MaxÎÎ MinÎÎÎÎMaxÎÎÎQuiescent Current PerPackageI DD5.010Control Inputs:V in = V SS or V DD ,ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ15 Switch ÎÎÎÎÎÎI/O: ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎV SS V I/O ÎÎΗ ÎÎ1.0 ÎÎÎΗ 0.015ÎÎÎ1.0ÎÎΗÎÎÎÎÎÎ 30 ÎÎ V DD , andÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ∆V switch 500 mV (5.) ÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎ ÎÎ ÎÎÎ ÎÎÎTotal Supply Current(Dynamic Plus Quiescent,Per PackageI D(AV)5.01015T A = 25 C only Thechannel component,(V in – V out )/R on , isnot included.)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(0.36 µA/kHz) f + I ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎDD ÎÎCONTROL INPUTS (Voltages Referenced to V SS )Low–Level ÎÎÎÎInput Voltage V IL 5.0 R on = per spec,10 I off = per spec15ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎHigh–Level Input Voltage V IH 5.01015ÎÎÎÎR on = per spec,I off = per spec——0.250.5Typical——0.0050.0100.250.5(0.07 µA/kHz) f + I DD(0.20 µA/kHz) f + I DDÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput Leakage Current15 — — —ÎÎÎÎÎÎεAÎÎÎÎÎÎÎÎÎÎInput CapacitanceI inC inV in = 0 or V DD—ÎÎÎÎÎÎΗ——3.57.0111.53.04.0——————3.57.0112.254.506.752.755.508.251.53.04.0————————3.57.0117.5151.53.04.0———±ÎÎ0.1ÎÎα0.00001 ±ÎÎÎ0.1 ±ÎÎ1.0ÎÎÎ5.0ÎÎÎ7.5 pF— — —ÎÎÎÎ ÎÎ ÎÎεAµAVV— —ÎÎ ÎÎΗÎÎÎÎÎÎÎ3.0ÎÎÎ3.0ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSWITCHES IN AND OUT (Voltages Referenced to V SS )V I/OPeak Voltage Into or Outof the SwitchÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎRecommended Peak–to–ÎÎΗÎÎÎChannel On or Off 0 V DD 0 — V DDÎÎÎÎÎÎÎ0ÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΗÎÎÎÎÎÎÎChannel On ÎÎÎ 0 ÎÎÎ0ÎÎÎΗ ÎÎÎ 600ÎÎÎ 0 ÎÎÎmVRecommended Static orDynamic Voltage Acrossthe Switch (5.) (Figure 1)∆V switch ÎÎ600 ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Offset VoltageÎÎÎÎV OO — ÎÎÎÎÎÎÎÎÎV in = 0 V, No Load — — — 10 — — ÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎΗ µVÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎON ResistanceR on5.01015∆V switch 500 mV (5.) ,V in = V IL or V IH(Control), and V in =0 to V DD (Switch)V DDV p–p300 ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ∆ON Resistance BetweenAny Two Channelsin the Same Package∆R on5.01015ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOff–Channel LeakageÎÎÎÎI ÎÎÎÎ ÎÎÎoff 15 V in = V IL or VÎÎÎIH— — — nAÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎCurrent (Figure 6)(Control) Channel toChannel or Any OneChannelÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎCÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎI/OSwitch Off— 10 15 —ÎÎ —ÎÎÎÎ ÎÎÎ ÎÎΗ pFÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCapacitance, FeedthroughÎÎÎÎΗÎÎÎÎÎÎÎÎΗ — — — — — pFÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎΗÎÎΗÎÎÎÎÎÎÎCapacitance, Switch I/OC(Switch ÎÎÎÎI/OOff)———————800400220705045——————±100 ÎÎ250120802510101050500280705045——————12005203001359565± 0.05 ±100 ±1000 ÎÎÎÎÎ ÎÎÎ0.47 ÎÎÎ4. Data labeled “Typ” is not to be used for design purposes, but is intended as an indication of the IC’s potential performance.5. For voltage drops across the switch (∆V switch ) > 600 mV ( > 300 mV at high temperature), excessive V DD current may be drawn; i.e. theÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎcurrent out of the switch may contain both V DD and switch input components. The reliability of the device will be unaffected unless theMaximum Ratings are exceeded. (See first page of this data sheet.)ΩΩhttp://onsemi.com171

MC14066BELECTRICAL CHARACTERISTICS (6.) (C L = 50 pF, T A = 25 C unless otherwise noted.)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCharacteristicSymbolMin Typ (7.) Max UnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPropagation Delay TimesV SS = 0 Vdc t PLH , t PHL nsÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput to Output (R L = 10 kΩ)t PLH , t PHL = (0.17 ns/pF) C L + 15.5 nst PLH , t PHL = (0.08 ns/pF) C L + 6.0 nst PLH , t PHL = (0.06 ns/pF) C L + 4.0 nsÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎControl to OutputÎÎÎÎ(R L = 1ÎÎÎÎkΩ)ÎÎÎÎ(FigureÎÎÎÎ2)ÎÎÎÎÎÎt PHZ nsÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎOutput “1” to High ImpedanceÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput “0” to High ImpedanceÎÎÎÎ t ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPLZ 5.0 — 40 80 nsÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎHigh Impedance to Output “1”ÎÎÎÎt ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPZH 5.0 — 60 120 nsÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎHigh Impedance to Output “0”ÎÎÎÎt PZL ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎ5.0nsÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSecond Harmonic Distortion V SS = – 5 ÎÎÎÎVdc ÎÎÎΗ ÎÎÎÎ5.0 ÎÎÎΗ ÎÎÎÎ0.1 ÎÎΗ %(V in = 1.77 Vdc, RMS Centered @ 0.0 Vdc,R L = 10 kΩ, f = 1.0 kHz)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎBandwidth (Switch ON) (Figure 3)V ÎÎÎÎSS = – 5 Vdc — 5.0 — 65 — MHzÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(R L = 1 kΩ, 20 Log (V out /V in ) = – 3 dB, C L = 50 pF,V in = 5 V p–p )ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎFeedthrough Attenuation (Switch OFF) V SS = – 5 Vdc —(V in = 5 V p–p , R L = 1 kΩ, f in =ÎÎÎÎ ÎÎÎÎ5.0 —ÎÎÎÎ ÎÎÎΖ 50 —ÎÎÎÎÎÎdB1.0 MHz) (Figure 3)V DDVdc5.010155.01015101510151015—————————————20107.040353035302015602015402015807060706040301204030ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎChannel Separation (Figure ÎÎÎÎ4)V SS = – 5 Vdc — 5.0 — – 50 — dB(V ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎin = 5 V p–p , R L = 1 kΩ, f in ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ= 8.0 MHz)(Switch A ON, Switch B OFF)Crosstalk, Control Input to Signal Output (Figure 5)V SS = – 5 Vdc(R 1 = 1 kΩ, R L = 10 kΩ, Control t TLH = t THL = 20 ns)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΗ 5.0 — 300 — ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎ6. The formulas given are for the typical characteristics only at 25 C.7. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎmV p–pÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎhttp://onsemi.com172

MC14066BTEST CIRCUITSV outCONTROLSECTIONOF ICSOURCEON SWITCHVLOADV CV CV outV out20 nst PZH10%t PZL90%V inR LV xC LV90% DD50%10%V SS tPHZ90%V in = V DDt PLZ V x = V SSV in = V SS10% V x = V DDFigure 1. ∆V Across SwitchFigure 2. Turn–On Delay Time Test Circuitand WaveformsV C = V DD FOR BANDWIDTH TESTV C = V SS FOR FEEDTHROUGH TESTV DD – V SS2V DD – V SS2V inV DDR LC LV inV outR LC LV CV DDV SSV SSR L C LFigure 3. Bandwidth andFeedthrough AttenuationFigure 4. Channel SeparationOFF CHANNEL UNDER TEST1 kV inR L10 kV outC L = 50 pFCONTROLSECTIONOF ICAV DDV SSV SSV C = – 5.0 V TO + 5.0 V SWINGV DDFigure 5. Crosstalk,Control to OutputFigure 6. Off Channel Leakagehttp://onsemi.com173

MC14066B10 kV DDV SSKEITHLEY 160DIGITALMULTIMETERV DD1 kΩRANGEX–YPLOTTERFigure 7. Channel Resistance (R ON ) Test CircuitTYPICAL RESISTANCE CHARACTERISTICS350350R ON , “ON” RESISTANCE (OHMS)30025020015010050T A = 125°C25°C–55°CR ON , “ON” RESISTANCE (OHMS)30025020015010050T A = 125°C25°C–55°C0– 10 – 8.0 – 6.0 – 4.0 – 2.0 0 0.2 4.0 6.0 8.0 10V in , INPUT VOLTAGE (VOLTS)Figure 8. V DD = 7.5 V, V SS = – 7.5 V0– 10 – 8.0 – 6.0 – 4.0 – 2.0 0 0.2 4.0 6.0 8.0 10V in , INPUT VOLTAGE (VOLTS)Figure 9. V DD = 5.0 V, V SS = – 5.0 VR ON , “ON” RESISTANCE (OHMS)700600500400300200100T A = 125°C25°C–55°CR ON , “ON” RESISTANCE (OHMS)35030025020015010050T A = 25°CV DD = 2.5 V5.0 V7.5 V0– 10 – 8.0 – 6.0 – 4.0 – 2.0 0 0.2 4.0 6.0 8.0 10V in , INPUT VOLTAGE (VOLTS)Figure 10. V DD = 2.5 V, V SS = – 2.5 V0– 10 – 8.0 – 6.0 – 4.0 – 2.0 0 0.2 4.0 6.0 8.0 10V in , INPUT VOLTAGE (VOLTS)Figure 11. Comparison at 25°C, V DD = –V SShttp://onsemi.com174

MC14066BAPPLICATIONS INFORMATIONFigure A illustrates use of the Analog Switch. The 0–to–5 volt digital control signal is used to directly control a5 volt peak–to–peak analog signal.The digital control logic levels are determined by V DDand V SS . The V DD voltage is the logic high voltage, the V SSvoltage is logic low. For the example, V DD = + 5 V = logichigh at the control inputs; V SS = GND = 0 V = logic low.The maximum analog signal level is determined by V DDand V SS . The analog voltage must not swing higher thanV DD or lower than V SS .The example shows a 5 volt peak–to–peak signal whichallows no margin at either peak. If voltage transients aboveV DD and/or below V SS are anticipated on the analogchannels, external diodes (D x ) are recommended as shownin Figure B. These diodes should be small signal types ableto absorb the maximum anticipated current surges duringclipping.The absolute maximum potential difference betweenV DD and V SS is 18.0 volts. Most parameters are specified upto 15 volts which is the recommended maximum differencebetween V DD and V SS .+5 VV DDV SS+ 5.0 V+5 V5 V p–pANALOG SIGNALSWITCHINSWITCHOUT5 V p–pANALOG SIGNAL+ 2.5 VGNDEXTERNALCMOSDIGITALCIRCUITRY0–TO–5 V DIGITALCONTROL SIGNALSMC14066BFigure A. Application ExampleV DDV DDD XD XSWITCHINSWITCHOUTD XD XV SSV SSFigure B. External Germanium or Schottky Clipping Diodeshttp://onsemi.com175

The MC14067 multiplexer/demultiplexer is a digitally controlledanalog switch featuring low ON resistance and very low leakagecurrent. This device can be used in either digital or analogapplications.The MC14067 is a 16–channel multiplexer/demultiplexer with aninhibit and four binary control inputs A, B, C, and D. These controlinputs select 1–of–16 channels by turning ON the appropriate analogswitch (see MC14067 truth table.)• Low OFF Leakage Current• Matched Channel Resistance• Low Quiescent Power Consumption• Low Crosstalk Between Channels• Wide Operating Voltage Range: 3 to 18 V• Low Noise• Pin for Pin Replacement for CD4067Bhttp://onsemi.comPDIP–24P SUFFIXCASE 709SOIC–24DW SUFFIXCASE 751EMARKINGDIAGRAMS241241MC14067BCPAWLYYWW14067BAWLYYWWMAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 1.)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol ParameterValueUnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎV DD DC Supply Voltage Range– 0.5 to + 18.0 VÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎV in , V out Input or Output Voltage RangeÎÎÎÎÎÎVÎÎÎÎÎÎÎÎÎÎI in(DC or Transient)Input Current (DC or Transient),per Control Pin– 0.5 to V DD + 0.5 Îα 10 mAÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎI sw Switch Through Current± 25 P DPower Dissipation,per Package (Note 2.)ÎÎ500 mWÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎA = Assembly LocationWL or L = Wafer LotYY or Y = YearWW or W = Work WeekORDERING INFORMATIONDevice Package ShippingMC14067BCP PDIP–24 15/RailMC14067BDW SOIC–24 30/RailMC14067BDWR2 SOIC–24 1000/Tape & ReelT AAmbient Temperature Range– 55 to + ÎÎ125 CÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎT stgT LStorage Temperature RangeLead Temperature(8–Second Soldering)– 65 to + ÎÎ150 CÎÎ260 CÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ1. Maximum Ratings are those values beyond which damage to the devicemay occur.2. Temperature Derating:Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 CÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎThis device contains protection circuitry to guard against damage due to highstatic voltages or electric fields. However, precautions must be taken to avoidapplications of any voltage higher than maximum rated voltages to thishigh–impedance circuit. For proper operation, V in and V out should be constrainedto the range V SS (V in or V out ) V DD .Unused inputs must always be tied to an appropriate logic voltage level (e.g.,either V SS or V DD ). Unused outputs must be left open.© Semiconductor Components Industries, LLC, 1999March, 2000 – Rev. 3176 Publication Order Number:MC14067B/D

MC14067BMC14067 TRUTH TABLEControl InputsA B C D InhSelectedChannelX X X X 1 None0 0 0 0 0 X01 0 0 0 0 X10 1 0 0 0 X21 1 0 0 0 X30 0 1 0 0 X41 0 1 0 0 X50 1 1 0 0 X61 1 1 0 0 X70 0 0 1 0 X81 0 0 1 0 X90 1 0 1 0 X101 1 0 1 0 X110 0 1 1 0 X121 0 1 1 0 X130 1 1 1 0 X141 1 1 1 0 X15MC14067BPIN ASSIGNMENTX124V DDX7223X8X6322X9X5421X10X4520X11X3619X12X2718X13X1817X14X0916X15ABV SS101112151413INHIBITCDhttp://onsemi.com177

MC14067BMC14067B16–Channel AnalogMultiplexer/DemultiplexerCONTROLSSWITCHESIN/OUT1510111413987654322322212019181716INHIBITABCDX0X1X2X3X4X5X6X7X8X9X10X11X12X13X14X15X1COMMONOUT/INV DD = PIN 24V SS = PIN 12MC14067 FUNCTIONAL DIAGRAMCONTROLINPUTSINHIBITABCD1–OF–16 DECODERXIN/OUTX0X1X2X3X4X5X6X7X8X9X10X11X12X13X14X15XOUT/INhttp://onsemi.com178

– ÎÎÎÎÎÎÎ55°C 25 ÎÎÎÎÎC125 C ÎÎMC14067BELECTRICAL CHARACTERISTICSÎÎÎÎÎÎÎ ÎÎCharacteristicSymbolÎÎÎV ÎÎÎÎÎÎÎÎDD ÎÎÎÎÎÎÎ MinÎÎÎ MaxÎÎÎ MaxÎÎÎÎÎMinÎÎÎÎÎÎÎÎUnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎTest Conditions Min Typ (3.) MaxSUPPLY REQUIREMENTS (Voltages Referenced to V SS )Power Supply Voltage3.0 3.0 3.0 18 VRangeV DD — ÎÎÎÎÎÎÎÎÎÎ18 ÎÎÎ — ÎÎÎ 18 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎQuiescent Current Per I DD 5.0 Control Inputs: V in =ÎÎÎÎÎÎÎÎÎÎÎÎÎΗÎÎÎ5.0 — 0.005ÎÎÎ ÎÎÎ ÎÎÎ5.0 —Package10ÎÎÎÎÎÎÎÎÎÎÎÎÎ150V ÎÎÎÎεASS or V DD ,— 10 — 0.010 10 — 300ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 15 Switch I/O: ÎÎÎ ÎÎÎV SS V I/O — ÎÎÎÎÎ20ÎÎΗ 0.015 ÎÎÎ20 ÎÎÎ — 600ÎÎÎVÎÎÎ ÎÎÎDD , andÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ∆V ÎÎÎÎÎÎÎswitch 500 mV (4.) ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎTotal Supply ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCurrent I ÎÎÎD(AV) 5.0 T A = ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ25 C only (The(0.07 µA/kHz) f + IÎÎ µA(Dynamic Plus10 channel component,DDÎÎÎÎÎÎÎÎ ÎÎÎQuiescent,15 (VÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Typical (0.20 µA/kHz) f ÎÎÎ+ Iin – V out )/R on , isDDÎÎÎÎÎÎÎÎÎÎÎÎÎ(0.36 µA/kHz) f + IÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎDD ÎÎPer Packagenot included.)CONTROL INPUTS — INHIBIT, A, B, C, D (Voltages Referenced to V SS )ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎV ILÎÎÎ 5.0R ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎon = per spec,VLow–Level Input Voltage ÎÎÎ1015I off = per specÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎV ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎIH 5.0 R on = per spec,3.5 — 3.5 2.75 — 3.5 — VHigh–Level Input VoltageÎÎÎ1015I off = per specÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎInput Leakage Current15 — ± 0.1 — ±0.00001— 1.0 µAI inV in = 0 or V DDÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput CapacitanceC in — ÎÎΗ ÎΗ —— — pFÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΗ——SWITCHES IN/OUT AND COMMONS OUT/IN — X, Y (Voltages Referenced to V SS )7.0111.53.04.0—————7.0112.254.506.755.508.251.53.04.0—————7.011±ÎÎÎ0.1ÎÎÎ5.0 ÎÎÎ7.5Recommended Peak–to–VÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎI/O — Channel On or Off0 VÎÎÎÎÎÎÎÎÎDD 0 — VÎÎÎ ÎÎÎ ÎÎÎDD 0 VÎÎÎ ÎÎÎDD V p–pÎÎÎÎÎÎÎÎ ÎÎÎPeak Voltage Into orÎÎÎÎÎÎÎÎOut of the SwitchÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎRecommended Static orÎÎÎ∆V switch — Channel On0ÎÎÎ ÎÎÎ0 — 0ÎÎÎ ÎÎÎ ÎÎÎmVÎÎÎÎÎÎÎÎÎÎDynamic VoltageAcross the Switch (4.)(Figure 1)600ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Offset Voltage— V in = 0 V, No Load — — — 10 — — — µVV OO1.53.04.0——ÎÎÎ600ÎÎ300ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎON ResistanceR on 5.0 ∆V switch 500 mV (4.) ,ÎÎΗÎÎÎ800ÎÎΗÎÎ250ÎÎÎ1050ÎÎΗÎÎÎ1300ÎÎÎÎÎÎÎÎÎÎÎÎÎΩÎÎÎÎÎÎÎÎÎÎÎ1015V in = V IL or V IH(Control), and V in0 to V DD (Switch)ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ∆ON Resistance Between ∆R on 5.0— 70 — 25 70 — 135 ΩAny Two Channelsin the Same Package1015ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎI offÎÎÎ 15ÎÎÎÎÎÎÎÎΗÎÎÎ ± 100ÎÎÎ — ÎÎÎ — ÎÎÎnAOff–Channel LeakageCurrent (Figure 2)V in = V IL or V IH(Control) Channel toChannel or Any OneChannelÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ C ÎÎÎ I/O — ÎÎÎÎÎÎÎÎÎÎ — ÎÎÎ — ÎÎÎ — ÎÎÎ 10 ÎÎÎ — ÎÎÎ — ÎÎÎ — ÎÎpFÎÎÎCapacitance, Switch I/O ÎÎÎInhibit = V DD————4002205045————1208010105002805045————55032095650.05ÎÎÎ ±100ÎÎα1000ÎαCapacitance, Common O/I ÎÎÎÎÎÎÎÎÎÎÎ C O/I — ÎÎÎÎÎÎÎInhibit = V ÎÎÎ DD ÎÎÎ(MC14067B)ÎÎΗÎÎΗÎÎΗÎÎÎ100ÎÎΗÎÎΗ —ÎÎ pFÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ(MC14097B)Capacitance, ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎFeedthroughÎÎÎÎÎÎC ÎÎÎI/O — Pins ÎÎÎNot ÎÎÎ —ÎÎÎAdjacent— — ÎÎΗ — ÎÎ pF—ÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ(Channel Off)ÎÎÎÎÎÎΗÎÎÎ ÎÎÎPins AdjacentÎÎÎÎÎÎÎÎ0.47ÎÎÎ3. Data labeled “Typ” is not to be used for design purposes, but is intended as an indication of the IC’s potential performance.4. For voltage drops across the switch (∆V switch ) > 600 mV ( > 300 mV at high temperature), excessive V DD current may be drawn; i.e.the current out of the switch may contain both V DD and switch input components. The reliability of the device will be unaffected unless theMaximum Ratings are exceeded. (See first page of this data sheet.)ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΗ——60———http://onsemi.com179

ÎÎÎΗ ÎÎÎÎ10 ÎÎÎÎ0.3MC14067BELECTRICAL CHARACTERISTICS (C L = 50 pF, T A = 25 C)V DD – V SSVdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCharacteristicSymbolTyp (5.) Max UnitPropagation Delay TimesChannel Input–to–Channel Output (R L = 200 kΩ)MC14067Bt PLH ,t PHLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(Figure 3)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎControl Input–to–Channel OutputChannel Turn–On Time (R L = 10 kΩ)MC14067Bt PZH , t PZL(Figure 4)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ15 75 1905.010155.010351512240115904030600290nsnsChannel Turn–Off Time (R L = 300 kΩ)MC14067Bt PHZ ,t PLZÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(Figure 4)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5.0101525012075625300190nsAny Pair of Address Inputs to OutputMC14067Bt PLH , t PHLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ15 85 2155.010280115700290nsÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSecond Harmonic Distortion(R L = 10 kΩ, f = 1 kHz, V in = 5 V p–p )ÎÎΗ %ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎON Channel Bandwidth[R L = 1 kΩ, V in = 1/2 (V DD – V SS ) p–p (sine–wave)]20 Log10 (V out /V in ) = – 3 dB MC14067BÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOff Channel Feedthrough AttenuationÎÎÎÎΗ ÎÎÎÎ 10 ÎÎÎÎ – 40 ÎÎÎÎ — ÎÎÎ dB[R L = 1 kΩ, V in = 1/2 (V DD –V SS ) p–p (sine–wave)]f in = 20 MHz – MC14067B (Figure 5)BW(Figure 5) 10 15 —ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎChannel SeparationÎÎÎÎΗÎÎÎÎ10ÎÎÎΖ 40 — dBÎÎÎÎÎÎ[R L = 1 kΩ, V in = 1/2 (V DD –V SS ) p–p (sine–wave)]f in = 20 MHz (Figure 6)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCrosstalk, Control Inputs–to–Common O/IÎÎÎÎΗÎÎÎÎ10ÎÎÎÎ30 —ÎÎÎÎÎÎmV(R1 = 1 kΩ, R L = 10 kΩ,Control t r = t f = 20 ns, Inhibit = V SS )(Figure 7)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.MHzÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎhttp://onsemi.com180

MC14067BCONTROLSECTIONOF ICVON SWITCHLOADCONTROLSECTIONOF ICOFF CHANNEL UNDER TESTV DDAOTHERCHANNEL(S)V SSV SSV DDSOURCEV SSV DDFigure 1. ∆V Across SwitchFigure 2. Off Channel Leakage50%20 ns 20 nsV90%DDV in50% 10%V SSV outt PLHt PHLPULSEV DDGENERATORABCDINHR LV outC L = 50 pFV inV Ct PZH , t PZLV out50%V out50%V CABCDV outINH RC L = 50 pFLV inV XV DD V SS V SS V DD20 ns 20 ns90%50%10%90%10%V in = V DDV X = V SSt PHZ , t PLZV in = V SSV X = V DDFigure 3. Propagation Delay Test Circuitand Waveforms V in to V outFigure 4. Turn–On and Delay Turn–OffTest Circuit and Waveformshttp://onsemi.com181

MC14067BA, B, and C inputs used to turn ON or OFFthe switch under test.ABCDINHV DDR LINH OFFV V out outC L = 50 pFR L C L = 50 pFR LV in V inABCDONFigure 5. Bandwidth and Off–ChannelFeedthrough AttenuationFigure 6. Channel Separation(Adjacent Channels Used for Setup)AV BCD CV outINH R L C L = 50 pFR1Figure 7. Crosstalk, Control to Common O/IV AV BABCDINHV DD10 kV DDV SSV DDKEITHLEY 160DIGITALMULTIMETER1 kΩRANGEX–YPLOTTERC LV outV A50%V B50%t PHLt PLHV out50%Figure 8. Channel Resistance (R ON ) Test CircuitFigure 9. Propagation Delay, Any Pair ofAddress Inputs to Outputhttp://onsemi.com182

MC14067BTYPICAL RESISTANCE CHARACTERISTICS350350R ON , “ON” RESISTANCE (OHMS)30025020015010050T A = 125°C25°C–55°CR ON , “ON” RESISTANCE (OHMS)30025020015010050T A = 125°C25°C–55°C0– 10 – 8.0 – 6.0 – 4.0 – 2.0 0 0.2 4.0 6.0 8.0 10V in , INPUT VOLTAGE (VOLTS)Figure 10. V DD = 7.5 V, V SS = – 7.5 V0– 10 – 8.0 – 6.0 – 4.0 – 2.0 0 0.2 4.0 6.0 8.0 10V in , INPUT VOLTAGE (VOLTS)Figure 11. V DD = 5.0 V, V SS = – 5.0 VR ON , “ON” RESISTANCE (OHMS)700600500400300200100T A = 125°C25°C–55°CR ON , “ON” RESISTANCE (OHMS)35030025020015010050T A = 25°CV DD = 2.5 V5.0 V7.5 V0– 10 – 8.0 – 6.0 – 4.0 – 2.0 0 0.2 4.0 6.0 8.0 10V in , INPUT VOLTAGE (VOLTS)Figure 12. V DD = 2.5 V, V SS = – 2.5 V0– 10 – 8.0 – 6.0 – 4.0 – 2.0 0 0.2 4.0 6.0 8.0 10V in , INPUT VOLTAGE (VOLTS)Figure 13. Comparison at 25°C, V DD = –V SShttp://onsemi.com183

MC14067BAPPLICATIONS INFORMATIONFigure A illustrates use of the AnalogMultiplexer/Demultiplexer. The 0–to–5 volt Digital Controlsignal is used to directly control a 5 V p–p analog signal.The digital control logic levels are determined by V DDand V SS . The V DD voltage is the logic high voltage; the V SSvoltage is logic low. For the example. V DD = + 5 V = logichigh at the control inputs; V SS = GND = 0 V = logic low.The maximum analog signal level is determined by V DDand V SS . The analog voltage must swing neither higher thanV DD nor lower than V SS . The example shows a 5 V p–psignal which allows no margin at either peak. If voltagetransients above V DD and/or below V SS are anticipated onthe analog channels, external diodes (D x ) are recommendedas shown in Figure B. These diodes should be small signaltypes able to absorb the maximum anticipated current surgesduring clipping.The absolute maximum potential difference between V DDand V SS is 18.0 volts. Most parameters are specified up to15 V which is the recommended maximum differencebetween V DD and V SS .+5 VV DDV SS+ 5.0 V+5 V5 V p–pANALOG SIGNALSWITCHI/OCOMMONO/I5 V p–pANALOG SIGNAL+ 2.5 VEXTERNALCMOSDIGITALCIRCUITRY0–TO–5 V DIGITALCONTROL SIGNALSMC14067BGNDFigure A. Application ExampleV DDV DDD XD XSWITCHI/OCOMMONO/ID XD XV SSV SSFigure B. External Germanium or Schottky Clipping Diodeshttp://onsemi.com184

The MC14069UB hex inverter is constructed with MOS P–channeland N–channel enhancement mode devices in a single monolithicstructure. These inverters find primary use where low powerdissipation and/or high noise immunity is desired. Each of the sixinverters is a single stage to minimize propagation delays.• Supply Voltage Range = 3.0 Vdc to 18 Vdc• Capable of Driving Two Low–Power TTL Loads or One Low–PowerSchottky TTL Load Over the Rated Temperature Range• Triple Diode Protection on All Inputs• Pin–for–Pin Replacement for CD4069UB• Meets JEDEC UB SpecificationsMAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 2.)Symbol Parameter Value UnitV DD DC Supply Voltage Range –0.5 to +18.0 VV in , V out Input or Output Voltage Range(DC or Transient)–0.5 to V DD + 0.5 VI in , I outP DInput or Output Current(DC or Transient) per PinPower Dissipation,per Package (Note 3.)±10 mA500 mWT A Ambient Temperature Range –55 to +125 °CT stg Storage Temperature Range –65 to +150 °CT LLead Temperature(8–Second Soldering)260 °C2. Maximum Ratings are those values beyond which damage to the devicemay occur.3. Temperature Derating:Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 CThis device contains protection circuitry to guard against damage due to highstatic voltages or electric fields. However, precautions must be taken to avoidapplications of any voltage higher than maximum rated voltages to thishigh–impedance circuit. For proper operation, V in and V out should be constrainedto the range V SS (V in or V out ) V DD .Unused inputs must always be tied to an appropriate logic voltage level (e.g.,either V SS or V DD ). Unused outputs must be left open.http://onsemi.comPDIP–14P SUFFIXCASE 646SOIC–14D SUFFIXCASE 751ATSSOP–14DT SUFFIXCASE 948GSOEIAJ–14F SUFFIXCASE 965A = Assembly LocationWL or L = Wafer LotYY or Y = YearWW or W = Work WeekORDERING INFORMATIONMARKINGDIAGRAMSDevice Package ShippingMC14069UBCP PDIP–14 2000/BoxMC14069UBD SOIC–14 2750/BoxMC14069UBDR2 SOIC–14 2500/Tape & Reel14MC14069UBCPAWLYYWW114114114069UAWLYWW14114069UALYWMC14069UAWLYWWMC14069UBDTTSSOP–1496/RailMC14069UBDTEL TSSOP–14MC14069UBDTR2 TSSOP–142000/Tape & Reel2500/Tape & ReelMC14069UBFSOEIAJ–14See Note 1.MC14069UBFEL SOEIAJ–14 See Note 1.1. For ordering information on the EIAJ version ofthe SOIC packages, please contact your localON Semiconductor representative.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 3185 Publication Order Number:MC14069UB/D

MC14069UBPIN ASSIGNMENTIN 1114V DDOUT 1213IN 6IN 2312OUT 6OUT 2411IN 5IN 3510OUT 5OUT 369IN 4V SS78OUT 41LOGIC DIAGRAM2CIRCUIT SCHEMATIC(1/6 OF CIRCUIT SHOWN)V DD34V DD = PIN 14V SS = PIN 759116810INPUT*V SSOUTPUT1312*Double diode protection on allinputs not shown.20 ns 20 nsV DDPULSEGENERATORINPUT714OUTPUTV SSC LINPUTt PHLOUTPUT90%50%10%90%50%10%t PLHV DDV SSV OHV OLt THLt TLHFigure 1. Switching Time Test Circuit and Waveformshttp://onsemi.com186

MC14069UBELECTRICAL CHARACTERISTICS (Voltages Referenced to V SS )ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΖ 55 C 25 CSymbo V DDÎÎÎÎÎÎÎÎÎÎÎCharacteristic ÎÎÎ lVdcÎÎÎ MinÎÎÎ MaxÎÎÎÎ MinTyp (4.) MaxMaxÎÎÎ UnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Voltage“0” LevelSymbo ÎÎÎ125 C ÎÎÎMin ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎV OL 5.0 ÎÎÎÎÎΗ ÎÎÎÎ0.05ÎÎΗÎÎÎÎ0ÎÎÎÎÎÎ0.05ÎÎΗÎÎÎ0.05 VdcV in = V DD10ÎÎΗÎÎÎ0.05ÎÎÎÎÎÎΗÎÎÎ0ÎÎÎÎ0.05ÎÎΗÎÎÎ0.05ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ15—ÎÎÎÎÎÎÎÎÎÎÎV ÎÎÎin =ÎÎÎ0“1”ÎÎÎLevelÎÎÎÎV OH 5.0ÎÎÎ4.95 —ÎÎÎÎ4.95ÎÎÎ5.0 —ÎÎÎ4.95 —ÎÎÎVdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput Voltage(V O = 4.5 Vdc)(V O = 9.0 Vdc)(V O = 13.5 Vdc)“0” LevelV IL10155.010159.9514.95———ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΓ1” Level V IH Vdc(V O = 0.5 Vdc)(V O = 1.0 Vdc)(V O = 1.5 Vdc)5.010154.08.012.5ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ0.05——1.02.02.5————9.9514.95———4.08.012.5010152.254.506.752.755.508.250.05——1.02.02.5————9.9514.95———4.08.012.50.05——1.02.02.5———VdcOutput Drive Current(V OH = 2.5 Vdc) Source(V OH = 4.6 Vdc)(V OH = 9.5 Vdc)(V OH = 13.5 Vdc)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎI OHÎÎÎÎÎÎÎÎÎÎmAdcÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5.05.01015– 3.0– 0.64– 1.6– 4.2ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΗ———– 2.4– 0.51– 1.3– 3.4– 4.2– 0.88– 2.25– 8.8————– 1.7– 0.36– 0.9– 2.4————ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V OL = 0.4 Vdc) Sink(V OL = 0.5 Vdc)(V OL = 1.5 Vdc)I OL5.010150.641.64.2ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎInput CurrentI in 15 — — ±0.00001 ± 0.1 — µAdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput Capacitance(V in = 0)C in—————0.511.33.40.882.258.8±ÎÎÎÎ0.1— — 5.0———7.50.360.92.4————mAdc±ÎÎÎ1.0— pFÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎQuiescentÎÎÎCurrentÎÎÎÎÎÎÎÎÎIÎÎÎÎDD 5.0ÎÎΗÎÎÎÎ0.25 —ÎÎÎ0.0005 0.25ÎÎΗÎÎÎ7.5 µAdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ(Per Package)ÎÎÎÎÎÎÎÎÎÎÎTotal Supply Current (5.) (6.)(Dynamic plus Quiescent,Per Gate) (C L = 50 pF)I T10155.01015——ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Rise and Fall Times (5.)(C L = 50 pF)t TLH , t THL = (1.35 ns/pF) C L + 33 ns0.51.0——0.00100.0015ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎt THLt TLH , t THL = (0.60 ns/pF) C L + 20 nst TLH , t THL = (0.40 ns/pF) C L + 20 nst TLH ,5.01015———0.51.0I T = (0.3 µA/kHz) f + I DD /6I T = (0.6 µA/kHz) f + I DD /6I T = (0.9 µA/kHz) f + I DD /6ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎPropagation Delay Times (5.)(C L = 50 pF)t PLH , t PHL = (0.90 ns/pF) C L + 20 nst PLH , t PHL = (0.36 ns/pF) C L + 22 nst PLH , t PHL = (0.26 ns/pF) C L + 17 nst PLH ,ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎt ÎÎÎ PHL5.01015———ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.5. The formulas given are for the typical characteristics only at 25 C.6. To calculate total supply current at loads other than 50 pF:ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎI T (C L ) = I T (50 pF) + (C L – 50) Vfkwhere: I T is in µA (per package), C L in pF, V = (V DD – V SS ) in volts, f in kHz is input frequency, and k = 0.002.————————————1005040654030200100801257555————————1530——————µAdcnsnsÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎhttp://onsemi.com187

Quad Exclusive “OR” and “NOR” GatesThe MC14070B quad exclusive OR gate and the MC14077B quadexclusive NOR gate are constructed with MOS P–channel andN–channel enhancement mode devices in a single monolithicstructure. These complementary MOS logic gates find primary usewhere low power dissipation and/or high noise immunity is desired.• Supply Voltage Range = 3.0 Vdc to 18 Vdc• All Outputs Buffered• Capable of Driving Two Low–Power TTL Loads or One Low–PowerSchottky TTL Load Over the Rated Temperature Range• Double Diode Protection on All Inputs• MC14070B — Replacement for CD4030B and CD4070B Types• MC14077B — Replacement for CD4077B Typehttp://onsemi.comPDIP–14P SUFFIXCASE 646SOIC–14D SUFFIXCASE 751AMARKINGDIAGRAMS141141MC140XXBCPAWLYYWW140XXBAWLYWWMAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 2.)Symbol Parameter Value UnitV DD DC Supply Voltage Range –0.5 to +18.0 VV in , V out Input or Output Voltage Range(DC or Transient)–0.5 to V DD + 0.5 VSOEIAJ–14F SUFFIXCASE 965141MC140XXBAWLYWWI in , I outP DInput or Output Current(DC or Transient) per PinPower Dissipation,per Package (Note 3.)±10 mA500 mWT A Ambient Temperature Range –55 to +125 °CT stg Storage Temperature Range –65 to +150 °CT LLead Temperature(8–Second Soldering)260 °C2. Maximum Ratings are those values beyond which damage to the devicemay occur.3. Temperature Derating:Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 CThis device contains protection circuitry to guard against damage due to highstatic voltages or electric fields. However, precautions must be taken to avoidapplications of any voltage higher than maximum rated voltages to thishigh–impedance circuit. For proper operation, V in and V out should be constrainedto the range V SS (V in or V out ) V DD .Unused inputs must always be tied to an appropriate logic voltage level (e.g.,either V SS or V DD ). Unused outputs must be left open.XX = Specific Device CodeA = Assembly LocationWL or L = Wafer LotYY or Y = YearWW or W = Work WeekORDERING INFORMATIONDevice Package ShippingMC140XXBCP PDIP–14 2000/BoxMC140XXBD SOIC–14 2750/BoxMC140XXBDR2 SOIC–14 2500/Tape & ReelMC140XXBF SOEIAJ–14 See Note 1.MC140XXBFEL SOEIAJ–14 See Note 1.1. For ordering information on the EIAJ version ofthe SOIC packages, please contact your localON Semiconductor representative.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 3188 Publication Order Number:MC14070B/D

MC14070B, MC14077BPIN ASSIGNMENTIN 1 A114V DDIN 2 A213IN 2 DOUT A312IN 1 DOUT B411OUT DIN 1 B510OUT CIN 2 B69IN 2 CV SS78IN 1 CMC14070BQUAD Exclusive ORGate1256891213341011MC14077BQUAD Exclusive NORGate1256891213V DD = PIN 14V SS = PIN 7(BOTH DEVICES)341011V in20 ns 20 nsV DD90%50%I V 10%DDin1/f*50% DUTY CYCLEC L*Inverted output on MC14077B only.Figure 1. Power Dissipation Test Circuit and WaveformV DDV SSV DDC L20 ns20 nsV90%DDPULSE*INPUT 50%GENERATOR10%#V SSt PHLt PLHVV OHSS 90%OUTPUT 50%10% V OLt THLt TLH*Inverted output on MC14077B only.#Connect unused input to V DD for MC14070B, to V SS for MC14077B.Figure 2. Switching Time Test Circuit and Waveformshttp://onsemi.com189

MC14070B, MC14077BELECTRICAL CHARACTERISTICS (Voltages Referenced to V SS )ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΖ 55 C 25 C 125 C V DDÎÎÎÎÎÎÎÎÎÎÎCharacteristic ÎÎÎÎVdcÎÎÎÎ MinMax ÎÎÎÎÎÎMin ÎÎÎÎÎÎÎÎTyp (4.)ÎÎÎÎÎMinÎÎÎ MaxÎÎÎ UnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput VoltageV in = V DD or 0“0” Level“1” LevelÎÎSymbolV OL 5.01015———ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎV in = 0 or V DDInput Voltage(V O = 4.5 or 0.5 Vdc)(V O = 9.0 or 1.0 Vdc)(V O = 13.5 or 1.5 Vdc)“0” LevelV OHV IL5.010154.959.9514.950.050.050.05———000ÎÎÎMax0.05 —0.05 —0.05 —ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5.01015——————4.959.9514.955.01015———4.959.9514.95ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V O = 0.5 or 4.5 Vdc)(V O = 1.0 or 9.0 Vdc)(V O = 1.5 or 13.5 Vdc)“1” LevelV IH5.010153.57.011ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ1.53.04.0——————3.57.0112.254.506.752.755.508.251.53.04.0——————3.57.0110.050.050.05———1.53.04.0———VdcVdcVdcVdcOutput Drive Current(V OH = 2.5 Vdc) Source(V OH = 4.6 Vdc)(V OH = 9.5 Vdc)(V OH = 13.5 Vdc)I OH5.05.01015– 3.0– 0.64– 1.6– 4.2ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΗ———– 2.4– 0.51– 1.3– 3.4– 4.2– 0.88– 2.25– 8.8————– 1.7– 0.36– 0.9– 2.4————mAdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V OL = 0.4 Vdc) Sink(V OL = 0.5 Vdc)(V OL = 1.5 Vdc)I OL5.010150.641.64.2ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput CurrentI in 15 — ± 0.1 — ±0.00001 ± 0.1 — µAdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput Capacitance(V in = 0)C in——————0.511.33.4—0.882.258.85.0———7.50.360.92.4————mAdc±ÎÎÎ1.0— pFÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎQuiescent Current(Per Package)I DD5.01015———ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTotal Supply Current (5.) (6.)(Dynamic plus Quiescent,Per Package)(C L = 50 pF on all outputs, allbuffers switching)I T5.01015ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ0.250.51.0———0.00050.00100.0015ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Rise and Fall Times (5.)(C L = 50 pF)t TLH , t THL = (1.35 ns/pF) C L + 33 nst TLH , t THL = (0.60 ns/pF) C L + 20 nsÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎt TLH , t THL = (0.40 ns/pF) C L + 20 nsPropagation Delay Times (5.)(C L = 50 pF)t PLH , t PHL = (0.90 ns/pF) C L + 130 nst TLH ,t THL5.01015———0.250.51.0I T = (0.3 µA/kHz) f + I DDI T = (0.6 µA/kHz) f + I DDI T = (0.9 µA/kHz) f + I DDÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎt PLH , t PHL = (0.36 ns/pF) C L + 57 nst PLH , t PHL = (0.26 ns/pF) C L + 37 nst PLH ,t PHL5.01015———ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.5. The formulas given are for the typical characteristics only at 25 C.6. To calculate total supply current at loads other than 50 pF:ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎI T (C L ) = I T (50 pF) + (C L – 50) Vfkwhere: I T is in µH (per package), C L in pF, V = (V DD – V SS ) in volts, f in kHz is input frequency, and k = 0.002.————————————1005040175755520010080350150110—————————7.51530——————µAdcµAdcnsnsÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎhttp://onsemi.com190

The MC14076B 4–Bit Register consists of four D–type flip–flopsoperating synchronously from a common clock. OR gatedoutput–disable inputs force the outputs into a high–impedance statefor use in bus organized systems. OR gated data–disable inputs causethe Q outputs to be fed back to the D inputs of the flip–flops. Thus theyare inhibited from changing state while the clocking process remainsundisturbed. An asynchronous master root is provided to clear all fourflip–flops simultaneously independent of the clock or disable inputs.• Three–State Outputs with Gated Control Lines• Fully Independent Clock Allows Unrestricted Operation for the TwoModes: Parallel Load and Do Nothing• Asynchronous Master Reset• Four Bus Buffer Registers• Supply Voltage Range = 3.0 Vdc to 18 Vdc• Capable of Driving Two Low–Power TTL Loads or One Low–PowerSchottky TTL Load Over the Rated Temperature RangeMAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 1.)Symbol Parameter Value UnitV DD DC Supply Voltage Range –0.5 to +18.0 VV in , V out Input or Output Voltage Range(DC or Transient)–0.5 to V DD + 0.5 VI in , I outP DInput or Output Current(DC or Transient) per PinPower Dissipation,per Package (Note 2.)±10 mA500 mWhttp://onsemi.comPDIP–16P SUFFIXCASE 648SOIC–16D SUFFIXCASE 751BA = Assembly LocationWL or L = Wafer LotYY or Y = YearWW or W = Work WeekORDERING INFORMATIONMARKINGDIAGRAMSDevice Package ShippingMC14076BCP PDIP–16 2000/BoxMC14076BD SOIC–16 2400/BoxMC14076BDR2 SOIC–16 2500/Tape & Reel161161MC14076BCPAWLYYWW14076BAWLYWWT A Ambient Temperature Range –55 to +125 °CT stg Storage Temperature Range –65 to +150 °CT LLead Temperature(8–Second Soldering)260 °C1. Maximum Ratings are those values beyond which damage to the devicemay occur.2. Temperature Derating:Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 CThis device contains protection circuitry to guard against damage due to highstatic voltages or electric fields. However, precautions must be taken to avoidapplications of any voltage higher than maximum rated voltages to thishigh–impedance circuit. For proper operation, V in and V out should be constrainedto the range V SS (V in or V out ) V DD .Unused inputs must always be tied to an appropriate logic voltage level (e.g.,either V SS or V DD ). Unused outputs must be left open.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 3191 Publication Order Number:MC14076B/D

MC14076BPIN ASSIGNMENTOUTPUTDISABLE{AB121615V DDRQ0314D0Q1413D1Q2512D2Q3611D3V SSC78109BA}DATADISABLEBLOCK DIAGRAM1514131211109721RESETD0D1D2D3BADATADISABLECLOCKB OUTPUTA DISABLEQ0Q1Q2Q33456V DD = PIN 16V SS = PIN 8FUNCTION TABLEInputsData DisableReset Clock A BDataDOutputQ1 X X X X 00 0 X X X Q n0 1 X X Q n0 X 1 X Q n0 0 0 0 00 0 0 1 1When either output disable A or B (or both) is (are) high theoutput is disabled to the high–impedance state; howeversequential operation of the flip–flops is not affected.X = Don’t Care.http://onsemi.com192

MC14076BELECTRICAL CHARACTERISTICS (Voltages Referenced to V SS )ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΖ 55 C 25 C 125 C V DDÎÎÎÎÎÎÎÎÎÎCharacteristic ÎÎÎÎÎÎÎMinÎÎÎMaxÎÎÎÎ MinÎÎÎÎÎTyp (3.) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎMaxMaxÎÎÎUnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput VoltageV in = V DD or 0“0” Level“1” LevelÎÎÎ ÎÎÎSymbol VdcV OL 5.0 —10 —15 —ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎV in = 0 or V DDInput Voltage(V O = 4.5 or 0.5 Vdc)(V O = 9.0 or 1.0 Vdc)(V O = 13.5 or 1.5 Vdc)“0” LevelV OHV IL5.010154.959.9514.950.050.050.05———0000.050.050.05ÎÎÎMin— 0.05 Vdc— 0.05— 0.05ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5.01015——————4.959.9514.955.01015———4.959.9514.95ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V O = 0.5 or 4.5 Vdc)(V O = 1.0 or 9.0 Vdc)(V O = 1.5 or 13.5 Vdc)“1” LevelV IH5.010153.57.011ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ1.53.04.0——————3.57.0112.254.506.752.755.508.251.53.04.0——————3.57.011———1.53.04.0———VdcVdcVdcOutput Drive Current(V OH = 2.5 Vdc) Source(V OH = 4.6 Vdc)(V OH = 9.5 Vdc)(V OH = 13.5 Vdc)I OH5.05.01015– 3.0– 0.64– 1.6– 4.2ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΗ———– 2.4– 0.51– 1.3– 3.4– 4.2– 0.88– 2.25– 8.8————– 1.7– 0.36– 0.9– 2.4————mAdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V OL = 0.4 Vdc) Sink(V OL = 0.5 Vdc)(V OL = 1.5 Vdc)I OL5.010150.641.64.2ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎInput CurrentI in 15 — ÎÎÎÎÎÎÎΗ±0.00001± 0.1 — ÎÎεAdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput Capacitance(V in = 0)C in—————0.511.33.40.882.258.8±ÎÎÎÎ0.1— — 5.0———7.50.360.92.4————mAdc±ÎÎÎ1.0— pFÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎQuiescent Current(Per Package)I DD5.01015———ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTotal Supply Current (4.) (5.)(Dynamic plus Quiescent,Per Package)(C L = 50 pF on all outputs, allbuffers switching)I T5.01015ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5.01020———0.0050.0100.015ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5.01020I T = (0.75 µA/kHz) f + I DDI T = (1.50 µA/kHz) f + I DDI T = (2.25 µA/kHz) f + I DD———150300600µAdcµAdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎThree–State Leakage Current ÎÎÎI ÎÎÎÎTL 15 — — — ± µAdc3.0ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎα 0.1 ± 0.0001ÎÎÎÎ ± 0.1 ÎÎÎÎÎÎÎ3. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.4. The formulas given are for the typical characteristics only at 25 C.5. To calculate total supply current at loads other than 50 pF:I T (C L ) = I T (50 pF) + (C L – 50) Vfkwhere: I T is in µA (per package), C L in pF, V = (V DD – V SS ) in volts, f in kHz is input frequency, and k = 0.002.ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎhttp://onsemi.com193

MC14076BSWITCHING CHARACTERISTICS (6.) (C L = 50 pF, T A = 25 C)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCharacteristicÎÎÎÎSymbolMin Typ (7.) ÎÎÎMaxÎÎÎÎUnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Rise and Fall Timet TLH , t THL = (1.5 ns/pF) C L + 25 nst TLH , t THL = (0.75 ns/pF) C L + 12.5 nst TLH , t THL = (0.55 ns/pF) C L + 9.5 nst TLH , t THLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPropagation Delay TimeClock to QÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎt PLH , t PHL = (1.7 ns/pF) C L + 215 nst PLH , t PHL = (0.66 ns/pF) C L + 92 nst PLH , t PHL = (0.5 ns/pF) C L + 65 nst PLH , t PHLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎReset to Qt PLH , t PHL = (1.7 ns/pF) C L + 215 nst PLH , t PHL = (0.66 ns/pF) C L + 92 nst PLH , t PHL = (0.5 ns/pF) C L + 65 nsÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ3–State Propagation Delay, Output “1” or “0”to High Impedancet PHZ , t PLZÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ3–State Propagation Delay, High Impedanceto “1” or “0” Levelt PZH , t PZLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎClock Pulse Widtht WHÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎReset Pulse Widtht WHÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎData Setup Timet suÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎData Hold Timet hÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎData Disable Setup Timet suÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎClock Pulse Rise and Fall TimeÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎClock Pulse Frequencyt TLH , t THLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ6. The formulas given are for the typical characteristics only at 25 C.7. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.f clV DDVdc5.010155.010155.010155.010155.010155.010155.010155.010155.010155.010155.010155.01015———————————————260110803701501103010413060502208050——————10050403001259030012590150604520080601305540185755515526530251104025———3.69.0122001008060025018060025018030012090400160120———————————————15541.84.56.0nsnsnsnsnsnsnsnsnsµsMHzÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎhttp://onsemi.com194

MC14076BDQINPUTINFORMATIONOUTPUTINPUT RISE AND FALL 20 ns90%50%10%t h t ht sut su20 ns50%t WHt WL90%10%t PLHf clt PHL10%90%50%t TLHt THLRESET = 0DATA DISABLE A AND B = 0OUTPUT DISABLE A AND B = 0V DDV SSV DDV SSV OHV OLOUTPUTDISABLEA OR BANY QOUTPUTANY QOUTPUTOTHERINPUTSOUTPUTDISABLEA OR B50%20nsOUTPUTSCONNECTEDt PLZ10%t PHZ90%MC14076B90%50%10%ANY QOUTPUTR L = 1 kΩC L20ns90%10%OUTPUTSDISCONNECTEDt PZLt PZHV DDV SSV OH≈ 2.5 V @ V DD = 5 V,10 V, AND 15 V≈ 2 V @ V DD = 5 V≈ 6 V @ V DD = 10 V≈ 10 V @ V DD = 15 VV OLOUTPUTSCONNECTEDV DD FOR t PLZ AND t PZLV SS FOR t PHZ AND t PZHFigure 1. Timing DiagramFigure 2. Three–State Propagation DelayWaveshape and CircuitEQUIVALENTFUNCTIONAL BLOCK DIAGRAMOUTPUT DISABLE AOUTPUT DISABLE B12D014DQDATA DISABLE ADATA DISABLE B910CR Q3 Q0D1 13DQCLOCK 7CR Q4 Q1D2 12DQCR Q5 Q2D3 11DQCR Q6 Q3RESET 15http://onsemi.com195

The MC14093B Schmitt trigger is constructed with MOSP–channel and N–channel enhancement mode devices in a singlemonolithic structure. These devices find primary use where low powerdissipation and/or high noise immunity is desired. The MC14093Bmay be used in place of the MC14011B quad 2–input NAND gate forenhanced noise immunity or to “square up” slowly changingwaveforms.• Supply Voltage Range = 3.0 Vdc to 18 Vdc• Capable of Driving Two Low–Power TTL Loads or One Low–PowerSchottky TTL Load Over the Rated Temperature Range• Triple Diode Protection on All Inputs• Pin–for–Pin Compatible with CD4093• Can be Used to Replace MC14011B• Independent Schmitt–Trigger at each InputMAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 2.)Symbol Parameter Value UnitV DD DC Supply Voltage Range –0.5 to +18.0 VV in , V out Input or Output Voltage Range(DC or Transient)–0.5 to V DD + 0.5 VI in , I outP DInput or Output Current(DC or Transient) per PinPower Dissipation,per Package (Note 3.)±10 mA500 mWT A Ambient Temperature Range –55 to +125 °CT stg Storage Temperature Range –65 to +150 °CT LLead Temperature(8–Second Soldering)260 °C2. Maximum Ratings are those values beyond which damage to the devicemay occur.3. Temperature Derating:Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 CThis device contains protection circuitry to guard against damage due to highstatic voltages or electric fields. However, precautions must be taken to avoidapplications of any voltage higher than maximum rated voltages to thishigh–impedance circuit. For proper operation, V in and V out should be constrainedto the range V SS (V in or V out ) V DD .Unused inputs must always be tied to an appropriate logic voltage level (e.g.,either V SS or V DD ). Unused outputs must be left open.http://onsemi.comA = Assembly LocationWL or L = Wafer LotYY or Y = YearWW or W = Work WeekORDERING INFORMATIONDevice Package ShippingMC14093BCP PDIP–14 2000/BoxMC14093BD SOIC–14 2750/BoxMC14093BDR2 SOIC–14 2500/Tape & ReelMC14093BDTPDIP–14P SUFFIXCASE 646SOIC–14D SUFFIXCASE 751ATSSOP–14DT SUFFIXCASE 948GSOEIAJ–14F SUFFIXCASE 965TSSOP–14MARKINGDIAGRAMS141141141MC14093BCPAWLYYWW14093BAWLYWW14114093BALYWMC14093BAWLYWW96/RailMC14093BDTEL TSSOP–14 2000/Tape & ReelMC14093BDTR2 TSSOP–14 2500/Tape & ReelMC14093BFSOEIAJ–14See Note 1.MC14093BFEL SOEIAJ–14 See Note 1.1. For ordering information on the EIAJ version ofthe SOIC packages, please contact your localON Semiconductor representative.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 3196 Publication Order Number:MC14093B/D

MC14093BPIN ASSIGNMENTIN 1 A114V DDIN 2 A213IN 2 DOUT A312IN 1 DOUT B411OUT D510OUT CIN 2 B69IN 2 CIN 1 BLOGIC DIAGRAMV SS78IN 1C1256891213341011V DD = PIN 14V SS = PIN 7EQUIVALENT CIRCUIT SCHEMATIC(1/4 OF CIRCUIT SHOWN)http://onsemi.com197

MC14093BELECTRICAL CHARACTERISTICS (Voltages Referenced to V SS )ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΖ 55 C 25 C 125 C V DDÎÎÎÎÎÎÎÎÎÎCharacteristic ÎÎÎÎÎÎÎMinÎÎÎMaxÎÎÎÎ MinÎÎÎÎÎTyp (4.) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎMaxMaxÎÎÎUnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput VoltageV in = V DD or 0“0” Level“1” LevelÎÎÎ ÎÎÎSymbol VdcV OL 5.0 —10 —15 —ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎV in = 0 or V DDOutput Drive Current(V OH = 2.5 Vdc) Source(V OH = 4.6 Vdc)(V OH = 9.5 Vdc)(V OH = 13.5 Vdc)V OHI OH5.010154.959.9514.950.050.050.05———0000.050.050.05ÎÎÎMin— 0.05 Vdc— 0.05— 0.05ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5.05.01015– 3.0– 0.64– 1.6– 4.2———4.959.9514.955.01015———4.959.9514.95ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V OL = 0.4 Vdc) Sink(V OL = 0.5 Vdc)(V OL = 1.5 Vdc)I OL5.010150.641.64.2ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΗ———– 2.4– 0.51– 1.3– 3.4– 4.2– 0.88– 2.25– 8.8————– 1.7– 0.36– 0.9– 2.4ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput Current15 — — ±0.00001 ± 0.1 — µAdcI inÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎInput Capacitance— — — — 5.0 7.5 — — pF(V in = 0)C in———0.511.33.4± 0.1ÎÎÎÎ0.882.258.8———0.360.92.4——————————VdcmAdcmAdc± 1.0ÎÎÎQuiescent Current(Per Package)I DD5.01015———ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTotal Supply Current (5.) (6.)(Dynamic plus Quiescent,Per Package)(C L = 50 pF on all outputs, allbuffers switching)I T5.01015ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ0.250.51.0———0.00050.00100.0015ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎHysteresis VoltageV H †5.010150.31.21.6ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎThreshold VoltagePositive–GoingV T+5.010152.24.66.80.250.51.0I T = (1.2 µA/kHz) f + I DDI T = (2.4 µA/kHz) f + I DDI T = (3.6 µA/kHz) f + I DDÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎNegative–GoingV T–5.010150.92.54.0ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.5. The formulas given are for the typical characteristics only at 25 C.6. To calculate total supply current at loads other than 50 pF:ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎI T (C L ) = I T (50 pF) + (C L – 50) Vfkwhere: I T is in µA (per package), C L in pF, V = (V DD – V SS ) in volts, f in kHz is input frequency, and k = 0.004.ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ2.03.45.03.67.110.82.85.27.40.31.21.62.24.66.80.92.54.01.11.72.12.95.98.81.93.95.82.03.45.03.67.110.82.85.27.4———0.31.21.62.24.66.80.92.54.07.515302.03.45.03.67.110.82.85.27.4µAdcµAdcVdcVdcVdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎhttp://onsemi.com198

MC14093BSWITCHING CHARACTERISTICS (C L = 50 pF, T A = 25 C)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCharacteristicÎÎÎÎSymbolMin Typ (7.) ÎÎÎMaxÎÎÎÎUnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Rise Timet TLHÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Fall Timet THLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPropagation Delay Timet PLH , t PHLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ7. Data labeled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.V DDVdc5.010155.010155.01015—————————100504010050401255040200100802001008025010080nsnsnsÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎV DD20 ns 20 nsPULSEGENERATORINPUT714VSSC LOUTPUTINPUTt PHLOUTPUT90%50%10%90%50%10%t PLHV DDV SSV OHV OLt THLt TLHFigure 1. Switching Time Test Circuit and WaveformsV inV H V DDV inV HV DDV SSV SSV DDV DDV outV outV SSV SS(a) Schmitt Triggers will square up(a) inputs with slow rise and fall times.(b) A Schmitt trigger offers maximum(b) noise immunity in gate applications.Figure 2. Typical Schmitt Trigger Applicationshttp://onsemi.com199

MC14093B14I OHV outV GS14I OLV outAll unused inputsconnected to ground.V GS7All unused inputsconnected to ground.7IOH, DRAIN CURRENT (mAdc)0– 2.0– 4.0– 6.0– 8.0aT A = – 55°CbT A = + 25°CbT A = + 125°CV GS = – 5.0 Vdc– 10 Vdcca a–10– 10 – 8.0 – 6.0 – 4.0 – 2.0 0V DS , DRAIN VOLTAGE (Vdc)Figure 3. Typical Output SourceCharacteristics Test Circuitcbab c b– 15 VdcI OL , DRAIN CURRENT (mAdc)108.06.04.0a b cbac15 VdcV GS = 10 Vdca2.0b 5.0 Vdcc00 2.0 4.0 6.0 8.0 10V DS , DRAIN VOLTAGE (Vdc)Figure 4. Typical Output SinkCharacteristics Test CircuitaT A = – 55°CbT A = + 25°CcT A = + 125°CV DD00Vout , OUTPUT VOLTAGE (Vdc)V T– V T+V HV in , INPUT VOLTAGE (Vdc)VDDFigure 5. Typical Transfer Characteristicshttp://onsemi.com200

The MC14094B combines an 8–stage shift register with a data latchfor each stage and a three–state output from each latch.Data is shifted on the positive clock transition and is shifted from theseventh stage to two serial outputs. The Q S output data is for use inhigh–speed cascaded systems. The Q′ S output data is shifted on thefollowing negative clock transition for use in low–speed cascadedsystems.Data from each stage of the shift register is latched on the negativetransition of the strobe input. Data propagates through the latch whilestrobe is high.Outputs of the eight data latches are controlled by three–statebuffers which are placed in the high–impedance state by a logic Lowon Output Enable.• Three–State Outputs• Capable of Driving Two Low–Power TTL Loads or One Low–PowerSchottky TTL Load Over the Rated Temperature Range• Input Diode Protection• Data Latch• Dual Outputs for Data Out on Both Positive andNegative Clock Transitions• Useful for Serial–to–Parallel Data Conversion• Pin–for–Pin Compatible with CD4094BMAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 1.)Symbol Parameter Value UnitV DD DC Supply Voltage Range –0.5 to +18.0 VV in , V out Input or Output Voltage Range(DC or Transient)–0.5 to V DD + 0.5 VI in , I outInput or Output Current(DC or Transient) per Pin±10 mAhttp://onsemi.comPDIP–16P SUFFIXCASE 648SOIC–16D SUFFIXCASE 751BTSSOP–16DT SUFFIXCASE 948FSOEIAJ–16F SUFFIXCASE 966MARKINGDIAGRAMS16116116MC14094BCPAWLYYWW14094BAWLYWW16A = Assembly LocationWL or L = Wafer LotYY or Y = YearWW or W = Work Week1114094BALYWMC14094BAWLYWWP DPower Dissipation,per Package (Note 2.)500 mWORDERING INFORMATIONT A Ambient Temperature Range –55 to +125 °CT stg Storage Temperature Range –65 to +150 °CT LLead Temperature(8–Second Soldering)260 °C2. Maximum Ratings are those values beyond which damage to the devicemay occur.3. Temperature Derating:Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 CThis device contains protection circuitry to guard against damage due to highstatic voltages or electric fields. However, precautions must be taken to avoidapplications of any voltage higher than maximum rated voltages to thishigh–impedance circuit. For proper operation, V in and V out should be constrainedto the range V SS (V in or V out ) V DD .Unused inputs must always be tied to an appropriate logic voltage level (e.g.,either V SS or V DD ). Unused outputs must be left open.Device Package ShippingMC14094BCP PDIP–16 2000/BoxMC14094BDSOIC–1648/RailMC14094BDR2 SOIC–16 2500/Tape & ReelMC14094BDT TSSOP–16 96/RailMC14094BDTR2 TSSOP–16 2500/Tape & ReelMC14094BF SOEIAJ–16 See Note 1.1. For ordering information on the EIAJ version of theSOIC packages, please contact your local ONSemiconductor representative.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 3201 Publication Order Number:MC14094B/D

MC14094BPIN ASSIGNMENTSTROBEDATACLOCK123161514V DDOUTPUTENABLEQ5Q1413Q6Q2512Q7Q3611Q8Q4710Q′ SV SS89Q SOutputParallel Outputs Serial OutputsClock Enable Strobe Data Q1 Q N Q S * Q′ S0 X X Z Z Q7 No Chg.0 X X Z Z No Chg. Q71 0 X No Chg. No Chg. Q7 No Chg.1 1 0 0 Q N –1 Q7 No Chg.1 1 1 1 Q N –1 Q7 No Chg.1 1 1 No Chg. No Chg. No Chg. Q7Z = High Impedance X = Don’t Care* At the positive clock edge, information in the 7th shift register stage is transferred to Q8 and Q S .http://onsemi.com202

MC14094BELECTRICAL CHARACTERISTICS (Voltages Referenced to V SS )ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΖ 55 C 25 C 125 C V DDÎÎÎÎÎÎÎÎÎÎCharacteristic ÎÎÎÎÎÎÎMinÎÎÎMaxÎÎÎÎ MinÎÎÎÎÎTyp (4.) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎMaxMaxÎÎÎUnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput VoltageV in = V DD or 0“0” Level“1” LevelÎÎÎ ÎÎÎSymbol VdcV OL 5.0 —10 —15 —ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎV in = 0 or V DDInput Voltage(V O = 4.5 or 0.5 Vdc)(V O = 9.0 or 1.0 Vdc)(V O = 13.5 or 1.5 Vdc)“0” LevelV OHV IL5.010154.959.9514.950.050.050.05———0000.050.050.05ÎÎÎMin— 0.05 Vdc— 0.05— 0.05ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5.01015——————4.959.9514.955.01015———4.959.9514.95ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V O = 0.5 or 4.5 Vdc)(V O = 1.0 or 9.0 Vdc)(V O = 1.5 or 13.5 Vdc)“1” LevelV IH5.010153.57.011ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ1.53.04.0——————3.57.0112.254.506.752.755.508.251.53.04.0——————3.57.011———1.53.04.0———VdcVdcVdcOutput Drive Current(V OH = 2.5 Vdc) Source(V OH = 4.6 Vdc)(V OH = 9.5 Vdc)(V OH = 13.5 Vdc)I OH5.05.01015– 3.0– 0.64– 1.6– 4.2ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΗ———– 2.4– 0.51– 1.3– 3.4– 4.2– 0.88– 2.25– 8.8————– 1.7– 0.36– 0.9– 2.4————mAdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V OL = 0.4 Vdc) Sink(V OL = 0.5 Vdc)(V OL = 1.5 Vdc)I OL5.010150.641.64.2ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput CurrentI in 15 — — ±0.00001± 0.1 — ± 1.0 µAdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput Capacitance(V in = 0)C in—————0.511.33.40.882.258.8±ÎÎÎÎ0.1— — 5.0———7.50.360.92.4—————mAdcpFÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎQuiescent Current(Per Package)I DD5.01015———ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTotal Supply Current (5.) (6.)(Dynamic plus Quiescent,Per Package)(C L = 50 pF on all outputs, allbuffers switching)I T5.01015ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5.01020———0.0050.0100.015ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5.01020I T = (4.1 µA/kHz) f + I DDI T = (14 µA/kHz) f + I DDI T = (140 µA/kHz) f + I DD———150300600µAdcµAdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ I ÎÎÎTL 15 — — — ± µA 3.0ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ3–State Output Leakage ÎÎÎÎCurrent ± 0.1 ± 0.0001ÎÎÎÎ ± 0.1 ÎÎÎÎÎÎÎ4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.5. The formulas given are for the typical characteristics only at 25 C.6. To calculate total supply current at loads other than 50 pF:I T (C L ) = I T (50 pF) + (C L – 50) Vfkwhere: I T is in µA (per package), C L in pF, V = (V DD – V SS ) in volts, f in kHz is input frequency, and k = 0.001.ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎhttp://onsemi.com203

MC14094BSWITCHING CHARACTERISTICS (7.) (C L = 50 pF, T A = 25 C)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCharacteristicSymbolMin Typ (8.) Max UnitOutput Rise and Fall Timet TLH , t THL = (1.35 ns/pF) C L + 33 nst TLH , t THL = (0.6 ns/pF) C L + 20 nst TLH , t THL = (0.4 ns/pF) C L + 20 nsPropagation Delay TimeClock to Serial out QSt PLH , t PHL = (0.90 ns/pF) C L + 305 nst PLH , t PHL = (0.36 ns/pF) C L + 107 nst PLH , t PHL = (0.26 ns/pF) C L + 82 nst TLH ,t THLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎt PLH ,t PHLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎV DDVdc5.010155.01015——————10050403501259520010080600250190nsnsClock to Serial out Q’St PLH , t PHL = (0.90 ns/pF) C L + 350 nst PLH , t PHL = (0.36 ns/pF) C L + 149 nsÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎt PLH , t PHL = (0.26 ns/pF) C L + 62 ns5.01015———23011075460220150Clock to Parallel outt PLH , t PHL = (0.90 ns/pF) C L + 375 nst PLH , t PHL = (0.35 ns/pF) C L + 177 nsÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎt PLH , t PHL = (0.26 ns/pF) C L + 122 ns5.01015———420195135840390270Strobe to Parallel outt PLH , t PHL = (0.90 ns/pF) C L + 245 nst PLH , t PHL = (0.36 ns/pF) C L + 127 nsÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎt PLH , t PHL = (0.26 ns/pF) C L + 87 ns5.01015———290145100580290200Output Enable to Outputt PHZ , t PZL = (0.90 ns/pF) C L + 95 nst PHZ , t PZL = (0.36 ns/PF) C L + 57 nst PHZ , t PZL = (0.26 ns/pF) C L + 42 nst PHZ ,t PZLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎt PLZ , t PZH = (0.90 ns/pF) C L + 180 nst PLZ , t PZH = (0.36 ns/pF) C L + 77 nst PLZ , t PZH = (0.26 ns/pF) C L + 57 nst PLZ ,t PZHÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSetup TimeData in to Clockt suÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎHold TimeClock to Datat hÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎClock Pulse Width, Hight WHÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎClock Rise and Fall Timet r(cl)t f(cl)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎClock Pulse Frequencyf clÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎStrobe Pulse Widtht WLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ7. The formulas given are for the typical characteristics only at 25 C.5.010155.010155.010155.010155.01015510155.010155.01015——————12555350202020010083——————200807014075552259570603020– 40– 1008. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.1005040———2.55.06.01004035280150110450190140—————————155.04.01.252.53.0———nsnsnsµsMHznsÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎhttp://onsemi.com204

MC14094B3–STATE TEST CIRCUITFOR t PHZ AND t PZHV SSFOR t PLZ AND t PZLV DDO.E.DATASTCLOCK1 k50 pFOUTPUTBLOCK DIAGRAMREGISTER STAGE 1LATCH 1 3–STATE BUFFER 1CLOCK CLOCK STROBEV DD42*SERIALDATA INCLOCKCLOCKSTROBESTROBEQ1CLOCKCLOCKSTROBE15*OUTPUTENABLE23REGISTER STAGE 2REGISTER STAGE 3LATCH 2LATCH 33–STATE BUFFER 23–STATE BUFFER 356Q2Q34REGISTER STAGE 4LATCH 43–STATE BUFFER 47Q45REGISTER STAGE 5LATCH 53–STATE BUFFER 514Q56REGISTER STAGE 6LATCH 63–STATE BUFFER 613Q67REGISTER STAGE 7LATCH 73–STATE BUFFER 712Q78REGISTER STAGE 8LATCH 83–STATE BUFFER 811Q83*CLOCKCLOCKCLOCKCLOCK STROBE STROBE CLOCKCLOCKCLOCKCLOCK10Q′ S1 *STROBE *Input Protection DiodesSTROBESTROBECLOCK9Q Shttp://onsemi.com205

MC14094BDYNAMIC TIMING DIAGRAMt WH50%50%t WL t TLH3 CLOCK90%10 Q′ S 50%50%t su t h10%2 DATA IN1 STROBE15OUTPUT50% 50%ENABLEt PHLt PLHt PHZt PZHN90%90%90%Q1 Q710%10%10%10%t THLt PLHt PHL9 Q S50%50%t PLH t PHLt rt f90%t PZLhttp://onsemi.com206

The MC14099B is an 8–bit addressable latch. Data is entered inserial form when the appropriate latch is addressed (via address pinsA0, A1, A2) and write disable is in the low state. For the MC14099Bthe input is a unidirectional write only port.The data is presented in parallel at the output of the eight latchesindependently of the state of Write Disable, Write/Read or ChipEnable.A Master Reset capability is available on both parts.• Serial Data Input• Parallel Output• Master Reset• Supply Voltage Range = 3.0 Vdc to 18 Vdc• Capable of Driving Two Low–power TTL Loads or One Low–PowerSchottky TTL Load over the Rated Temperature Range• MC14099B pin for pin compatible with CD4099BMAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 2.)Symbol Parameter Value UnitV DD DC Supply Voltage Range –0.5 to +18.0 VV in , V out Input or Output Voltage Range(DC or Transient)–0.5 to V DD + 0.5 VI in , I outP DInput or Output Current(DC or Transient) per PinPower Dissipation,per Package (Note 3.)±10 mA500 mWT A Ambient Temperature Range –55 to +125 °CT stg Storage Temperature Range –65 to +150 °CT LLead Temperature(8–Second Soldering)260 °C2. Maximum Ratings are those values beyond which damage to the devicemay occur.3. Temperature Derating:Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 CThis device contains protection circuitry to guard against damage due to highstatic voltages or electric fields. However, precautions must be taken to avoidapplications of any voltage higher than maximum rated voltages to thishigh–impedance circuit. For proper operation, V in and V out should be constrainedto the range V SS (V in or V out ) V DD .Unused inputs must always be tied to an appropriate logic voltage level (e.g.,either V SS or V DD ). Unused outputs must be left open.ORDERING INFORMATIONDevice Package ShippingMC14099BCP PDIP–16 2000/BoxMC14099BDWhttp://onsemi.comPDIP–16P SUFFIXCASE 648SOIC–16DW SUFFIXCASE 751GSOEIAJ–16F SUFFIXCASE 966SOIC–16MARKINGDIAGRAMS2350/BoxMC14099BDWR2 SOIC–16 1000/Tape & Reel16A = Assembly LocationWL or L = Wafer LotYY or Y = YearWW or W = Work WeekMC14099BF SOEIAJ–16 See Note 1.MC14099BFEL SOEIAJ–16 See Note 1.1161MC14099BCPAWLYYWWMC14099BAWLYWW1. For ordering information on the EIAJ version ofthe SOIC packages, please contact your localON Semiconductor representative.16114099BAWLYYWW© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 3207 Publication Order Number:MC14099B/D

MC14099BQ7RESETDATAWRITEDISABLEA0PIN ASSIGNMENTA1A2V SS12345678161514131211109V DDQ6Q5Q4Q3Q2Q1Q0WRITE DISABLEDATAA0A1A2RESET567MC14099BDECODERV DD = 16V SS = 843828LATCHES91011121314151Q0Q1Q2Q3Q4Q5Q6Q7ELECTRICAL CHARACTERISTICS (Voltages Referenced to V SS )ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΖ 55 C 25 C 125 C ÎÎÎÎÎÎÎÎÎÎCharacteristicÎÎÎÎV DDÎÎÎMin Typ (4.) ÎÎÎÎÎMinÎÎÎ ÎÎÎÎÎÎÎÎÎMaxÎÎÎÎÎÎÎÎÎMaxUnitMaxÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput VoltageV in = V DD or 0“0” Level“1” LevelÎÎÎ Symbol VdcV OL 5.0 — 0.0510 — 0.0515 — 0.05ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎV in = 0 or V DDV OH5.010154.959.9514.95ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput Voltage“0” Level(V O = 4.5 or 0.5 Vdc)(V O = 9.0 or 1.0 Vdc)(V O = 13.5 or 1.5 Vdc)V IL5.01015——————0000.050.050.05ÎÎÎMin— 0.05 Vdc— 0.05— 0.05ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΗ——1.53.04.04.959.9514.95———5.010152.254.506.75———1.53.04.04.959.9514.95——————1.53.04.0VdcVdc(V O = 0.5 or 4.5 Vdc)(V O = 1.0 or 9.0 Vdc)(V O = 1.5 or 13.5 Vdc)“1” LevelV IH5.010153.57.011ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΗ——3.57.0112.755.508.25———3.57.011———VdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Drive Current(V OH = 2.5 Vdc) Source(V OH = 4.6 Vdc)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V OH = 9.5 Vdc)(V OH = 13.5 Vdc)(V OL = 0.4 Vdc) Sink(V OL = 0.5 Vdc)(V OL = 1.5 Vdc)I OHI OL5.05.010155.01015– 3.0– 0.64– 1.6– 4.20.641.64.2ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΗ———– 2.4– 0.51– 1.3– 3.4– 4.2– 0.88– 2.25– 8.8————– 1.7– 0.36– 0.9– 2.4ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput Current ÎÎÎÎÎÎ15 ÎÎÎ — ÎÎÎ ± 0.1ÎÎÎÎ — ÎÎΗ ÎÎÎ ± 1.0ÎÎÎ µAdcÎÎÎÎI inÎÎÎÎÎÎÎÎÎÎInput Capacitance (V in = ÎÎÎÎ0)C in ÎÎÎ — ÎÎΗ ÎÎÎ —ÎÎÎΗ ÎÎÎ 5.0ÎÎÎÎÎΗ ÎÎΗ ÎÎÎ pFÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΗ ÎÎÎ — ÎÎÎ —ÎÎÎÎ — ÎÎÎ 15 ÎÎÎΗ ÎÎÎ — ÎÎÎ pFInput CapacitanceMC14599B — Data (pin 3)(V in = 0)Quiescent Current(Per Package)C inI DD5.01015——————0.511.33.40.882.258.8———0.360.92.4± 0.1 ÎÎα0.00001ÎÎÎÎÎÎÎ7.522.5 ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTotal Supply Current (5.) (6.)(Dynamic plus Quiescent,Per Package)(C L = 50 pF on all outputs, allbuffers switching)I T5.01015ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5.01020———0.0050.0100.015ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5.01020I T = (1.5 µA/kHz) f + I DDI T = (3.0 µA/kHz) f + I DDI T = (4.5 µA/kHz) f + I DD4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.5. The formulas given are for the typical characteristics only at 25 C.6. To calculate total supply current at loads other than 50 pF:I T (C L ) = I T (50 pF) + (C L – 50) Vfkwhere: I T is in µA (per package), C L in pF, V = (V DD – V SS ) in volts, f in kHz is input frequency, and k = 0.004.——————————150300600mAdcmAdcµAdcµAdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎhttp://onsemi.com208

MC14099BSWITCHING CHARACTERISTICS (7.) (C L = 50 pF, T A = 25 C)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCharacteristicÎÎÎÎSymbolMin Typ (8.) ÎÎÎMaxÎÎÎÎUnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Rise and Fall Timet TLH , t THL = (1.35 ns/pF) C L + 32 nst TLH , t THL = (0.6 ns/pF) C L + 20 nst TLH , t THL = (0.4 ns/pF) C L + 20 nst TLH ,t THLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPropagation Delay TimeData to Output Qt PHL ,t PLHÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎWrite Disable to Output QÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎReset to Output QÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCE to Output Q (MC14599B only)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPropagation Delay Time, MC14599B onlyChip Enable, Write/Read to Datat PHL ,t PLHÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎAddress to DataÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPulse WidthsResett w(H)t w(L)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎWrite DisableÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSet Up TimeData to Write Disablet suÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎHold TimeWrite Disable to Datat hÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSet Up TimeAddress to Write DisableÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎRemoval TimeWrite Disable to Addresst sut remÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎV DDVdc5.010155.010155.010155.010155.010155.010155.010155.010155.010155.010155.010155.010155.01015—————————————————————1507550320160120100503515075501008040000100504020075502008060175806522510075200806520090757540251608060502520754025453010– 80– 40– 407. The formulas given are for the typical characteristics only at 25 C.8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.20010080400150100400160120350160130450200150400160130400180150——————————————————nsnsnsnsnsnsnsnsnsnsnsnsnshttp://onsemi.com209

MC14099BMC14099BFUNCTION DIAGRAMRESET29 Q0DATA3WRITEDISABLE4EACH LATCHA05TOOTHERLATCHESZEROSELECT10 Q111 Q2A16ADDRESSDECODEROTHER LATCHES12 Q313 Q414 Q5A2 7(M.S.B.)15 Q61 Q7WriteDisableResetTRUTH TABLEAddressedLatchUnaddressedLatches0 0 Data Q n *0 1 Data Reset 1 0 Q n * Q n *1 1 Reset Reset*Q n is previous state of latch.†Reset to zero state.CAUTION:To avoid unintentional data changes in the latches, WriteDisable must be active (high) during transitions on theaddress inputs A0, A1, and A2.http://onsemi.com210

MC14099BDATA ORWRITE DISABLE50%SWITCHING WAVEFORMSV DDV SSOUTPUT Qt PLH t PHL90%ADDRESS50%10%50%V DDV SSt su t w(L) t remt TLHt THLWRITEDISABLE50%V DDV SSt w(H)t sut hV DDV DDRESET50%DATA50%V SSV SSt PHLOUTPUT Qhttp://onsemi.com211

The MC14106B hex Schmitt Trigger is constructed with MOSP–channel and N–channel enhancement mode devices in a singlemonolithic structure. These devices find primary use where low powerdissipation and/or high noise immunity is desired. The MC14106Bmay be used in place of the MC14069UB hex inverter for enhancednoise immunity or to “square up” slowly changing waveforms.• Increased Hysteresis Voltage Over the MC14584B• Supply Voltage Range = 3.0 Vdc to 18 Vdc• Capable of Driving Two Low–power TTL Loads or One Low–powerSchottky TTL Load Over the Rated Temperature Range• Pin–for–Pin Replacement for CD40106B and MM74C14• Can Be Used to Replace the MC14584B or MC14069UBMAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 1.)Symbol Parameter Value UnitV DD DC Supply Voltage Range –0.5 to +18.0 VV in , V out Input or Output Voltage Range(DC or Transient)–0.5 to V DD + 0.5 VI in , I outP DInput or Output Current(DC or Transient) per PinPower Dissipation,per Package (Note 2.)±10 mA500 mWT A Ambient Temperature Range –55 to +125 °CT stg Storage Temperature Range –65 to +150 °CT LLead Temperature(8–Second Soldering)260 °C1. Maximum Ratings are those values beyond which damage to the devicemay occur.2. Temperature Derating:Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 CThis device contains protection circuitry to guard against damage due to highstatic voltages or electric fields. However, precautions must be taken to avoidapplications of any voltage higher than maximum rated voltages to thishigh–impedance circuit. For proper operation, V in and V out should be constrainedto the range V SS (V in or V out ) V DD .Unused inputs must always be tied to an appropriate logic voltage level (e.g.,either V SS or V DD ). Unused outputs must be left open.http://onsemi.comPDIP–14P SUFFIXCASE 646SOIC–14D SUFFIXCASE 751ATSSOP–14DT SUFFIXCASE 948GA = Assembly LocationWL or L = Wafer LotYY or Y = YearWW or W = Work WeekORDERING INFORMATIONMARKINGDIAGRAMSDevice Package ShippingMC14106BCP PDIP–14 2000/BoxMC14106BD SOIC–14 55/RailMC14106BDR2 SOIC–14 2500/Tape & Reel14MC14106BDT TSSOP–14 96/Rail1141MC14106BCPAWLYYWW14106BAWLYWW14106BALYWMC14106BDTR2 TSSOP–14 2500/Tape & Reel141© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 3212 Publication Order Number:MC14106B/D

MC14106BLOGIC DIAGRAM12345698111013 12V DD = PIN 14V SS = PIN 7EQUIVALENT CIRCUIT SCHEMATIC(1/6 OF CIRCUIT SHOWN)http://onsemi.com213

MC14106BELECTRICAL CHARACTERISTICS (Voltages Referenced to V SS )ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΖ 55 C 25 C 125 C V DDÎÎÎÎÎÎÎÎÎÎCharacteristic ÎÎÎÎÎÎÎMinÎÎÎMaxÎÎÎÎ MinÎÎÎÎÎTyp (3.) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎMaxMaxÎÎÎUnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput VoltageV in = V DD“0” Level“1” LevelÎÎÎ ÎÎÎSymbol VdcV OL 5.0 —10 —15 —ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎV in = 0Hysteresis VoltageV OHV H (6.)5.010155.010154.959.9514.950.31.21.60.050.050.05———0000.050.050.05ÎÎÎMin— 0.05 Vdc— 0.05— 0.05ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΗ——4.959.9514.955.01015———4.959.9514.95ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎThreshold VoltagePositive–GoingV T+5.010152.24.66.8ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎNegative–GoingV T–5.010150.92.54.0ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Drive Current(V OH = 2.5 Vdc) Source(V OH = 4.6 Vdc)(V OH = 9.5 Vdc)ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V OH = 13.5 Vdc)I OH5.05.01015– 3.0– 0.64– 1.6– 4.2ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V OL = 0.4 Vdc) Sink(V OL = 0.5 Vdc)(V OL = 1.5 Vdc)I OL5.010150.641.64.2ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ2.03.45.03.67.110.82.85.27.4————0.31.21.62.24.66.80.92.54.0– 2.4– 0.51– 1.3– 3.41.11.72.12.95.98.81.93.95.8– 4.2– 0.88– 2.25– 8.82.03.45.03.67.110.82.85.27.4————0.31.21.62.24.66.80.92.54.0– 1.7– 0.36– 0.9ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput Current ÎÎÎÎÎÎ15 — ÎÎÎ ÎÎÎ — — µAdcÎÎÎ ÎÎÎÎÎÎÎI inÎÎÎÎÎÎÎÎÎÎÎÎÎInput CapacitanceÎÎÎÎC ÎÎÎin — ÎÎÎ — ÎÎÎ —ÎÎÎÎ — ÎÎÎ 5.0ÎÎÎΗ ÎÎÎ — ÎÎÎ pF(V in = 0)———0.511.33.40.882.258.8———– 2.40.360.92.4———2.03.45.03.67.110.82.85.27.4———————VdcVdcVdcVdcmAdcmAdc± 0.1 ± 0.1 ± 1.0 ÎÎÎÎÎα0.00001ÎÎÎÎÎÎÎÎ7.5 ÎÎÎQuiescent Current(Per Package)I DD5.01015———ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTotal Supply Current (4.) (5.)(Dynamic plus Quiescent,Per Package)(C L = 50 pF on all outputs, allbuffers switching)I T5.01015ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ0.250.51.0———0.00050.00100.0015ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ0.250.51.0I T = (1.8 µA/kHz) f + I DDI T = (3.6 µA/kHz) f + I DDI T = (5.4 µA/kHz) f + I DD3. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.4. The formulas given are for the typical characteristics only at 25 C.5. To calculate total supply current at loads other than 50 pF:I T (C L ) = I T (50 pF) + (C L – 50) Vfkwhere I T is in µA (per package), C L in pF, V = (V DD – V SS ) in volts, f in kHz is input frequency, and k = 0.001.6. V = H V T+ – V T– (But maximum variation of V H is specified as less that V T+ max – V T– min ).———7.51530µAdcµAdchttp://onsemi.com214

MC14106BSWITCHING CHARACTERISTICS (C L = 50 pF, T A = 25 C)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCharacteristicSymbolMin Typ (7.) Max UnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Rise Timet TLH5.0 — 100 20010 — 50 10015 — 40 80Output Fall Timet THL5.0 — 100 20010 — 50 10015 — 40 80Propagation Delay Timet PLH , t PHL 5.0 — 125 25010 — 50 10015 — 40 807. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎV DDVdcnsnsÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎnsÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPULSEGENERATORINPUTV DD14OUTPUT7 V C SSL20 nsINPUTt PHLOUTPUT90%50%10%90%50%10%20 nst PLHV DDV SSV OHt ft rV OLFigure 1. Switching Time Test Circuit and WaveformsV DD0V out , OUTPUT VOLTAGE (Vdc)0V T– V T+V HV in , INPUT VOLTAGE (Vdc)Figure 2. Typical Transfer CharacteristicsV DDhttp://onsemi.com215

MC14106BAPPLICATIONSV inV outV HV DDV HV DDV inV inV SSV SSV DDV DDV outV outV SS(a) Schmitt Triggers will square upinputs with slow rise and fall times.Figure 3.(b) A Schmitt trigger offers maximumnoise immunity in gate applications.V SSV DDV DDRtwCtwRsRsV outV outCRtw = RC INV DDV T+Useful as Pushbutton/Keyboard Debounce Circuit.Figure 4. Monostable Multivibratorhttp://onsemi.com216

MC14106BR1ft1V inRACV outCVT*t1 RC lnVT–*t2 RC ln V DD – V T–VDD – VT1ft2RC ln*. V DD –VT–VDD –VT.. V TVT–.*V inAV outV DDV T+V SSV DDV T+V SSV DDV T+V SS*t 1 + t 2 t PHL + t PLH Useful in discriminating against short pulse durations.Figure 6. IntegratorFigure 5. Astable MultivibratorV inCV inR+ EDGE– EDGE + EDGE– EDGEV DDV inC C CtwR R Rtw = RC lnUseful as an edge detector circuit.V DDV T+Figure 7. DifferentiatorFigure 8. Positive Edge Time Delay Circuithttp://onsemi.com217

The MC14174B hex type D flip–flop is constructed with MOSP–channel and N–channel enhancement mode devices in a singlemonolithic structure. Data on the D inputs which meets the setup timerequirements is transferred to the Q outputs on the positive edge of theclock pulse. All six flip–flops share common clock and reset inputs.The reset is active low, and independent of the clock.• Static Operation• All Inputs and Outputs Buffered• Diode Protection on All Inputs• Supply Voltage Range = 3.0 Vdc to 18 Vdc• Capable of Driving Two Low–Power TTL Loads or One Low–PowerSchottky TTL Load over the Rated Temperature Range• Functional Equivalent to TTL 74174MAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 2.)Symbol Parameter Value UnitV DD DC Supply Voltage Range –0.5 to +18.0 VV in , V out Input or Output Voltage Range(DC or Transient)–0.5 to V DD + 0.5 VI in , I outP DInput or Output Current(DC or Transient) per PinPower Dissipation,per Package (Note 3.)±10 mA500 mWT A Ambient Temperature Range –55 to +125 °CT stg Storage Temperature Range –65 to +150 °CT LLead Temperature(8–Second Soldering)260 °C2. Maximum Ratings are those values beyond which damage to the devicemay occur.3. Temperature Derating:Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 CThis device contains protection circuitry to guard against damage due to highstatic voltages or electric fields. However, precautions must be taken to avoidapplications of any voltage higher than maximum rated voltages to thishigh–impedance circuit. For proper operation, V in and V out should be constrainedto the range V SS (V in or V out ) V DD .Unused inputs must always be tied to an appropriate logic voltage level (e.g.,either V SS or V DD ). Unused outputs must be left open.http://onsemi.comPDIP–16P SUFFIXCASE 648SOIC–16D SUFFIXCASE 751BSOEIAJ–16F SUFFIXCASE 966A = Assembly LocationWL or L = Wafer LotYY or Y = YearWW or W = Work WeekORDERING INFORMATIONMARKINGDIAGRAMSDevice Package ShippingMC14174BCP PDIP–16 2000/BoxMC14174BD SOIC–16 48/RailMC14174BDR2 SOIC–16 2500/Tape & Reel1. For ordering information on the EIAJ version ofthe SOIC packages, please contact your localON Semiconductor representative.161161161MC14174BCPAWLYYWW14174BAWLYWWMC14174BAWLYWWMC14174BF SOEIAJ–16 See Note 1.MC14174BFEL SOEIAJ–16 See Note 1.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 3218 Publication Order Number:MC14174B/D

MC14174BPIN ASSIGNMENTR116V DDQ0215Q5D0314D5D1413D4Q1512Q4D2611D3Q2710Q3V SS89CBLOCK DIAGRAM9CLOCKQ02134RESETD0D1Q1Q25761113D2D3D4Q3Q4101214D5Q515V DD = PIN 16V SS = PIN 8TRUTH TABLE(Positive Logic)InputsOutputClock Data Reset Q0 1 01 1 1X 1 QX X 0 0X = Don’t CareNoChangehttp://onsemi.com219

MC14174BELECTRICAL CHARACTERISTICS (Voltages Referenced to V SS )ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΖ 55 C 25 C 125 C V DDÎÎÎÎÎÎÎÎÎÎCharacteristic ÎÎÎÎÎÎÎMinÎÎÎMaxÎÎÎÎ MinÎÎÎÎÎTyp (4.) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎMaxMaxÎÎÎUnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput VoltageV in = V DD or 0“0” Level“1” LevelÎÎÎ ÎÎÎSymbol VdcV OL 5.0 —10 —15 —ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎV in = 0 or V DDInput Voltage(V O = 4.5 or 0.5 Vdc)(V O = 9.0 or 1.0 Vdc)(V O = 13.5 or 1.5 Vdc)“0” LevelV OHV IL5.010154.959.9514.950.050.050.05———0000.050.050.05ÎÎÎMin— 0.05 Vdc— 0.05— 0.05ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5.01015——————4.959.9514.955.01015———4.959.9514.95ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V O = 0.5 or 4.5 Vdc)(V O = 1.0 or 9.0 Vdc)(V O = 1.5 or 13.5 Vdc)“1” LevelV IH5.010153.57.011ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ1.53.04.0——————3.57.0112.254.506.752.755.508.251.53.04.0——————3.57.011———1.53.04.0———VdcVdcVdcOutput Drive Current(V OH = 2.5 Vdc) Source(V OH = 4.6 Vdc)(V OH = 9.5 Vdc)(V OH = 13.5 Vdc)I OH5.05.01015– 3.0– 0.64– 1.6– 4.2ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΗ———– 2.4– 0.51– 1.3– 3.4– 4.2– 0.88– 2.25– 8.8————– 1.7– 0.36– 0.9– 2.4————mAdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V OL = 0.4 Vdc) Sink(V OL = 0.5 Vdc)(V OL = 1.5 Vdc)I OL5.010150.641.64.2ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎInput CurrentI in 15 — ÎÎÎÎÎÎÎΗ±0.00001± 0.1 — ÎÎεAdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput Capacitance(V in = 0)C in—————0.511.33.40.882.258.8±ÎÎÎÎ0.1— — 5.0———7.50.360.92.4————mAdc±ÎÎÎ1.0— pFÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎQuiescent Current(Per Package)I DD5.01015———ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTotal Supply Current (5.) (6.)(Dynamic plus Quiescent,Per Package)(C L = 50 pF on all outputs, allbuffers switching)I T5.01015ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5.01020———0.0050.0100.015ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5.01020I T = (1.1 µA/kHz) f + I DDI T = (2.3 µA/kHz) f + I DDI T = (3.7 µA/kHz) f + I DD4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.5. The formulas given are for the typical characteristics only at 25 C.6. To calculate total supply current at loads other than 50 pF:I T (C L ) = I T (50 pF) + (C L – 50) Vfkwhere: I T is in µA (per package), C L in pF, V = (V DD – V SS ) in volts, f in kHz is input frequency, and k = 0.003.———150300600µAdcµAdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎhttp://onsemi.com220

SWITCHING CHARACTERISTICS (7.) (C L = 50 pF, T A = 25 C)CharacteristicMC14174BSymbolt TLH , t THLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMinTyp (8.) Max ÎÎÎOutput Rise and Fall Timet TLH , t THL = (1.35 ns/pF) C L + 32 nst TLH , t THL = (0.6 ns/pF) C L + 20 nst TLH , t THL = (0.4 ns/pF) C L + 20 nsV DDVdcAll TypesÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPropagation Delay Time — Clock to Qt PLH , t PHL = (0.9 ns/pF) C L + 165 nst PLH , t PHL = (0.36 ns/pF) C L + 64 nst PLH , t PHL = (0.26 ns/pF) C L + 52 nsPropagation Delay Time — Reset to Qt PHL = (0.9 ns/pF) C L + 205 nst PHL = (0.36 ns/pF) C L + 79 nst PHL = (0.26 ns/pF) C L + 62 nst PLH , t PHLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎt PHLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎClock Pulse Widtht WHÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎReset Pulse Widtht WLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎClock Pulse Frequencyf clÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎClock Pulse Rise and Fall Timet TLH , t THLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎData Setup Timet suÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎData Hold Timet hÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎReset Removal TimeÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ7. The formulas given are for the typical characteristics only at 25 C.8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.t remÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5.010155.010155.010155.010155.010155.010155.010155.010155.010155.01015—————————150907020010080——————40201580403025010080100504021085652501007575453510050407.01215.5———20100402015125504020010080400160120500200150——————2.05.06.5155.04.0—————————UnitnsnsnsnsnsmHzsnsnsnshttp://onsemi.com221

MC14174BTIMING DIAGRAMFUNCTIONAL BLOCK DIAGRAMhttp://onsemi.com222

The MC14175B quad type D flip–flop is constructed with MOSP–channel and N–channel enhancement mode devices in a singlemonolithic structure. Each of the four flip–flops is positive–edgetriggered by a common clock input (C). An active–low reset input (R)asynchronously resets all flip–flops. Each flip–flop has independentData (D) inputs and complementary outputs (Q and Q). These devicesmay be used as shift register elements or as type T flip–flops forcounter and toggle applications.• Complementary Outputs• Static Operation• All Inputs and Outputs Buffered• Diode Protection on All Inputs• Supply Voltage Range = 3.0 Vdc to 18 Vdc• Output Compatible with Two Low–Power TTL Loads or OneLow–Power Schottky TTL Load• Functional Equivalent to TTL 74175MAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 2.)Symbol Parameter Value UnitV DD DC Supply Voltage Range –0.5 to +18.0 VV in , V out Input or Output Voltage Range(DC or Transient)–0.5 to V DD + 0.5 VI in , I outP DInput or Output Current(DC or Transient) per PinPower Dissipation,per Package (Note 3.)±10 mA500 mWT A Ambient Temperature Range –55 to +125 °CT stg Storage Temperature Range –65 to +150 °CT LLead Temperature(8–Second Soldering)260 °C2. Maximum Ratings are those values beyond which damage to the devicemay occur.3. Temperature Derating:Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 CThis device contains protection circuitry to guard against damage due to highstatic voltages or electric fields. However, precautions must be taken to avoidapplications of any voltage higher than maximum rated voltages to thishigh–impedance circuit. For proper operation, V in and V out should be constrainedto the range V SS (V in or V out ) V DD .Unused inputs must always be tied to an appropriate logic voltage level (e.g.,either V SS or V DD ). Unused outputs must be left open.http://onsemi.comPDIP–16P SUFFIXCASE 648SOIC–16D SUFFIXCASE 751BSOEIAJ–16F SUFFIXCASE 966A = Assembly LocationWL or L = Wafer LotYY or Y = YearWW or W = Work WeekORDERING INFORMATIONMARKINGDIAGRAMSDevice Package ShippingMC14175BCP PDIP–16 2000/BoxMC14175BD SOIC–16 48/RailMC14175BDR2 SOIC–16 2500/Tape & Reel1. For ordering information on the EIAJ version ofthe SOIC packages, please contact your localON Semiconductor representative.161161161MC14175BCPAWLYYWW14175BAWLYWWMC14175BAWLYWWMC14175BF SOEIAJ–16 See Note 1.MC14175BFEL SOEIAJ–16 See Note 1.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 3223 Publication Order Number:MC14175B/D

MC14175BPIN ASSIGNMENTR116V DDQ0215Q3Q0314Q3D0413D3D1512D2Q1611Q2Q1710Q2V SS89CBLOCK DIAGRAM9CLOCKQ0214RESETD0Q0Q1Q1376512D1D2Q2Q2Q310111513D3Q314V DD = PIN 16V SS = PIN 8TRUTH TABLEInputsOutputsClock Data Reset Q Q0 1 0 11 1 1 0X 1 Q QX X 0 0 1X = Don’t CareNoChangehttp://onsemi.com224

MC14175BELECTRICAL CHARACTERISTICS (Voltages Referenced to V SS )ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΖ 55 C 25 C 125 C V DDÎÎÎÎÎÎÎÎÎÎCharacteristic ÎÎÎÎÎÎÎMinÎÎÎMaxÎÎÎÎ MinÎÎÎÎÎTyp (4.) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎMaxMaxÎÎÎUnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput VoltageV in = V DD or 0“0” Level“1” LevelÎÎÎ ÎÎÎSymbol VdcV OL 5.0 —10 —15 —ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎV in = 0 or V DDInput Voltage(V O = 4.5 or 0.5 Vdc)(V O = 9.0 or 1.0 Vdc)(V O = 13.5 or 1.5 Vdc)“0” LevelV OHV IL5.010154.959.9514.950.050.050.05———0000.050.050.05ÎÎÎMin— 0.05 Vdc— 0.05— 0.05ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5.01015——————4.959.9514.955.01015———4.959.9514.95ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V O = 0.5 or 4.5 Vdc)(V O = 1.0 or 9.0 Vdc)(V O = 1.5 or 13.5 Vdc)“1” LevelV IH5.010153.57.011ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ1.53.04.0——————3.57.0112.254.506.752.755.508.251.53.04.0——————3.57.011———1.53.04.0———VdcVdcVdcOutput Drive Current(V OH = 2.5 Vdc) Source(V OH = 4.6 Vdc)(V OH = 9.5 Vdc)(V OH = 13.5 Vdc)I OH5.05.01015– 3.0– 0.64– 1.6– 4.2ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΗ———– 2.4– 0.51– 1.3– 3.4– 4.2– 0.88– 2.25– 8.8————– 1.7– 0.36– 0.9– 2.4————mAdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V OL = 0.4 Vdc) Sink(V OL = 0.5 Vdc)(V OL = 1.5 Vdc)I OL5.010150.641.64.2ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎInput CurrentI in 15 — ÎÎÎÎÎÎÎΗ±0.00001± 0.1 — ÎÎεAdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput Capacitance(V in = 0)C in—————0.511.33.40.882.258.8±ÎÎÎÎ0.1— — 5.0———7.50.360.92.4————mAdc±ÎÎÎ1.0— pFÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎQuiescent Current(Per Package)I DD5.01015———ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTotal Supply Current (5.) (6.)(Dynamic plus Quiescent,Per Package)(C L = 50 pF on all outputs, allbuffers switching)I T5.01015ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5.01020———0.0050.0100.015ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5.01020I T = (1.7 µA/kHz) f + I DDI T = (3.4 µA/kHz) f + I DDI T = (5.0 µA/kHz) f + I DD4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.5. The formulas given are for the typical characteristics only at 25 C.6. To calculate total supply current at loads other than 50 pF:I T (C L ) = I T (50 pF) + (C L – 50) Vfkwhere: I T is in µA (per package), C L in pF, V = (V DD – V SS ) in volts, f in kHz is input frequency, and k = 0.004.———150300600µAdcµAdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎhttp://onsemi.com225

SWITCHING CHARACTERISTICS (7.) (C L = 50 pF, T A = 25 C)CharacteristicMC14175BSymbolt TLH , t THLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMinTyp (8.) Max ÎÎÎOutput Rise and Fall Timet TLH , t THL = (1.35 ns/pF) C L + 32 nst TLH , t THL = (0.6 ns/pF) C L + 20 nst TLH , t THL = (0.4 ns/pF) C L + 20 nsV DDVdcAll TypesÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPropagation Delay Time — Clock to Q, Qt PLH , t PHL = (0.9 ns/pF) C L + 175 nst PLH , t PHL = (0.36 ns/pF) C L + 72 nst PLH , t PHL = (0.26 ns/pF) C L + 57 nsPropagation Delay Time — Reset to Q, Qt PHL = (0.9 ns/pF) C L + 280 nst PHL = (0.36 ns/pF) C L + 112 nst PHL = (0.26 ns/pF) C L + 87 nst PLH , t PHLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎt PHL , t PLHÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎClock Pulse Widtht WHÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎReset Pulse Widtht WLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎClock Pulse Frequencyf clÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎClock Pulse Rise and Fall Timet TLH , t THLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎData Setup Timet suÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎData Hold Timet hÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎReset Removal TimeÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ7. The formulas given are for the typical characteristics only at 25 C.8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.t remÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5.010155.010155.010155.010155.010155.010155.010155.010155.010155.01015—————————250100752008060——————12050408040302501008010050402209070325130100110453510040304.51114———602520402015125504020010080400160120500200150——————2.05.06.5155.04.0—————————UnitnsnsnsnsnsmHzsnsnsnshttp://onsemi.com226

MC14175BTIMING DIAGRAMFUNCTIONAL BLOCK DIAGRAMhttp://onsemi.com227

The MC14490 is constructed with complementary MOSenhancement mode devices, and is used for the elimination ofextraneous level changes that result when interfacing with mechanicalcontacts. The digital contact bounce eliminator circuit takes an inputsignal from a bouncing contact and generates a clean digital signalfour clock periods after the input has stabilized. The bounce eliminatorcircuit will remove bounce on both the “make” and the “break” of acontact closure. The clock for operation of the MC14490 is derivedfrom an internal R–C oscillator which requires only an externalcapacitor to adjust for the desired operating frequency (bounce delay).The clock may also be driven from an external clock source or theoscillator of another MC14490 (see Figure 5).NOTE: Immediately after power–up, the outputs of the MC14490are in indeterminate states.• Diode Protection on All Inputs• Six Debouncers Per Package• Internal Pullups on All Data Inputs• Can Be Used as a Digital Integrator, System Synchronizer, or DelayLine• Internal Oscillator (R–C), or External Clock Source• TTL Compatible Data Inputs/Outputs• Single Line Input, Debounces Both “Make” and “Break” Contacts• Does Not Require “Form C” (Single Pole Double Throw) InputSignal• Cascadable for Longer Time Delays• Schmitt Trigger on Clock Input (Pin 7)• Supply Voltage Range = 3.0 V to 18 V• Chip Complexity: 546 FETs or 136.5 Equivalent GatesMAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 2.)Symbol Parameter Value UnitV DD DC Supply Voltage Range –0.5 to +18.0 VV in , V out Input or Output Voltage Range(DC or Transient)–0.5 to V DD + 0.5 VI inP DInput Current(DC or Transient) per PinPower Dissipation,per Package (Note 3.)±10 mA500 mWT A Ambient Temperature Range –55 to +125 °CT stg Storage Temperature Range –65 to +150 °CT LLead Temperature(8–Second Soldering)260 °C2. Maximum Ratings are those values beyond which damage to the devicemay occur.3. Temperature Derating:Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 Chttp://onsemi.comPDIP–16P SUFFIXCASE 648SOIC–16DW SUFFIXCASE 751GSOEIAJ–16F SUFFIXCASE 9661A = Assembly LocationWL or L = Wafer LotYY or Y = YearWW or W = Work WeekORDERING INFORMATIONMARKINGDIAGRAMSDevice Package ShippingMC14490DW SOIC–16 47/RailMC14490DWR2 SOIC–16 1000/Tape & ReelMC14490F SOEIAJ–16 See Note 1.1. For ordering information on the EIAJ version ofthe SOIC packages, please contact your localON Semiconductor representative.16161MC14490PAWLYYWWMC14490FEL SOEIAJ–16 See Note 1.MC14490P PDIP–16 25/Rail114490AWLYYWWThis device contains protection circuitry to guardagainst damage due to high static voltages or electricfields. However, precautions must be taken to avoid applicationsof any voltage higher than maximum ratedvoltages to this high–impedance circuit. For properoperation, V in and V out should be constrained to therange V SS (V in or V out ) V DD .Unused inputs must always be tied to an appropriatelogic voltage level (e.g., either V SS or V DD ). Unused outputsmust be left open.16MC14490AWLYWW© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 3228 Publication Order Number:MC14490/D

MC14490PIN ASSIGNMENTA in116V DDB out215A outC in314B inD out413C outE in512D inF out611E outOSC in710F inV SS89OSC outBLOCK DIAGRAMA in 1+V DDφ 1DATA4–BIT STATIC SHIFT REGISTERSHIFT LOAD1/2–BITDELAY15 A outOSC in 7OSC out 9OSCILLATORANDTWO–PHASECLOCK GENERATORφ 2φ 1 φ 2φ 1 φ 2φ 1 φ 2V DD = PIN 16V SS = PIN 8B in 14IDENTICAL TO ABOVE STAGE2 B outφ 1 φ 2C in 3IDENTICAL TO ABOVE STAGE13 C outφ 1 φ 2D in 12IDENTICAL TO ABOVE STAGE4 D outφ 1 φ 2E in 5IDENTICAL TO ABOVE STAGE11 E outφ 1 φ 2F in 10IDENTICAL TO ABOVE STAGE6 F outhttp://onsemi.com229

MC14490ELECTRICAL CHARACTERISTICS (Voltages Referenced to V SS )ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎV – 55 C 25 C 125 C DDCharacteristicÎÎÎÎMin ÎÎÎMax ÎÎÎÎÎMinÎÎÎÎÎÎÎÎÎTyp (4.) ÎÎÎÎÎMaxUnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Voltage “0” LevelÎÎÎÎÎÎ5.0ÎÎΗÎÎÎ0.05ÎÎÎΗÎÎÎ0ÎÎÎÎ0.05ÎÎΗÎÎÎ0.05ÎÎÎVdcV in = V DD or 0V in = 0 or V DD“1” LevelÎÎÎ ÎÎÎSymbol VdcV OL10 — 0.0515 — 0.05V OH5.010154.959.9514.95Min ÎÎÎ Max ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput Voltage “0” Level(V O = 4.5 or 0.5 Vdc)(V O = 9.0 or 1.0 Vdc)ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V O = 13.5 or 1.5 Vdc)V IL5.01015———ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V O = 0.5 or 4.5 Vdc) “1 Level”(V O = 1.0 or 9.0 Vdc)(V O = 1.5 or 13.5 Vdc)V IH5.010153.57.011ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Drive CurrentOscillator Output(V OH = 2.5 V)(V OH = 4.6 V)(V OH = 9.5 V)(V OH = 13.5 V)SourceI OH5.05.01015– 0.6– 0.12– 0.23– 1.4ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎDebounce Outputs(V OH = 2.5 V)(V OH = 4.6 V)(V OH = 9.5 V)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V OH = 13.5 V)Oscillator Output(V OL = 0.4 V)(V OL = 0.5 V)(V OL = 1.5 V)SinkI OL5.05.01015– 0.9– 0.19– 0.61.8———1.53.04.0—————————4.959.9514.95———3.57.011– 0.5– 0.1– 0.2– 1.2005.010152.254.506.752.755.508.25– 1.5– 0.3– 0.8– 3.00.050.05———1.53.04.0—————————4.959.9514.95———3.57.011– 0.4– 0.08– 0.16– 1.0ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5.010150.360.94.2ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎDebounce Outputs(V OL = 0.4 V)(V OL = 0.5 V)(V OL = 1.5 V)5.010152.64.012————– 0.75– 0.16– 0.5– 1.5– 2.2– 0.46– 1.2– 4.5————– 0.6– 0.12– 0.4ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput CurrentÎÎÎÎÎÎ15 — 2.0 — 0.2 — 11 µAdcÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎDebounce Inputs (V in = V DD )I IHÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎI in 15 ÎÎÎ — ÎÎÎ — ÎÎΗ ÎÎÎÎÎÎεAdcÎÎÎInput Current Oscillator — Pin 7(V in = V SS or V DD )Pullup Resistor Source CurrentDebounce Inputs(V in = V SS )I IL5.01015175340505——————0.30.753.52.23.3100.92.3104.09.035——————– 1.20.240.62.81.82.78.12.0 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎInput CapacitanceC in — — ÎÎÎΗ ÎÎΗ 5.0 7.5 — ÎÎΗ ÎÎÎpFÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎQuiescent Current(V in = V SS or V DD , I out = 0 µA)I SS5.01015———0.050.05———1.53.04.0—————————————————VdcVdcVdcmAdcmAdcÎÎÎÎ ÎÎÎÎÎÎÎÎα 620 ± 255 ± 400 ± 250375 140 190 255 70 225 µAdc740 280 380 500 145 4401100 415 570 750 215 6604. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ150280840———4090225100225650———90180550µAdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎhttp://onsemi.com230

MC14490SWITCHING CHARACTERISTICS (5.) (C L = 50 pF, T A = 25 C)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎCharacteristicSymbolMin Typ (6.) Max UnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Rise TimeAll OutputsOutput Fall TimeOscillator Outputt TLHÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎt THLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎDebounce OutputsPropagation Delay TimeOscillator Input to Debounce Outputst THLt PHLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎt PLHÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎClock Frequency (50% Duly Cycle)(External Clock)f clÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSetup Time (See Figure 1)t suÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMaximum External Clock InputRise and Fall TimeOscillator Inputt r , t fÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOscillator FrequencyOSC outC ext ≥ 100 pF*ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎNote: These equations are intended to be a design guide.Laboratory experimentation may be required. Formulasare typically ± 15% of actual frequencies.f osc , typV DDVdc5.010155.010155.010155.010155.010155.010155.010155.01015——————————————————100806018090651005040603020285120953701601202.869504030No LimitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5. The formulas given are for the typical characteristics only at 25 C.6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ*POWER–DOWN CONSIDERATIONSLarge values of C ext may cause problems when powering down the MC14490 because of the amount of energy stored in thecapacitor. When a system containing this device is powered down, the capacitor may discharge through the input protectiondiodes at Pin 7 or the parasitic diodes at Pin 9. Current through these internal diodes must be limited to 10 mA, therefore theturn–off time of the power supply must not be faster than t = (V DD – V SS ) C ext /(10 mA). For example, If V DD – V SS = 15V and C ext = 1 µF, the power supply must turn off no faster than t = (15 V) (1 µF)/10 mA = 1.5 ms. This is usually not a problembecause power supplies are heavily filtered and cannot discharge at this rate.When a more rapid decrease of the power supply to zero volts occurs, the MC14490 may sustain damage. To avoid thispossibility, use external clamping diodes, D1 and D2, connected as shown in Figure 2.OSC in50%V DD0 V5.010153601801302001008012060405702401907403202401.43.04.5———nsnsnsMHznsnsHzt PLHV DD V DDA out90%D1D2A out50%10%t rt ft PHL90%10% 50%7OSC inC ext9OSC outOSC inA in50%50%t suFigure 1. Switching WaveformsV DD0 VV DD0 VMC14490Figure 2. Discharge Protection During Power Downhttp://onsemi.com231

MC14490THEORY OF OPERATIONThe MC14490 Hex Contact Bounce Eliminator isbasically a digital integrator. The circuit can integrate bothup and down. This enables the circuit to eliminate bounce onboth the leading and trailing edges of the signal, shown in thetiming diagram of Figure 3.Each of the six Bounce Eliminators is composed of a4–1/2–bit register (the integrator) and logic to compare theinput with the contents of the shift register, as shown inFigure 4. The shift register requires a series of timing pulsesin order to shift the input signal into each shift registerlocation. These timing pulses (the clock signal) arerepresented in the upper waveform of Figure 3. Each of thesix Bounce Eliminator circuits has an internal resistor asshown in Figure 4. A pullup resistor was incorporated ratherthan a pulldown resistor in order to implement switchedground input signals, such as those coming from relaycontacts and push buttons. By switching ground, rather thana power supply lead, system faults (such as shorts to groundon the signal input leads) will not cause excessive currentsin the wiring and contacts. Signal lead shorts to ground aremuch more probable than shorts to a power supply lead.When the relay contact is closed, (see Figure 4) the lowlevel is inverted, and the shift register is loaded with a highon each positive edge of the clock signal. To understand theoperation, we assume all bits of the shift register are loadedwith lows and the output is at a high level.At clock edge 1 (Figure 3) the input has gone low and ahigh has been loaded into the first bit or storage location ofthe shift register. Just after the positive edge of clock 1, theinput signal has bounced back to a high. This causes the shiftregister to be reset to lows in all four bits — thus starting thetiming sequence over again.During clock edges 3 to 6 the input signal has stayed low.Thus, a high has been shifted into all four shift register bitsand, as shown, the output goes low during the positive edgeof clock pulse 6.It should be noted that there is a 3–1/2 to 4–1/2 clockperiod delay between the clean input signal and outputsignal. In this example there is a delay of 3.8 clock periodsfrom the beginning of the clean input signal.After some time period of N clock periods, the contact isopened and at N+1 a low is loaded into the first bit. Just afterN+1, when the input bounces low, all bits are set to a high.At N+2 nothing happens because the input and output arelow and all bits of the shift register are high. At time N+3and thereafter the input signal is a high, clean signal. At thepositive edge of N+6 the output goes high as a result of fourlows being shifted into the shift register.Assuming the input signal is long enough to be clockedthrough the Bounce Eliminator, the output signal will be nolonger or shorter than the clean input signal plus or minusone clock period.The amount of time distortion between the input andoutput signals is a function of the difference in bouncecharacteristics on the edges of the input signal and the clockfrequency. Since most relay contacts have more bouncewhen making as compared to breaking, the overall delay,counting bounce period, will be greater on the leading edgeof the input signal than on the trailing edge. Thus, the outputsignal will be shorter than the input signal — if the leadingedge bounce is included in the overall timing calculation.The only requirement on the clock frequency in order toobtain a bounce free output signal is that four clock periodsdo not occur while the input signal is in a false state.Referring to Figure 3, a false state is seen to occur three timesat the beginning of the input signal. The input signal goeslow three times before it finally settles down to a valid lowstate. The first three low pulses are referred to as false states.If the user has an available clock signal of the properfrequency, it may be used by connecting it to the oscillatorinput (pin 7). However, if an external clock is not availablethe user can place a small capacitor across the oscillatorinput and output pins in order to start up an internal clocksource (as shown in Figure 4). The clock signal at theoscillator output pin may then be used to clock otherMC14490 Bounce Eliminator packages. With the use of theMC14490, a large number of signals can be cleaned up, withthe requirement of only one small capacitor external to theHex Bounce Eliminator packages.123456N + 1N + 3N + 5N + 7OSC in OR OSC outINPUTOUTPUTCONTACTOPENCONTACTBOUNCINGCONTACT CLOSED(VALID TRUE SIGNAL)CONTACTBOUNCINGCONTACT OPENFigure 3. Timing Diagramhttp://onsemi.com232

MC14490+V DDPULLUP RESISTOR(INTERNAL)A in1“FORM A”CONTACTOSC in 7 OSCILLATORφ 1ANDC ext 9 TWO–PHASEOSCCLOCK GENERATOR φ 2outDATA4–BIT STATIC SHIFT REGISTERSHIFT LOADφ 1 φ 21/2 BITDELAYφ 1 φ 215AoutFigure 4. Typical “Form A” Contact Debounce Circuit(Only One Debouncer Shown)OPERATING CHARACTERISTICSThe single most important characteristic of the MC14490is that it works with a single signal lead as an input, makingit directly compatible with mechanical contacts (Form Aand B).The circuit has a built–in pullup resistor on each input.The worst case value of the pullup resistor (determined fromthe Electrical Characteristics table) is used to calculate thecontact wetting current. If more contact current is required,an external resistor may be connected between V DD and theinput.Because of the built–in pullup resistors, the inputs cannotbe driven with a single standard CMOS gate when V DD isbelow 5 V. At this voltage, the input should be driven withparalleled standard gates or by the MC14049 or MC14050buffers.The clock input circuit (pin 7) has Schmitt trigger shapingsuch that proper clocking will occur even with very slowclock edges, eliminating any need for clock preshaping. Inaddition, other MC14490 oscillator inputs can be drivenfrom a single oscillator output buffered by an MC14050 (seeFigure 5). Up to six MC14490s may be driven by a singlebuffer.The MC14490 is TTL compatible on both the inputs andthe outputs. When V DD is at 4.5 V, the buffered outputs cansink 1.6 mA at 0.4 V. The inputs can be driven with TTL asa result of the internal input pullup resistors.C ext1/6 MC14050OSC in 7NO CONNECTION9 OSC outOSC in79OSC outFROMCONTACTSMC14490TO SYSTEMLOGICFROM CONTACTSMC14490TO SYSTEMLOGICOSC in 7NO CONNECTION9 OSC outFROM CONTACTSMC14490TO SYSTEMLOGICFigure 5. Typical Single Oscillator Debounce Systemhttp://onsemi.com233

MC14490TYPICAL APPLICATIONSASYMMETRICAL TIMINGIn applications where different leading and trailing edgedelays are required (such as a fast attack/slow release timer.)Clocks of different frequencies can be gated into theMC14490 as shown in Figure 6. In order to produce a slowattack/fast release circuit leads A and B should beinterchanged. The clock out lead can then be used to feedclock signals to the other MC14490 packages where theasymmetrical input/output timing is required.OSC inINMC14490MC14011BOUTOSC outMULTIPLE TIMING SIGNALSAs shown in Figure 8, the Bounce Eliminator circuits canbe connected in series. In this configuration each output isdelayed by four clock periods relative to its respective input.This configuration may be used to generate multiple timingsignals such as a delay line, for programming other timingoperations.One application of the above is shown in Figure 9, whereit is required to have a single pulse output for a singleoperation (make) of the push button or relay contact. Thisonly requires the series connection of two BounceEliminator circuits, one inverter, and one NOR gate in orderto generate the signal AB as shown in Figures 9 and 10. Thesignal AB is four clock periods in length. If the inverter isswitched to the A output, the pulse AB will be generatedupon release or break of the contact. With the use of a fewadditional parts many different pulses and waveshapes maybe generated.AB1A inB.E. 115A outEXTERNALCLOCKf C÷ Nf C/N14B inB.E. 22B outFigure 6. Fast Attack/Slow Release CircuitLATCHED OUTPUTThe contents of the Bounce Eliminator can be latched byusing several extra gates as shown in Figure 7. If the latchlead is high the clock will be stopped when the output goeslow. This will hold the output low even though the input hasreturned to the high state. Any time the clock is stopped theoutputs will be representative of the input signal four clockperiods earlier.3C in12D in5E inB.E. 3B.E. 4B.E. 513411C outD outE outINMC14490OUT10F inB.E. 66F outOSC inOSC outCLOCKMC14011B7 9OSC in CLOCKOSC outLATCH = 1UNLATCH = 0Figure 7. Latched Output CircuitFigure 8. Multiple Timing Circuit Connectionshttp://onsemi.com234

MC14490AINBE 1OUTAINBE 2A ≡ ACTIVE LOWB ≡ ACTIVE LOWOUTBBABFigure 9. Single Pulse Output CircuitOSC in OROSC outINPUTABCDEFABABFigure 10. Multiple Output Signal Timing Diagramhttp://onsemi.com235

The MC14503B is a hex non–inverting buffer with 3–state outputs,and a high current source and sink capability. The 3–state outputsmake it useful in common bussing applications. Two disable controlsare provided. A high level on the Disable A input causes the outputs ofbuffers 1 through 4 to go into a high impedance state and a high levelon the Disable B input causes the outputs of buffers 5 and 6 to go into ahigh impedance state.• 3–State Outputs• TTL Compatible — Will Drive One TTL Load Over FullTemperature Range• Supply Voltage Range = 3.0 Vdc to 18 Vdc• Two Disable Controls for Added Versatility• Pin for Pin Replacement for MM80C97 and 340097MAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 2.)Symbol Parameter Value UnitV DD DC Supply Voltage Range –0.5 to +18.0 VV in , V out Input or Output Voltage Range(DC or Transient)–0.5 to V DD + 0.5 VI inI outP DInput Current(DC or Transient) per PinOutput Current(DC or Transient) per PinPower Dissipation,per Package (Note 3.)±10 mA±25 mA500 mWT A Ambient Temperature Range –55 to +125 °CT stg Storage Temperature Range –65 to +150 °CT LLead Temperature(8–Second Soldering)260 °C2. Maximum Ratings are those values beyond which damage to the devicemay occur.3. Temperature Derating:Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 CThis device contains protection circuitry to guard against damage due to highstatic voltages or electric fields. However, precautions must be taken to avoidapplications of any voltage higher than maximum rated voltages to thishigh–impedance circuit. For proper operation, V in and V out should be constrainedto the range V SS (V in or V out ) V DD .Unused inputs must always be tied to an appropriate logic voltage level (e.g.,either V SS or V DD ). Unused outputs must be left open.http://onsemi.comPDIP–16P SUFFIXCASE 648SOIC–16D SUFFIXCASE 751BSOEIAJ–16F SUFFIXCASE 966A = Assembly LocationWL or L = Wafer LotYY or Y = YearWW or W = Work WeekORDERING INFORMATIONMARKINGDIAGRAMSDevice Package ShippingMC14503BCP PDIP–16 2000/BoxMC14503BD SOIC–16 48/RailMC14503BDR2 SOIC–16 2500/Tape & Reel1. For ordering information on the EIAJ version ofthe SOIC packages, please contact your localON Semiconductor representative.161161161MC14503BCPAWLYYWW14503BAWLYWWMC14503BAWLYWWMC14503BF SOEIAJ–16 See Note 1.MC14503BFEL SOEIAJ–16 See Note 1.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 3236 Publication Order Number:MC14503B/D

MC14503BPIN ASSIGNMENTDIS A116V DDIN 1215DIS BOUT 1314IN 6IN 2413OUT 6OUT 2512IN 5IN 3611OUT 5OUT 3710IN 4V SS89OUT 4TRUTH TABLELOGIC DIAGRAMAppropriateDisableIn n Input Out n0 0 01 0 1X 1 HighImpedanceX = Don’t CareDISABLE BIN 5IN 6IN 1IN 215121424111335OUT 5OUT 6OUT 1OUT 2IN 367OUT 3IN 4109OUT 4DISABLE A1V DD = PIN 16V SS = PIN 8CIRCUIT DIAGRAMONE OF TWO/FOUR BUFFERSV DD*IN nOUT n* DISABLE* INPUTTO OTHER BUFFERSV SS*Diode protection on all inputs (not shown)http://onsemi.com237

MC14503BELECTRICAL CHARACTERISTICS (Voltages Referenced to V SS )ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΖ 55 C 25 C 125 C V DDÎÎÎÎÎÎÎÎÎÎCharacteristic ÎÎÎÎÎÎÎMinÎÎÎMaxÎÎÎÎ MinÎÎÎÎÎTyp (4.) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎMaxMaxÎÎÎUnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput VoltageV in = 0“0” Level“1” LevelÎÎÎ ÎÎÎSymbol VdcV OL 5.0 —10 —15 —ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎV in = V DDInput Voltage(V O = 3.6 or 1.4 Vdc)(V O = 7.2 or 2.8 Vdc)(V O = 11.5 or 3.5 Vdc)“0” LevelV OHV IL5.010154.959.9514.950.050.050.05———0000.050.050.05ÎÎÎMin— 0.05 Vdc— 0.05— 0.05ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5.01015——————4.959.9514.955.01015———4.959.9514.95ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V O = 1.4 or 3.6 Vdc)(V O = 2.8 or 7.2 Vdc)(V O = 3.5 or 11.5 Vdc)“1” LevelV IH5.010153.57.011ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ1.53.04.0——————3.57.0112.254.506.752.755.508.251.53.04.0——————3.57.011———1.53.04.0———VdcVdcVdcOutput Drive Current(V OH = 2.5 Vdc) Source(V OH = 2.5 Vdc)(V OH = 4.6 Vdc)(V OH = 9.5 Vdc)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V OH = 13.5 Vdc)(V OL = 0.4 Vdc) Sink(V OL = 0.4 Vdc)(V OL = 0.5 Vdc)I OHI OL4.55.05.010154.55.010– 4.3– 5.8– 1.2– 3.1– 8.2ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΗ————– 3.6– 4.8– 1.02– 2.6– 6.8– 5.0– 6.1– 1.4– 3.7– 14.1—————– 2.5– 3.0– 0.7– 1.8ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V OL = 1.5 Vdc)152.22.66.519.2————1.82.15.516.12.12.36.225————– 4.81.21.33.811.2—————————mAdcmAdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput Current ÎÎÎÎ I in 15 ÎÎÎ — ÎÎÎ ± 0.1ÎÎÎÎ — ÎÎΗ ÎÎÎ ± 1.0ÎÎÎ µAdcÎÎÎÎÎΗ ÎÎΗ ÎÎΗ ÎÎΗ ÎÎΗ pFInput Capacitance(V in = 0)C in± 0.1 ÎÎα0.00001ÎÎÎÎÎÎÎ7.5ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎQuiescent Current(Per Package)I Q5.01015———ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTotal Supply Current (5.) (6.)(Dynamic plus Quiescent,Per Package)(C L = 50 pF on all outputs)(All outputs switching,50% Duty Cycle)I T5.01015ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎThree–State Output Leakage ÎÎÎÎÎÎ15 — ± 0.1ÎÎÎÎ — — ± 3.0ÎÎÎ µAdcCurrentI TL1.02.04.0———0.0020.0040.0061.02.04.0I T = (2.5 µA/kHz) f + I DDI T = (6.0 µA/kHz) f + I DDI T = (10 µA/kHz) f + I DDÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΗ——0.0001ÎÎÎα ± ÎÎÎ0.14. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.5. The formulas given are for the typical characteristics only at 25 C.6. To calculate total supply current at loads other than 50 pF:I T (C L ) = I T (50 pF) + (C L – 50) Vfkwhere: I T is in µA (per package), C L in pF, V = (V DD – V SS ) in volts, f in kHz is input frequency, and k = 0.006.3060120µAdcµAdcÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΗÎÎÎÎ 5.0ÎÎÎÎhttp://onsemi.com238

MC14503BSWITCHING CHARACTERISTICS (7.) (C L = 50 pF, T A = 25 C)CharacteristicSymbolÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTyp (8.) Max ÎÎÎÎOutput Rise Timet TLH = (0.5 ns/pF) C L + 20 nst TLH = (0.3 ns/pF) C L + 8.0 nsV DDV CCAll TypesÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎt TLH = (0.2 ns/pF) C L + 8.0 nsOutput Fall Timet THL = (0.5 ns/pF) C L + 20 nst THL = (0.3 ns/pF) C L + 8.0 nsÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎt THL = (0.2 ns/pF) C L + 8.0 nsÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTurn–Off Delay Time, all Outputst PLH = (0.3 ns/pF) C L + 60 nst PLH = (0.15 ns/pF) C L + 27 nst PLH = (0.1 ns/pF) C L + 20 nsÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTurn–On Delay Time, all Outputst PHL = (0.3 ns/pF) C L + 60 nst PHL = (0.15 ns/pF) C L + 27 nsÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎt PHL = (0.1 ns/pF) C L + 20 ns3–State Propagation Delay TimeOutput “1” to High ImpedanceÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput “0” to High ImpedanceÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎHigh Impedance to “1” LevelÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎHigh Impedance to “0” LevelÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ7. The formulas given are for the typical characteristics only at 25 C.8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎt TLHt THLt PLHt PHLt PHZt PLZt PZHt PZL5.010155.010155.010155.010155.010155.010155.010155.010154523184523187535257535257540358040356525201003525904535904535150705015070501508070160807013050402007050UnitnsnsnsnsnsnsnsnsÎÎÎÎDISABLEINPUTPULSEGENERATORINPUTV DD16V SS C LOUTPUT90%20 ns 20 nsINPUTt PLHV90%DD50%10%V SSt PHLOUTPUT50%V OH10%V OLt PLHt TLHt THLt PHLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎFigure 1. Switching Time Test Circuit and Waveforms(t TLH , t THL , t PHL , and t PLH )http://onsemi.com239

MC14503BPULSEGENERATORDISABLE INPUTPULSEGENERATORDISABLE INPUTV DDt PLZ , t PZL CIRCUITt PHZ , t PZH CIRCUIT16161 kINPUTOUTPUTINPUTOUTPUT8V DD1kV SSC L8V SSC L20 ns 20 nsV90%DD50%10%DISABLE INPUTV SSt PLZt PZLV90% OHOUTPUT FOR t 10%PZH , t PZL CIRCUIT≈ V OL + 0.05 Vt PHZt PZHOUTPUT FOR t PHZ , t PLZ CIRCUIT90%≈ V OH – 0.15 V10%V OLFigure 2. 3–State AC Test Circuit and Waveforms(t PLZ , t PHZ , t PZH , t PZL )http://onsemi.com240

The MC14504B is a hex non–inverting level shifter using CMOStechnology. The level shifter will shift a TTL signal to CMOS logiclevels for any CMOS supply voltage between 5 and 15 volts. A controlinput also allows interface from CMOS to CMOS at one logic level toanother logic level: Either up or down level translating isaccomplished by selection of power supply levels V DD and V CC . TheV CC level sets the input signal levels while V DD selects the outputvoltage levels.• UP Translates from a Low to a High Voltage or DOWN Translatesfrom a High to a Low Voltage• Input Threshold Can Be Shifted for TTL Compatibility• No Sequencing Required on Power Supplies or Inputs for Power Upor Power Down• 3 to 18 Vdc Operation for V DD and V CC• Diode Protected Inputs to V SS• Capable of Driving Two Low–Power TTL Loads or One Low–PowerSchottky TTL Load Over the Rated Temperature RangeMAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 2.)Symbol Parameter Value UnitV CC DC Supply Voltage Range –0.5 to +18.0 VV DD DC Supply Voltage Range –0.5 to +18.0 VV in Input Voltage Range(DC or Transient)–0.5 to +18.0 VV outI in , I outP DOutput Voltage Range(DC or Transient)Input or Output Current(DC or Transient) per PinPower Dissipation,per Package (Note 3.)–0.5 to V DD + 0.5 V±10 mA500 mWT A Ambient Temperature Range –55 to +125 °CT stg Storage Temperature Range –65 to +150 °CT LLead Temperature(8–Second Soldering)260 °C2. Maximum Ratings are those values beyond which damage to the devicemay occur.3. Temperature Derating:Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 CThis device contains protection circuitry to guard against damage due to highstatic voltages or electric fields. However, precautions must be taken to avoidapplications of any voltage higher than maximum rated voltages to thishigh–impedance circuit. For proper operation, V in and V out should be constrainedto the range V SS (V in or V out ) V DD .Unused inputs must always be tied to an appropriate logic voltage level (e.g.,either V SS or V DD ). Unused outputs must be left open.http://onsemi.comPDIP–16P SUFFIXCASE 648SOIC–16D SUFFIXCASE 751BTSSOP–16DT SUFFIXCASE 948FSOEIAJ–16F SUFFIXCASE 966A = Assembly LocationWL or L = Wafer LotYY or Y = YearWW or W = Work WeekORDERING INFORMATIONMARKINGDIAGRAMSDevice Package ShippingMC14504BCP PDIP–16 2000/BoxMC14504BD SOIC–16 48/RailMC14504BDR2 SOIC–16 2500/Tape & Reel1. For ordering information on the EIAJ version ofthe SOIC packages, please contact your localON Semiconductor representative.161161161MC14504BCPAWLYYWW14504BAWLYWW16MC14504BAWLYWWMC14504BDT TSSOP–16 96/RailMC14504BF SOEIAJ–16 See Note 1.MC14504BFEL SOEIAJ–16 See Note 1.114504BALYW© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 3241 Publication Order Number:MC14504B/D

MC14504BPIN ASSIGNMENTV CC116V DDA out215F outA in314F inB out413MODE512E outC out611B inLOGIC DIAGRAME inC in710D outV SS89D inMODEV DDINPUTV CCTTL/CMOSMODE SELECTLEVELSHIFTEROUTPUTInput Logic Output LogicMode Select LevelsLevels1 (V CC ) TTL CMOS0 (V SS ) CMOS CMOS1/6 of package shown.http://onsemi.com242

MC14504BELECTRICAL CHARACTERISTICS (Voltages Referenced to V SS )ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCC V – 55 C 25 C DD CharacteristicOutput Voltage “0” LevelV in = 0 VV CCV DD125 ÎÎÎCTyp (4.) Max ÎÎ UnitÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMaxÎÎÎÎÎÎÎÎMinÎÎÎÎÎÎÎÎMinÎÎÎÎÎÎÎÎÎÎÎÎÎÎMaxÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎV in = V CC“1” LevelSymbolÎÎÎ ÎÎÎ ÎÎVdc VdcV OL — 5.0 —— 10 —— 1 5 —V OH———5.01015ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput Voltage “0” Level(V OL = 1.0 Vdc) TTL–CMOS(V OL = 1.5 Vdc) TTL–CMOS(V OL = 1.0 Vdc) CMOS–CMOSÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V OL = 1.5 Vdc) CMOS–CMOS(V OL = 1.5 Vdc) CMOS–CMOSV IL5.05.05.05.0101015101515ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput Voltage “1” Level(V OH = 9.0 Vdc) TTL–CMOS(V OH = 13.5 Vdc) TTL–CMOS(V OH = 9.0 Vdc) CMOS–CMOS(V OH = 13.5 Vdc) CMOS–CMOS(V OH = 13.5 Vdc) CMOS–CMOSV IHÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5.05.05.05.0101015101515ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ4.959.9514.95—————2.02.03.63.67.10.050.050.05———0.80.81.51.53.0————————4.959.9514.95—————2.02.03.53.57.00005.010151.31.32.252.254.51.51.52.752.755.50.050.050.05———0.80.81.51.53.0————————4.959.9514.95—————2.02.03.53.57.00.050.050.05———0.80.81.41.52.9—————VdcVdcVdcVdcOutput Drive Current(V OH = 2.5 Vdc) Source(V OH = 4.6 Vdc)(V OH = 9.5 Vdc)(V OH = 13.5 Vdc)I OH————5.05.01015– 3.0–0.64– 1.6– 4.2ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(V OL = 0.4 Vdc) SinkÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ(V OL = 0.5 Vdc)(V OL = 1.5 Vdc)I OL———5.010150.641.64.2———————– 2.4–0.51– 1.3– 3.40.511.33.4– 4.2– 0.88– 2.25– 8.80.882.258.8———————– 1.7–0.36– 0.9– 2.40.360.92.4———————mAdcmAdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput CurrentÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎI ÎÎÎin — ± — ±0.00001 ± 0.1 ± µAdcÎÎÎÎÎÎÎÎΗÎÎÎÎÎÎ 1.0ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput Capacitance (V ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎ ÎÎÎin = 0)C in15ÎÎΗ — ÎÎÎ5.0 7.5 pFÎÎΗÎÎÎÎÎ 0.1ÎÎΗÎÎÎÎÎÎΗÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎQuiescent CurrentÎÎÎÎI ÎÎÎÎÎÎÎÎÎÎÎÎÎÎDD or — 5.0—ÎÎÎ ÎÎÎΗÎÎÎ0.05ÎΗ 0.0005ÎÎÎ0.05ÎÎΗ 1.5 µAdc(Per —ÎÎÎ —ÎÎÎPackage)I CC — 10 — 0.10 — 0.0010 0.10 — 3.0CMOS–CMOS Mode— 15 — 0.20 — 0.0015 0.20 — 6.0Quiescent Current(Per Package)TTL–CMOS ModeI DD5.05.05.05.01015ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎQuiescent Current(Per Package)TTL–CMOS ModeI CC5.05.05.05.01015ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎΗ—————0.51.02.05.05.05.0——————0.00050.00100.00154. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.2.52.52.50.51.02.05.05.05.0——————3.87.5156.06.06.0µAdcmAdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎhttp://onsemi.com243

SWITCHING CHARACTERISTICS (C L = 50 pF, T A = 25 C)MC14504BÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎV CC V DDÎÎÎÎÎÎÎÎCharacteristicVdc VdcMin Typ (5.)UnitÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎPropagation Delay, High to LowÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPropagation Delay, Low to HighÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol Shifting ModetÎÎÎPHL TTL – CMOS 5.0ÎÎÎÎÎÎV DD > ÎÎÎV CC 5.0CMOS – CMOSÎÎÎ5.0ÎÎÎÎÎÎV DD > V CCÎÎÎÎÎÎ5.010ÎÎÎCMOS – CMOSÎÎÎ10ÎÎÎÎÎÎÎÎÎÎÎÎV CC > V DD 1515ÎÎÎÎÎÎÎÎÎt PLH TTLÎÎΖ CMOS 5.0V ÎÎÎÎÎÎDD > V CC 5.0 ÎÎÎCMOS – CMOS 5.0V DD > V CC 5.0101015101515—————Limits14014012012070ÎÎÎMax280 ns280240240140ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ5.05.0101015101515————————185185175170160170170100370370350340320340340200ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCMOS – CMOSV CC > V DDÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Rise and Fall Time ÎÎÎÎÎt TLH , t THL ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎALLnsÎÎÎÎÎÎ5. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ101515———5.05.0105.01015——————275275145100504055055029020010080nsÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎhttp://onsemi.com244

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉMC14504B77VSp, INPUT SWITCHPOINT VOLTAGE (Vdc)654321V CC = 10 VV CC = 5 VVSp, INPUT SWITCHPOINT VOLTAGE (Vdc)654321V CC = 5 V00510 15 20V DD , SUPPLY VOLTAGE (Vdc)Figure 1. Input Switchpoint CMOS to CMOS Mode2000510 15 20V DD , SUPPLY VOLTAGE (Vdc)Figure 2. Input Switchpoint TTL to CMOS Mode20VDD, SUPPLY VOLTAGE (Vdc)15105ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉVDD, SUPPLY VOLTAGE (Vdc)15105ÉÉÉÉÉÉÉÉÉÉÉÉ00510 15 20V CC , SUPPLY VOLTAGE (Vdc)Figure 3. Operating Boundary CMOS to CMOS Mode00510 15 20V CC , SUPPLY VOLTAGE (Vdc)Figure 4. Operating Boundary TTL to CMOS ModeÉÉÉÉÉÉÉÉÉhttp://onsemi.com245

The MC14511B BCD–to–seven segment latch/decoder/driver isconstructed with complementary MOS (CMOS) enhancement modedevices and NPN bipolar output drivers in a single monolithic structure.The circuit provides the functions of a 4–bit storage latch, an 8421BCD–to–seven segment decoder, and an output drive capability. Lamptest (LT), blanking (BI), and latch enable (LE) inputs are used to test thedisplay, to turn–off or pulse modulate the brightness of the display, andto store a BCD code, respectively. It can be used with seven–segmentlight–emitting diodes (LED), incandescent, fluorescent, gas discharge,or liquid crystal readouts either directly or indirectly.Applications include instrument (e.g., counter, DVM, etc.) displaydriver, computer/calculator display driver, cockpit display driver, andvarious clock, watch, and timer uses.• Low Logic Circuit Power Dissipation• High–Current Sourcing Outputs (Up to 25 mA)• Latch Storage of Code• Blanking Input• Lamp Test Provision• Readout Blanking on all Illegal Input Combinations• Lamp Intensity Modulation Capability• Time Share (Multiplexing) Facility• Supply Voltage Range = 3.0 V to 18 V• Capable of Driving Two Low–power TTL Loads, One Low–powerSchottky TTL Load or Two HTL Loads Over the Rated TemperatureRange• Chip Complexity: 216 FETs or 54 Equivalent Gates• Triple Diode Protection on all InputsMAXIMUM RATINGS (Voltages Referenced to V SS ) (2.)Symbol Parameter Value UnitV DD DC Supply Voltage Range –0.5 to +18.0 VV in Input Voltage Range, All Inputs –0.5 to V DD + 0.5 VI DC Current Drain per Input Pin 10 mAP DPower Dissipation,500 mWper Package (3.)T A Operating Temperature Range –55 to +125 °CT stg Storage Temperature Range –65 to +150 °CI OHmaxP OHmaxMaximum Output Drive Current(Source) per Output25 mAMaximum Continuous Output50 mAPower (Source) per Output (4.)2. Maximum Ratings are those values beyond which damage to the devicemay occur.3. Temperature Derating:Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C4. P OHmax = I OH (V DD – V OH )http://onsemi.comPDIP–16P SUFFIXCASE 648SOIC–16D SUFFIXCASE 751BSOIC–16DW SUFFIXCASE 751GSOEIAJ–16F SUFFIXCASE 966A = Assembly LocationWL or L = Wafer LotYY or Y = YearWW or W = Work WeekORDERING INFORMATIONMARKINGDIAGRAMS16Device Package ShippingMC14511BCP PDIP–16 2000/BoxMC14511BD SOIC–16 48/RailMC14511BDW SOIC–16 47/Rail1. For ordering information on the EIAJ version ofthe SOIC packages, please contact your localON Semiconductor representative.1MC14511BCPAWLYYWWMC14511BDWR2 SOIC–16 1000/Tape & Reel16116116114511BAWLYWW14511BAWLYYWWMC14511BAWLYWWMC14511BF SOEIAJ–16 See Note 1.MC14511BFEL SOEIAJ–16 See Note 1.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 3246 Publication Order Number:MC14511B/D

MC14511BThis device contains protection circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is advisedthat normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high–impedance circuit. Adestructive high current mode may occur if V in and V out are not constrained to the range V SS (V in or V out ) V DD .Due to the sourcing capability of this circuit, damage can occur to the device if V DD is applied, and the outputs are shorted to V SS and are at alogical 1 (See Maximum Ratings).Unused inputs must always be tied to an appropriate logic voltage level (e.g., either V SS or V DD ).PIN ASSIGNMENTB116V DDC215fLTBILED345614131211gabcefdgabcV SSA78109deDISPLAY0 1 2 3 4 5 6 7 8 9TRUTH TABLEInputsOutputsLE BI LT D C B A a b c d e f g DisplayX X 0 X X X X 1 1 1 1 1 1 1 8X 0 1 X X X X 0 0 0 0 0 0 0 Blank0 1 1 0 0 0 0 1 1 1 1 1 1 0 00 1 1 0 0 0 1 0 1 1 0 0 0 0 10 1 1 0 0 1 1 1 1 1 1 0 0 1 20 1 1 0 0 1 1 1 1 1 1 0 0 1 30 1 1 0 1 0 0 0 1 1 0 0 1 1 40 1 1 0 1 0 1 1 0 1 1 0 1 1 50 1 1 0 1 1 0 0 0 1 1 1 1 1 60 1 1 0 1 1 1 1 1 1 0 0 0 0 70 1 1 1 0 0 0 1 1 1 1 1 1 1 80 1 1 1 0 0 1 1 1 1 0 0 1 1 90 1 1 1 0 1 0 0 0 0 0 0 0 0 Blank0 1 1 1 0 1 1 0 0 0 0 0 0 0 Blank0 1 1 1 1 0 0 0 0 0 0 0 0 0 Blank0 1 1 1 1 0 1 0 0 0 0 0 0 0 Blank0 1 1 1 1 1 0 0 0 0 0 0 0 0 Blank0 1 1 1 1 1 1 0 0 0 0 0 0 0 Blank1 1 1 X X X X * *X = Don’t Care* Depends upon the BCD code previously applied when LE = 0http://onsemi.com247

MC14511BELECTRICAL CHARACTERISTICS (Voltages Referenced to V SS )– 55 C 25 C 125 CV DDVdc Min Max Min Typ (5.) Max Min Max UnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCharacteristicOutput Voltage “0” LevelV in = V DD or 0SymbolV OL 5.01015V 5.0“1” LevelV in = 0 or V DDOH1015Input Voltage # “0” Level(V O = 3.8 or 0.5 Vdc)(V O = 8.8 or 1.0 Vdc)(V O = 13.8 or 1.5 Vdc)(V O = 0.5 or 3.8 Vdc)(V O = 1.0 or 8.8 Vdc)(V O = 1.5 or 13.8 Vdc)“1” LevelOutput Drive Voltage(I OH = 0 mA) Source(I OH = 5.0 mA)(I OH = 10 mA)(I OH = 15 mA)(I OH = 20 mA)(I OH = 25 mA)(I OH = 0 mA)(I OH = 5.0 mA)(I OH = 10 mA)(I OH = 15 mA)(I OH = 20 mA)(I OH = 25 mA)(I OH = 0 mA)(I OH = 5.0 mA)(I OH = 10 mA)(I OH = 15 mA)(I OH = 20 mA)(I OH = 25 mA)Output Drive Current(V OL = 0.4 V) Sink(V OL = 0.5 V)(V OL = 1.5 V)V IL5.01015V IH5.01015———4.19.114.1———3.57.011OH5.0 4.1—3.9—3.4—I OL5.0101510 9.1—9.0—8.6—15 14.1—14—13.6—0.641.64.20.050.050.05———1.53.04.0————————————————————————4.19.114.1———3.57.0114.1—3.9—3.4—9.1—9.0—8.6—14.1—14—13.6—0004.579.5814.592.254.506.752.755.508.254.574.244.123.943.703.549.589.269.179.048.908.7014.5914.2714.1814.0713.9513.70Input Current I in 15 — ± 0.1 — ±0.00001 ± 0.1 — ± 1.0 µAdcInput Capacitance C in — — — — 5.0 7.5 — — pFQuiescent Current(Per Package) V in = 0 or V DD ,I out = 0 µATotal Supply Current (6.) (7.)(Dynamic plus Quiescent,Per Package)(C L = 50 pF on all outputs, allbuffers switching)I DD 5.01015I T 5.01015———0.511.33.45. Noise immunity specified for worst–case input combination.Noise Margin for both “1” and “0” level =1.0 Vdc min @ V DD = 5.0 Vdc2.0 Vdc min @ V DD = 10 Vdc2.5 Vdc min @ V DD = 15 Vdc6. The formulas given are for the typical characteristics only at 25 C.7. To calculate total supply current at loads other than 50 pF:I T (C L ) = I T (50 pF) + 3.5 x 10 –3 (C L – 50) V DD fwhere: I T is in µA (per package), C L in pF, V DD in Vdc, and f in kHz is input frequency.———5.01020———0.882.258.80.0050.0100.0150.050.050.05———1.53.04.0————————————————————————5.01020I T = (1.9 µA/kHz) f + I DDI T = (3.8 µA/kHz) f + I DDI T = (5.7 µA/kHz) f + I DD———4.19.114.1———3.57.0114.1—3.5—3.0—9.1—8.6—8.2—14.1—13.6—13.2—0.360.92.4———0.050.050.05———1.53.04.0————————————————————————150300600VdcVdcVdcVdcVdcVdcVdcmAdcµAdcµAdchttp://onsemi.com248

MC14511BSWITCHING CHARACTERISTICS (8.) (C L = 50 pF, T A = 25 C)CharacteristicÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Rise Timet TLH = (0.40 ns/pF) C L + 20 nst TLH = (0.25 ns/pF) C L + 17.5 nst TLH = (0.20 ns/pF) C L + 15 nsOutput Fall Timet THL = (1.5 ns/pF) C L + 50 nst THL = (0.75 ns/pF) C L + 37.5 nst THL = (0.55 ns/pF) C L + 37.5 nsData Propagation Delay Timet PLH = (0.40 ns/pF) C L + 620 nst PLH = (0.25 ns/pF) C L + 237.5 nst PLH = (0.20 ns/pF) C L + 165 nsSymbolt TLH5.01015t THL5.01015t PLH5.01015V DDVdc Min Typ Max Unit—————————40302512575656402501758060502501501301280500350nsnsnst PHL = (1.3 ns/pF) C L + 655 nst PHL = (0.60 ns/pF) C L + 260 nst PHL = (0.35 ns/pF) C L + 182.5 nst PHL 5.01015———7202902001440580400Blank Propagation Delay Timet PLH = (0.30 ns/pF) C L + 585 nst PLH = (0.25 ns/pF) C L + 187.5 nst PLH = (0.15 ns/pF) C L + 142.5 nst PLH5.0I015———600200150750300220nst PHL = (0.85 ns/pF) C L + 442.5 nst PHL = (0.45 ns/pF) C L + 177.5 nst PHL = (0.35 ns/pF) C L + 142.5 nst PHL 5.01015———485200160970400320Lamp Test Propagation Delay Timet PLH = (0.45 ns/pF) C L + 290.5 nst PLH = (0.25 ns/pF) C L + 112.5 nst PLH = (0.20 ns/pF) C L + 80 nst PLH5.01015———31312590625250180nst PHL = (1.3 ns/pF) C L + 248 nst PHL = (0.45 ns/pF) C L + 102.5 nst PHL = (0.35 ns/pF) C L + 72.5 nst PHL 5.01015———31312590625250180Setup Time t su 5.010151004030——————nsHold Time t h 5.01015604030——————nsLatch Enable Pulse Width t WL 5.0101552022013026011065———ns8. The formulas given are for the typical characteristics only.http://onsemi.com249

MC14511BInput LE low, and Inputs D, BI and LT high.f in respect to a system clock.All outputs connected to respective C L loads.A, B, AND CANY OUTPUT20 ns 20 ns90%50%12f50%10%50% DUTY CYCLEV DDV SSV OHV OLFigure 1. Dynamic Power Dissipation Signal Waveforms20 ns 20 ns90%V DDINPUT C50%10%V SSt PLH t PHL90%OUTPUT g50%10%V OHV OLt TLHt THL(a) Inputs D and LE low, and Inputs A, B, BI and LT high.20 nsLE10%90%50%t hV DDV SSt suV DDINPUT C50%V SSOUTPUT gV OH(b) Input D low, Inputs A, B, BI and LT high.V OLLE20 ns90%50%10%20 nsV DDV SSt WL(c) Data DCBA strobed into latches.Figure 2. Dynamic Signal Waveformshttp://onsemi.com250

MC14511BCONNECTIONS TO VARIOUS DISPLAY READOUTSLIGHT EMITTING DIODE (LED) READOUTV DDV DDCOMMONANODE LEDCOMMONCATHODE LED≈ 1.7 VV SSV SS≈ 1.7 VINCANDESCENT READOUTFLUORESCENT READOUTV DDV DDV DD**DIRECT(LOW BRIGHTNESS)V SSFILAMENTSUPPLYV SSV SS OR APPROPRIATEVOLTAGE BELOW V SS .(CAUTION: Maximum working voltage = 18.0 V)GAS DISCHARGE READOUTLIQUID CRYSTAL (LCD) READOUTEXCITATIONAPPROPRIATE(SQUARE WAVE,V DDVOLTAGEV DD V SS TO V DD )1/4 OF MC14070BV SS V SS** A filament pre–warm resistor is recommended to reduce filamentthermal shock and increase the effective cold resistance of thefilament.Direct dc drive of LCD’s not recommended for life ofLCD readouts.http://onsemi.com251

MC14511BLOGIC DIAGRAMBI 413 aA712 b11 cB110 d9eC215 f14 gLT 3D6LE 5V DD = PIN 16V SS = PIN 8http://onsemi.com252

The MC14512B is an 8–channel data selector constructed withMOS P–channel and N–channel enhancement mode devices in asingle monolithic structure. This data selector finds primaryapplication in signal multiplexing functions. It may also be used fordata routing, digital signal switching, signal gating, and numbersequence generation.• Diode Protection on All Inputs• Single Supply Operation• 3–State Output (Logic “1”, Logic “0”, High Impedance)• Supply Voltage Range = 3.0 Vdc to 18 Vdc• Capable of Driving Two Low–power TTL Loads or One Low–powerSchottky TTL Load Over the Rated Temperature Rangehttp://onsemi.comPDIP–16P SUFFIXCASE 648MARKINGDIAGRAMS161MC14512BCPAWLYYWWMAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 2.)Symbol Parameter Value UnitV DD DC Supply Voltage Range –0.5 to +18.0 VV in , V out Input or Output Voltage Range(DC or Transient)–0.5 to V DD + 0.5 VI in , I outP DInput or Output Current(DC or Transient) per PinPower Dissipation,per Package (Note 3.)±10 mA500 mWT A Ambient Temperature Range –55 to +125 °CT stg Storage Temperature Range –65 to +150 °CT LLead Temperature(8–Second Soldering)260 °C2. Maximum Ratings are those values beyond which damage to the devicemay occur.3. Temperature Derating:Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 CThis device contains protection circuitry to guard against damage due to highstatic voltages or electric fields. However, precautions must be taken to avoidapplications of any voltage higher than maximum rated voltages to thishigh–impedance circuit. For proper operation, V in and V out should be constrainedto the range V SS (V in or V out ) V DD .Unused inputs must always be tied to an appropriate logic voltage level (e.g.,either V SS or V DD ). Unused outputs must be left open.SOIC–16D SUFFIXCASE 751BSOEIAJ–16F SUFFIXCASE 966A = Assembly LocationWL or L = Wafer LotYY or Y = YearWW or W = Work WeekORDERING INFORMATIONDevice Package ShippingMC14512BCP PDIP–16 2000/BoxMC14512BD SOIC–16 48/RailMC14512BDR2 SOIC–16 2500/Tape & Reel16116114512BAWLYWWMC14512BAWLYWWMC14512BF SOEIAJ–16 See Note 1.MC14512BFL1 SOEIAJ–16 See Note 1.1. For ordering information on the EIAJ version ofthe SOIC packages, please contact your localON Semiconductor representative.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 3253 Publication Order Number:MC14512B/D

MC14512BTRUTH TABLEC B A Inhibit Disable Z0 0 0 0 0 X00 0 1 0 0 X10 1 0 0 0 X20 1 1 0 0 X31 0 0 0 0 X41 0 1 0 0 X51 1 0 0 0 X61 1 1 0 0 X7X X X 1 0 0X X X X 1 HighImpedanceX = Don’t CarePIN ASSIGNMENTX0116V DDX1215DISX2314ZX3413CX4512BX5611AX6710INHV SS89X7http://onsemi.com254

MC14512BELECTRICAL CHARACTERISTICS (Voltages Referenced to V SS )– 55 C 25 C 125 CV DDVdc Min Max Min Typ (4.) Max Min Max UnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCharacteristicOutput VoltageV in = V DD or 0“0” LevelSymbolV OL 5.01015V 5.0“1” LevelV in = 0 or V DDOH1015Input Voltage“0” Level(V O = 4.5 or 0.5 Vdc)(V O = 9.0 or 1.0 Vdc)(V O = 13.5 or 1.5 Vdc)V IL5.01015———4.959.9514.95———0.050.050.05———1.53.04.0———4.959.9514.95———0005.010152.254.506.750.050.050.05———1.53.04.0———4.959.9514.95———0.050.050.05———1.53.04.0VdcVdcVdc(V O = 0.5 or 4.5 Vdc)(V O = 1.0 or 9.0 Vdc)(V O = 1.5 or 13.5 Vdc)“1” LevelV IH5.010153.57.011———3.57.0112.755.508.25———3.57.011———VdcOutput Drive Current(V OH = 2.5 Vdc) Source(V OH = 4.6 Vdc)(V OH = 9.5 Vdc)(V OH = 13.5 Vdc)I OH5.05.01015– 3.0– 0.64– 1.6– 4.2————– 2.4– 0.51– 1.3– 3.4– 4.2– 0.88– 2.25– 8.8————– 1.7– 0.36– 0.9– 2.4————mAdc(V OL = 0.4 Vdc) Sink(V OL = 0.5 Vdc)(V OL = 1.5 Vdc)I OL 5.010150.641.64.2Input Current I in 15 — ± 0.1 — ±0.00001 ± 0.1 — ± 1.0 µAdcInput Capacitance(V in = 0)———0.511.33.40.882.258.8C in — — — — 5.0 7.5 — — pF———0.360.92.4———mAdcQuiescent Current(Per Package)I DD 5.01015———5.01020———0.0050.0100.0155.01020———150300600µAdcTotal Supply Current (5.) (6.)(Dynamic plus Quiescent,Per Package)(C L = 50 pF on all outputs, allbuffers switching)I T 5.01015I T = (0.8 µA/kHz) f + I DDI T = (1.6 µA/kHz) f + I DDI T = (2.4 µA/kHz) f + I DDµAdcThree–State Leakage Current I TL 15 — ± 0.1 — ± 0.0001 ± 0.1 — ± 3.0 µAdc4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.5. The formulas given are for the typical characteristics only at 25 C.6. To calculate total supply current at loads other than 50 pF:I T (C L ) = I T (50 pF) + (C L – 50) Vfkwhere: I T is in µA (per package), C L in pF, V = (V DD – V SS ) in volts, f in kHz is input frequency, and k = 0.001.http://onsemi.com255

MC14512BSWITCHING CHARACTERISTICS (7.) (C L = 50 pF, T A = 25 C, See Figure 1)All TypesCharacteristic Symbol V DD Typ (8.) Max UnitOutput Rise and Fall Timet TLH , t THL = (1.5 ns/pF) C L + 25 nst TLH , t THL = (0.75 ns/pF) C L + 12.5 nst TLH , t THL = (0.55 ns/pF) C L + 9.5 nst TLH ,t THL 5.01015100504020010080nsPropagation Delay Time (Figure 2)Inhibit, Control, or Data to ZPropagation Delay Time (Figure 2)Inhibit, Control, or Data to Z3–State Output Delay Times (Figure 3)“1” or “0” to High Z, andHigh Z to “1” or “0”t PLH5.01015t PHL5.01015t PHZ , t PLZ , 5.0t PZH , t PZL 10157. The formulas given are for the typical characteristics only at 25 C.8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.330125853301258560353065025017065025017015010075nsnsnsI DV DD50%V in50%DUTYCYCLEPULSEGENERATORDISABLEINHIBITABCX0X1X2X3X4X5X6X7ZC LV SSFigure 1. Power Dissipation Test Circuit and Waveformhttp://onsemi.com256

MC14512BV DD20 ns 20 nsPULSEGENERATORDISABLEINHIBITABCX0X1X2X3X4X5X6X7ZC LDATAZINHIBIT,A, B, OR Ct PLHt TLH90%50%10%90%10%50%TEST CONDITIONS:INHIBIT = V SSA, B, C = V SS20 ns 20 ns90%50%10%t PHLt THLV DDV SSV OHV OLV DDV SSV SSParameterInhibit to ZTest ConditionsA, B, C = V SS , X O = V DDZt PHL90%50%10%t PLHV OHV OLA, B, C to Z Inh = V SS , X O = V DDt THLt TLHFigure 2. AC Test Circuit and WaveformsV DDPULSEGENERATORV DDS3S4V SSDISABLEINHIBITABCX0X1X2X3X4X5X6X7ZC L1kV DDS1S2V SSDISABLEINPUTOUTPUTOUTPUT20 ns90%50%10%Switch Positions for 3–State TestTest S1 S2 S3 S420 nsV SSV DDtt PZLPLZV OH90%10%V≈ 2.5 V @ V DD = 5 V,OL10 V, AND 15 Vt PHZ t PZH≈ 2 V @ V DD = 5 VV90%OH ≈ 6 V @ V DD = 10 V10% ≈ 10 V @ VV DD = 15 VOLV SSt PHZ Open Closed Closed Opent PLZ Closed Open Open Closedt PZL Closed Open Open Closedt PZH Open Closed Closed OpenFigure 3. 3–State AC Test Circuit and Waveformhttp://onsemi.com257

MC14512B13C12B11A1X02X1LOGIC DIAGRAM15DISABLE10INHIBITSELECTEDDEVICEMC14512BI ODDATABUSV DDZX2X3X4X5345614MC14512BMC14512BI LLOADI TLI TLX67V SSX79IN1 1OUTINOUT2TRANSMISSIONGATE23–STATE MODE OF OPERATIONOutput terminals of several MC14512B 8–Bit DataSelectors can be connected to a single date bus as shown.One MC14512B is selected by the 3–state control, and theremaining devices are disabled into a high–impedance “off”state. The number of 8–bit data selectors, N, that may beconnected to a bus line is determined from the output drivecurrent, I OD , 3–state or disable output leakage current, I TL ,and the load current, I L , required to drive the bus line(including fanout to other device inputs), and can becalculated by:I OD – I LN = + 1I TLN must be calculated for both high and low logic state of thebus line.http://onsemi.com258

CMOS MSI(Low–Power Complementary MOS)The MC14513B BCD–to–seven segment latch/decoder/driver isconstructed with complementary MOS (CMOS) enhancement modedevices and NPN bipolar output drivers in a single monolithic structure.The circuit provides the functions of a 4–bit storage latch, an 8421BCD–to–seven segment decoder, and has output drive capability. Lamptest (LT), blanking (BI), and latch enable (LE) inputs are used to test thedisplay, to turn–off or pulse modulate the brightness of the display, andto store a BCD code, respectively. The Ripple Blanking Input (RBI) andRipple Blanking Output (RBO) can be used to suppress either leadingor trailing zeroes. It can be used with seven–segment light emittingdiodes (LED), incandescent, fluorescent, gas discharge, or liquid crystalreadouts either directly or indirectly.Applications include instrument (e.g., counter, DVM, etc.) displaydriver, computer/calculator display driver, cockpit display driver, andvarious clock, watch, and timer uses.• Low Logic Circuit Power Dissipation• High–current Sourcing Outputs (Up to 25 mA)• Latch Storage of Binary Input• Blanking Input• Lamp Test Provision• Readout Blanking on all Illegal Input Combinations• Lamp Intensity Modulation Capability• Time Share (Multiplexing) Capability• Adds Ripple Blanking In, Ripple Blanking Out to MC14511B• Supply Voltage Range = 3.0 V to 18 V• Capable of Driving Two Low–Power TTL Loads, One Low–powerSchottky TTL Load to Two HTL Loads Over the Rated TemperatureRange.MAXIMUM RATINGS (Voltages Referenced to V SS ) (1.)Symbol Parameter Value UnitV DD DC Supply Voltage Range –0.5 to +18.0 VV in Input Voltage Range, All Inputs –0.5 to V DD + 0.5 VI DC Current Drain per Input Pin 10 mAP DPower Dissipation,500 mWper Package (2.)PDIP–18P SUFFIXCASE 707http://onsemi.com18A = Assembly LocationWL or L = Wafer LotYY or Y = YearWW or W = Work WeekORDERING INFORMATIONDevice Package ShippingMC14513BCP PDIP–18 20/Rail1MARKINGDIAGRAMSMC14513BCPAWLYYWWThis device contains protection circuitry to protectthe inputs against damage due to high static voltagesor electric fields. However, it is advised that normalprecautions be taken to avoid application of any voltagehigher than maximum rated voltages to this high–impedance circuit. A destructive high current modemay occur if V in and V out are not constrained to therange V SS (V in or V out ) V DD .Due to the sourcing capability of this circuit, damagecan occur to the device if V DD is applied, and theoutputs are shorted to V SS and are at a logical 1 (SeeMaximum Ratings).Unused inputs must always be tied to an appropriatelogic voltage level (e.g., either V SS or V DD ).T A Operating Temperature Range –55 to +125 °CT stg Storage Temperature Range –65 to +150 °CI OHmaxP OHmaxMaximum Continuous OutputDrive Current (Source) per Output25 mAMaximum Continuous Output50 mWPower (Source) per Output (3.)1. Maximum Ratings are those values beyond whichdamage to the device may occur.2. Temperature Derating:Plastic “P and D/DW” Packages: – 7.0 mW/ CFrom 65 C To 125 C3. P OHmax = I OH (V DD – V OH )© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 3259 Publication Order Number:MC14513B/D

MC14513BPIN ASSIGNMENTB118V DDC217fLTBILED345616151413gabcefdgabcA712dRBIV SS891110eRBODISPLAY0 1 2 3 4 5 6 7 8 9TRUTH TABLEInputsOutputsRBI LE BI LT D C B A RBO a b c d e f g DisplayX X X 0 X X X X + 1 1 1 1 1 1 1 8X X 0 1 X X X X + 0 0 0 0 0 0 0 Blank1 0 1 1 0 0 0 0 1 0 0 0 0 0 0 0 Blank0 0 1 1 0 0 0 0 0 1 1 1 1 1 1 0 0X 0 1 1 0 0 0 1 0 0 1 1 0 0 0 0 1X 0 1 1 0 0 1 0 0 1 1 0 1 1 0 1 2X 0 1 1 0 0 1 1 0 1 1 1 1 0 0 1 3X 0 1 1 0 1 0 0 0 0 1 1 0 0 1 1 4X 0 1 1 0 1 0 1 0 1 0 1 1 0 1 1 5X 0 1 1 0 1 1 0 0 1 0 1 1 1 1 1 6X 0 1 1 0 1 1 1 0 1 1 1 0 0 0 0 7X 0 1 1 1 0 0 0 0 1 1 1 1 1 1 1 8X 0 1 1 1 0 0 1 0 1 1 1 1 0 1 1 9X 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0 BlankX 0 1 1 1 0 1 1 0 0 0 0 0 0 0 0 BlankX 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 BlankX 0 1 1 1 1 0 1 0 0 0 0 0 0 0 0 BlankX 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 BlankX 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 BlankX 1 1 1 X X X X † * *X = Don’t Care†RBO = RBI (D C B A), indicated by other rows of table*Depends upon the BCD code previously applied when LE = 0http://onsemi.com2

MC14513BELECTRICAL CHARACTERISTICS (Voltages Referenced to V SS )– 55 C 25 C 125 CV DDVdc Min Max Min Typ (4.) Max Min Max UnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCharacteristicOutput Voltage — Segment Outputs“0” LevelV in = V DD or 0SymbolV OL5.01015V 5.0“1” LevelV in = 0 or V DDOH1015Output Voltage — RBO Output“0” LevelV in = V DD or 0V OL5.01015V 5.0“1” LevelV in = 0 or V DDOH1015Input Voltage (4.) “0” Level(V O = 3.8 or 0.5 Vdc)(V O = 8.8 or 1.0 Vdc)(V O = 13.8 or 1.5 Vdc)V IL5.01015———4.19.114.1———4.959.9514.95———0.050.050.05———0.050.050.05———1.53.04.0———4.19.114.1———4.959.9514.95———0005.010150005.010152.254.506.750.050.050.05———0.050.050.05———1.53.04.0———4.19.114.1———4.959.9514.95———0.050.050.05———0.050.050.05———1.53.04.0VdcVdcVdcVdcVdc(V O = 0.5 or 3.8 Vdc) “1” Level(V O = 1.0 or 8.8 Vdc)(V O = 1.5 or 13.8 Vdc)V IH 5.010153.57.011———3.57.0112.755.508.25———3.57.011———VdcOutput Drive Voltage — Segments(I OH = 0 mA) Source(I OH = 5.0 mA)(I OH = 10 mA)(I OH = 15 mA)(I OH = 20 mA)(I OH = 25 mA)OH5.0 4.1—3.9—3.4———————4.1—3.9—3.4—4.574.244.123.943.703.54——————4.1—3.5—3.0———————Vdc(I OH = 0 mA)(I OH = 5.0 mA)(I OH = 10 mA)(I OH = 15 mA)(I OH = 20 mA)(I OH = 25 mA)10 9.1—9.0—8.6———————9.1—9.0—8.6—9.589.269.179.048.908.75——————9.1—8.6—8.2———————Vdc(I OH = 0 mA)(I OH = 5.0 mA)(I OH = 10 mA)(I OH = 15 mA)(I OH = 20 mA)(I OH = 25 mA)15 14.1—14—13.6———————14.1—14—13.6—14.5914.2714.1814.0713.9513.80——————14.1—13.6—13.2———————Vdc(continued)http://onsemi.com261

MC14513BELECTRICAL CHARACTERISTICS — continued (Voltages Referenced to V SS )– 55 C 25 C 125 CV DDVdc Min Max Min Typ (4.) Max Min Max UnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCharacteristicOutput Drive Current — RBO Output(V OH = 2.5 V) Source(V OH = 9.5 V)(V OH = 13.5 V)SymbolI OH5.01015– 0.40– 0.21– 0.81———– 0.32– 0.17– 0.66– 0.64– 0.34– 1.30———– 0.22– 0.12– 0.46———mAdc(V OL = 0.4 V) Sink(V OL = 0.5 V)(V OL = 1.5 V)I OL 5.010150.180.471.80———0.150.381.500.290.752.90———0.100.261.0———mAdcOutput Drive Current — Segments(V OL = 0.4 V) Sink(V OL = 0.5 V)(V OL = 1.5 V)I OL5.010150.641.64.2Input Current I in 15 — ± 0.1 — ±0.00001 ± 0.1 — ± 1.0 µAdcInput Capacitance C in — — — — 5.0 7.5 — — pFQuiescent Current(Per Package) V in = 0 or V DD ,I out = 0 µATotal Supply Current (5.) (6.)(Dynamic plus Quiescent,Per Package)(C L = 50 pF on all outputs, allbuffers switching)I DD 5.01015I T 5.010154. Noise immunity specified for worst–case input combination.Noise Margin for both “1” and “0” level =1.0 Vdc min @ V DD = 5.0 Vdc2.0 Vdc min @ V DD = 10 Vdc2.5 Vdc min @ V DD = 15 Vdc5. The formulas given are for the typical characteristics only at 25 C.6. To calculate total supply current at loads other than 50 pF:I T (C L ) = I T (50 pF) + 3.5 x 10 –3 (C L – 50) V DD fwhere: I T is in µA (per package), C L in pF, V DD in Vdc, and f in kHz is input frequency.——————5.010200.511.33.4———0.882.258.80.0050.0100.015———5.01020I T = (1.9 µA/kHz) f + I DDI T = (3.8 µA/kHz) f + I DDI T = (5.7 µA/kHz) f + I DD0.360.92.4——————150300600mAdcµAdcµAdcInput LE and RBI low, and Inputs D, BI and LT high.f in respect to a system clock.All outputs connected to respective C L loads.20 ns 20 ns90%A, B, AND C50%110%2fANY OUTPUT50% DUTY CYCLE50%V DDV SSV OHV OLFigure 1. Dynamic Power Dissipation Signal Waveformshttp://onsemi.com262

SWITCHING CHARACTERISTICS (7.) (C L = 50 pF, T A = 25 C)MC14513BV DDAll TypesVdc Min Typ Max UnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCharacteristicSymbolOutput Rise Time — Segment Outputs t TLH5.01015Output Rise Time — RBO Output t TLH5.01015Output Fall Time — Segment Outputs (7.)t THL = (1.5 ns/pF) C L + 50 nst THL = (0.75 ns/pF) C L + 37.5 nst THL = (0.55 ns/pF) C L + 37.5 nsOutput Fall Time — RBO Outputst THL = (3.25 ns/pF) C L + 107.5 nst THL = (1.35 ns/pF) C L + 67.5 nst THL = (0.95 ns/pF) C L + 62.5 nsPropagation Delay Time — A, B, C, D Inputs (7.)t PLH = (0.40 ns/pF) C L + 620 nst PLH = (0.25 ns/pF) C L + 237.5 nst PLH = (0.20 ns/pF) C L + 165 nst THL5.01015t THL5.01015t PLH5.01015———————————————40302548024019012575652701351106402501758060509604803802501501305402702201280500350nsnsnsnsnst PHL = (1.3 ns/pF) C L + 655 nst PHL = (0.60 ns/pF) C L + 260 nst PHL = (0.35 ns/pF) C L + 182.5 nst PHL 5.01015———7202902001440580400nsPropagation Delay Time — RBI and BI Inputs (7.)t PLH = (1.05 ns/pF) C L + 547.5 nst PLH = (0.45 ns/pF) C L + 177.5 nst PLH = (0.30 ns/pF) C L + 135 nst PLH5.01015———600200150750300220nst PHL = (0.85 ns/pF) C L + 442.5 nst PHL = (0.45 ns/pF) C L + 177.5 nst PHL = (0.35 ns/pF) C L + 142.5 nst PHL 5.01015———485200160970400320nsPropagation Delay Time — LT Input (7.)t PLH = (0.45 ns/pF) C L + 290.5 nst PLH = (0.25 ns/pF) C L + 112.5 nst PLH = (0.20 ns/pF) C L + 80 nst PLH5.01015———31312590625250180nst PHL = (1.3 ns/pF) C L + 248 nst PHL = (0.45 ns/pF) C L + 102.5 nst PHL = (0.35 ns/pF) C L + 72.5 nst PHL 5.01015———31312590625250180nsSetup Time t su 5.010151004030——————nsHold Time t h 5.01015604030——————nsLatch Enable Pulse Width t WL(LE) 5.0101552022013026011065———ns7. The formulas given are for the typical characteristics only.http://onsemi.com263

MC14513BCONNECTIONS TO VARIOUS DISPLAY READOUTSLIGHT EMITTING DIODE (LED) READOUTV DDV DDCOMMONCATHODE LEDCOMMONANODE LED≈ 1.7 V≈ 1.7 VV SSV SSINCANDESCENT READOUTFLUORESCENT READOUTV DDV DD* *V SSV DDDIRECT(LOW BRIGHTNESS)V SSFILAMENT(SUPPLY)V SS OR APPROPRIATEVOLTAGE BELOW V SS .GAS DISCHARGE READOUTV DDAPPROPRIATEVOLTAGELIQUID CRYSTAL (LC) READOUTV DDEXCITATION(SQUARE WAVE,V SS TO V DD )1/4 OF MC14070BV SS** A filament pre–warm resistor is recommended to reducefilament thermal shock and increase the effective coldresistance of the filament.V SSDirect dc drive of LC’s not recommended for life of LC readouts.http://onsemi.com265

MC14513BLOGIC DIAGRAMBI 415 aA714 b13 cB112 d11 eC2D6RBI 8LT 3010 RBO17 f16 gLE 5http://onsemi.com266

MC14513BTYPICAL APPLICATIONS FOR RIPPLE BLANKINGLEADING EDGE ZERO SUPPRESSIONDISPLAYSCONNECT TOV DD (1)a– – –– – ga – – – – – g a – – – – – g a – – – – – g a– – – – – g a – – – – – gRBI RBO RBI RBO RBI RBO RBI RBO RBI RBO RBI RBOD C B A 1 D C B A 1 D C B A 0 D C B A 0 D C B A 0 D C B A0INPUTCODEMC14513B0 0 0 0(0)MC14513B MC14513B MC14513B MC14513B MC14513B0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 1 1(0)(5)(0)(1)(3)TRAILING EDGE ZERO SUPPRESSIONDISPLAYS0a – – – – – g a – – – – – g a – – – – – g a – – – – – g a – – – – – g a – – – – – gCONNECT TORBO RBI RBO RBI RBO RBI RBO RBI RBO RBI RBO RBID C B A 0 D C B A 0 D C B A 0 D C B A 1 D C B A 1 D C B A V DD (1)MC14513B0 1 0 1(5)MC14513B MC14513B MC14513B MC14513B MC14513B0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0(0)(1)(3)(0)(0)INPUT CODEhttp://onsemi.com267

The MC14514B and MC14515B are two output options of a 4 to 16line decoder with latched inputs. The MC14514B (output active highoption) presents a logical “1” at the selected output, whereas theMC14515B (output active low option) presents a logical “0” at theselected output. The latches are R–S type flip–flops which hold thelast input data presented prior to the strobe transition from “1” to “0”.These high and low options of a 4–bit latch/4 to 16 line decoder areconstructed with N–channel and P–channel enhancement modedevices in a single monolithic structure. The latches are R–S typeflip–flops and data is admitted upon a signal incident at the strobeinput, decoded, and presented at the output.These complementary circuits find primary use in decodingapplications where low power dissipation and/or high noise immunityis desired.• Supply Voltage Range = 3.0 Vdc to 18 Vdc• Capable of Driving Two Low–power TTL Loads or One Low–powerSchottky TTL Load Over the Rated Temperature RangePDIP–24P SUFFIXCASE 709http://onsemi.com241MARKINGDIAGRAMSMC145XXBCPAWLYYWWMAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 1.)24Symbol Parameter Value UnitV DD DC Supply Voltage Range –0.5 to +18.0 VV in , V out Input or Output Voltage Range(DC or Transient)–0.5 to V DD + 0.5 VSOIC–24DW SUFFIXCASE 751E1145XXBAWLYYWWI in , I outP DInput or Output Current(DC or Transient) per PinPower Dissipation,per Package (Note 2.)±10 mA500 mWT A Ambient Temperature Range –55 to +125 °CT stg Storage Temperature Range –65 to +150 °CT LLead Temperature(8–Second Soldering)260 °C1. Maximum Ratings are those values beyond which damage to the devicemay occur.2. Temperature Derating:Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 CThis device contains protection circuitry to guard against damage due to highstatic voltages or electric fields. However, precautions must be taken to avoidapplications of any voltage higher than maximum rated voltages to thishigh–impedance circuit. For proper operation, V in and V out should be constrainedto the range V SS (V in or V out ) V DD .Unused inputs must always be tied to an appropriate logic voltage level (e.g.,either V SS or V DD ). Unused outputs must be left open.XX = Specific Device CodeA = Assembly LocationWL or L = Wafer LotYY or Y = YearWW or W = Work WeekORDERING INFORMATIONDevice Package ShippingMC14514BCP PDIP–24 15/RailMC14514BDW SOIC–24 30/RailMC14514BDWR2 SOIC–24 1000/Tape & ReelMC14515BCP PDIP–24 15/RailMC14515BDW SOIC–24 30/RailMC14515BDWR2 SOIC–24 1000/Tape & Reel© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 3268 Publication Order Number:MC14514B/D

MC14514B, MC14515BPIN ASSIGNMENTST124V DDD1223INHD2322D4S7421D3S6520S10S5619S11S4718S8S3817S9S1916S14S21015S15S01114S12V SS1213S13DECODE TRUTH TABLE (Strobe = 1)*Data InputsSelected OutputMC14514 = Logic “1”Inhibit D C B A MC14515 = Logic “0”0 0 0 0 0 S00 0 0 0 1 S10 0 0 1 0 S20 0 0 1 1 S30 0 1 0 0 S40 0 1 0 1 S50 0 1 1 0 S60 0 1 1 1 S70 1 0 0 0 S80 1 0 0 1 S90 1 0 1 0 S100 1 0 1 1 S110 1 1 0 0 S120 1 1 0 1 S130 1 1 1 0 S140 1 1 1 1 S151 X X X X All Outputs = 0, MC14514All Outputs = 1, MC14515X = Don’t Care*Strobe = 0, Data is latchedDATA 1DATA 2DATA 3DATA 4STROBEBLOCK DIAGRAM2321221V DD = PIN 24V SS = PIN 12TRANSPARENTLATCHABS0S1S2S3S4S5S6S7S8S911910876544 TO 16C18DECODER17D 20S101914S11S12S13S14S15131615A B C DA B C DA B C DA B C DA B C DA B C DA B C DA B C DA B C DA B C DA B C DA B C DA B C DA B C DA B C DA B C DINHIBIT23http://onsemi.com269

MC14514B, MC14515BELECTRICAL CHARACTERISTICS (Voltages Referenced to V SS )– 55 C 25 C 125 CV DDVdc Min Max Min Typ (3.) Max Min Max UnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCharacteristicOutput VoltageV in = V DD or 0“0” LevelSymbolV OL 5.01015V 5.0“1” LevelV in = 0 or V DDOH1015Input Voltage“0” Level(V O = 4.5 or 0.5 Vdc)(V O = 9.0 or 1.0 Vdc)(V O = 13.5 or 1.5 Vdc)V IL5.01015———4.959.9514.95———0.050.050.05———1.53.04.0———4.959.9514.95———0005.010152.254.506.750.050.050.05———1.53.04.0———4.959.9514.95———0.050.050.05———1.53.04.0VdcVdcVdc(V O = 0.5 or 4.5 Vdc)(V O = 1.0 or 9.0 Vdc)(V O = 1.5 or 13.5 Vdc)“1” LevelV IH5.010153.57.011———3.57.0112.755.508.25———3.57.011———VdcOutput Drive Current(V OH = 2.5 Vdc) Source(V OH = 4.6 Vdc)(V OH = 9.5 Vdc)(V OH = 13.5 Vdc)I OH5.05.01015– 1.2– 0.25– 0.62– 1.8————– 1.0– 0.2– 0.5– 1.5– 1.7– 0.36– 0.9– 3.5————– 0.7– 0.14– 0.35– 1.1————mAdc(V OL = 0.4 Vdc) Sink(V OL = 0.5 Vdc)(V OL = 1.5 Vdc)I OL 5.010150.641.64.2Input Current I in 15 — ± 0.1 — ±0.00001 ± 0.1 — ± 1.0 µAdcInput Capacitance(V in = 0)———0.511.33.40.882.258.8C in — — — — 5.0 7.5 — — pF———0.360.92.4———mAdcQuiescent Current(Per Package)Total Supply Current (4.) (5.)(Dynamic plus Quiescent,Per Package)(C L = 50 pF on all outputs, allbuffers switching)I DD 5.01015I TL 5.01015———5.01020———0.0050.0100.0155.01020I T = (1.35 µA/kHz) f + I DDI T = (2.70 µA/kHz) f + I DDI T = (4.05 µA/kHz) f + I DD3. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.4. The formulas given are for the typical characteristics only at 25 C.5. To calculate total supply current at loads other than 50 pF:I T (C L ) = I T (50 pF) + (C L – 50) Vfkwhere: I T is in µA (per package), C L in pF, V = (V DD – V SS ) in volts, f in kHz is input frequency, and k = 0.002.———150300600µAdcµAdchttp://onsemi.com270

SWITCHING CHARACTERISTICS (6.) (C L = 50 pF, T A = 25 C)MC14514B, MC14515BAll TypesÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Rise Timet TLH = (3.0 ns/pF) C L + 30 nst TLH = (1.5 ns/pF) C L + 15 nst TLH = (1.1 ns/pF) C L + 10 nsOutput Fall Timet THL = (1.5 ns/pF) C L + 25 nst THL = (0.75 ns/pF) C L + 12.5 nst THL = (0.55 ns/pF) C L + 9.5 nsPropagation Delay Time; Data, Strobe to St PLH , t PHL = (1.7 ns/pF) C L + 465 nst PLH , t PHL = (0.86 ns/pF) C L + 192 nst PLH , t PHL = (0.5 ns/pF) C L + 125 nsInhibit Propagation Delay Timest PLH , t PHL = (1.7 ns/pF) C L + 315 nst PLH , t PHL = (0.66 ns/pF) C L + 117 nst PLH , t PHL = (0.5 ns/pF) C L + 75 nsSetup TimeData to StrobeHold TimeStrobe to DataCharacteristic Symbol V DD Min Typ (7.) Max Unitt TLH5.01015t THL5.01015t PLH ,t PHL 5.01015t PLH ,t PHL 5.01015t su5.01015t h 5.01015Strobe Pulse Width t WH5.010156. The formulas given are for the typical characteristics only at 25 C.7. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.————————————25010075– 2001035010075180906510050405502251504001501001255038– 100– 40– 301755038360180130200100801100450300800300200—————————nsnsnsnsnsnsnsV DDV DSS0STROBE S1S2S3INHIBITS4For MC14514BS51. For P–channel: Inhibit = V SSD1 S61. and D1–D4 constituteS71. binary code for “outputS8D2 S91. under test.”S102. For N–channel: Inhibit = V DD D3 S11S12S13D4 S14S15I DEXTERNALPOWER SUPPLYFor MC14515B1. For P–channel: Inhibit = V DD2. For N–channel: Inhibit = V SS2. and D1–D4 constitute binary2. code for “output under test.”V SSFigure 1. Drain Characteristics Test Circuithttp://onsemi.com271

MC14514B, MC14515BV DDPULSEGENERATOR0.01 µFI D500CERAMICµF24 V DDD1 S0D2D3D4STROBEINHIBIT S1512 V SSC LC LV in90%V DD20 ns 20 ns10%V SSFigure 2. Dynamic Power Dissipation Test Circuit and WaveformV DDPROGRAMMABLEPULSEGENERATORSTROBEINHIBITD1D2D3D4S0S1C LOUTPUT S0OUTPUT S1C LINPUT10%t PLHOUTPUTS15OUTPUT S15V SS C Lt TLHt TLH90%50%20 ns90%50%10%t THLt THLV DDV SSt PHLV DDV SSFigure 3. Switching Time Test Circuit and Waveformshttp://onsemi.com272

MC14514B, MC14515BDATA 1 2DATA 2 3DATA 3 21DATA 4 22STROBE 1INHIBIT 23SRSRSRSRQQQQQQQQABCDLOGIC DIAGRAMIN MC14515B ONLYA B C DABC DA BCDAB CDA B CDABCDA BCDAB CDA B C DAB C DA BCDAB CDA B CDABCDA BCDAB CD11 S09 S110 S28 S37 S46 S55 S64 S718 S817 S920 S1019 S1114 S1213 S1316 S1415 S15http://onsemi.com273

MC14514B, MC14515BCOMPLEX DATA ROUTINGTwo MC14512 eight–channel data selectors are used herewith the MC14514B four–bit latch/decoder to effect acomplex data routing system. A total of 16 inputs from dataregisters are selected and transferred via a 3–state data busto a data distributor for rearrangement and entry into 16output registers. In this way sequential data can be re–routedor intermixed according to patterns determined by dataselect and distribution inputs.Data is placed into the routing scheme via the eight inputson both MC14512 data selectors. One register is assigned toeach input. The signals on A0, A1, and A2 choose one ofeight inputs for transfer out to the 3–state data bus. A fourthsignal, labelled Dis, disables one of the MC14512 selectors,assuring transfer of data from only one register.In addition to a choice of input registers, 1 thru 16, the rateof transfer of the sequential information can also be varied.That is, if the MC14512 were addressed at a rate that is eighttimes faster then the shift frequency of the input registers,the most significant bit (MSB) from each register could beselected for transfer to the data bus. Therefore, all of themost significant bits from all of the registers can betransferred to the data bus before the next most significantbit is presented for transfer by the input registers.Information from the 3–state bus is redistributed by theMC14514B four–bit latch/decoder. Using the four–bitaddress, D1 thru D4, the information on the inhibit line canbe transferred to the addressed output line to the desiredoutput registers, A thru P. This distribution of data bits to theoutput registers can be made in many complex patterns. Forexample, all of the most significant bits from the inputregisters can be routed into output register A, all of the nextmost significant bits into register B, etc. In this wayhorizontal, vertical, or other methods of data slicing can beimplemented.DATA ROUTING SYSTEMINPUTREGISTERSDATATRANSFER3–STATEDATA BUSDATADISTRIBUTIONOUTPUTREGISTERSDATASELECTREGISTER 1REGISTER 8REGISTER 9REGISTER 16D0D1D2D3D4D5D6DISMC14512QD7A0 A1 A2A0 A1 A2D0 QD1D2D3D4D5D6D7DISMC14512D1 D2 D3 D4S0STROBE S1S2S3S4S5S6S7S8S9S10S11S12S13INHIBIT S14S15MC14514BREGISTER AREGISTER Phttp://onsemi.com274

The MC14516B synchronous up/down binary counter isconstructed with MOS P–channel and N–channel enhancement modedevices in a monolithic structure.This counter can be preset by applying the desired value, in binary,to the Preset inputs (P0, P1, P2, P3) and then bringing the PresetEnable (PE) high. The direction of counting is controlled by applyinga high (for up counting) or a low (for down counting) to theUP/DOWN input. The state of the counter changes on the positivetransition of the clock input.Cascading can be accomplished by connecting the Carry Out to theCarry In of the next stage while clocking each counter in parallel. Theoutputs (Q0, Q1, Q2, Q3) can be reset to a low state by applying a highto the reset (R) pin.This CMOS counter finds primary use in up/down and differencecounting. Other applications include: (1) Frequency synthesizerapplications where low power dissipation and/or high noise immunityis desired, (2) Analog–to–digital and digital–to–analog conversions,and (3) Magnitude and sign generation.• Diode Protection on All Inputs• Supply Voltage Range = 3.0 Vdc to 18 Vdc• Internally Synchronous for High Speed• Logic Edge–Clocked Design — Count Occurs on Positive GoingEdge of Clock• Single Pin Reset• Asynchronous Preset Enable Operation• Capable of Driving Two Low–Power TTL Loads or One Low–PowerSchottky Load Over the Rated Temperature RangeMAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 2.)Symbol Parameter Value UnitV DD DC Supply Voltage Range –0.5 to +18.0 VV in , V out Input or Output Voltage Range(DC or Transient)–0.5 to V DD + 0.5 VI in , I outP DInput or Output Current(DC or Transient) per PinPower Dissipation,per Package (Note 3.)±10 mA500 mWT A Ambient Temperature Range –55 to +125 °CT stg Storage Temperature Range –65 to +150 °CT LLead Temperature(8–Second Soldering)260 °C2. Maximum Ratings are those values beyond which damage to the devicemay occur.3. Temperature Derating:Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 Chttp://onsemi.comPDIP–16P SUFFIXCASE 648SOIC–16D SUFFIXCASE 751BSOEIAJ–16F SUFFIXCASE 966A = Assembly LocationWL or L = Wafer LotYY or Y = YearWW or W = Work WeekORDERING INFORMATIONMARKINGDIAGRAMSDevice Package ShippingMC14516BCP PDIP–16 2000/BoxMC14516BD SOIC–16 48/RailMC14516BDR2 SOIC–16 2500/Tape & Reel1. For ordering information on the EIAJ version ofthe SOIC packages, please contact your localON Semiconductor representative.161161161MC14516BCPAWLYYWW14516BAWLYWWMC14516BAWLYWWMC14516BF SOEIAJ–16 See Note 1.MC14516BFEL SOEIAJ–16 See Note 1.This device contains protection circuitry to guardagainst damage due to high static voltages or electricfields. However, precautions must be taken to avoid applicationsof any voltage higher than maximum ratedvoltages to this high–impedance circuit. For properoperation, V in and V out should be constrained to therange V SS (V in or V out ) V DD .Unused inputs must always be tied to an appropriatelogic voltage level (e.g., either V SS or V DD ). Unused outputsmust be left open.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 3275 Publication Order Number:MC14516B/D

MC14516BPIN ASSIGNMENTPE116V DDQ3215CP3314Q2P0413P2CARRY IN512P1Q0611Q1CARRY OUT710U/DV SS89RBLOCK DIAGRAM1PEQ065CARRY IN9RESETQ11110UP/DOWN15CLOCKQ2144P012P1Q32133P2P3CARRYOUT7V DD = PIN 16V SS = PIN 8TRUTH TABLEPresetCarry In Up/Down Enable Reset Clock Action1 X 0 0 X No Count0 1 0 0 Count Up0 0 0 0 Count DownX X 1 0 X PresetX X X 1 X ResetX = Don’t CareNOTE: When counting up, the Carry Out signal is normally high and is low onlywhen Q0 through Q3 are high and Carry In is low. When counting down,Carry Out is low only when Q0 through Q3 and Carry In are low.http://onsemi.com276

MC14516BELECTRICAL CHARACTERISTICS (Voltages Referenced to V SS )– 55 C 25 C 125 CV DDVdc Min Max Min Typ (4.) Max Min Max UnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCharacteristicOutput VoltageV in = V DD or 0“0” LevelSymbolV OL 5.01015V 5.0“1” LevelV in = 0 or V DDOH1015Input Voltage“0” Level(V O = 4.5 or 0.5 Vdc)(V O = 9.0 or 1.0 Vdc)(V O = 13.5 or 1.5 Vdc)V IL5.01015———4.959.9514.95———0.050.050.05———1.53.04.0———4.959.9514.95———0005.010152.254.506.750.050.050.05———1.53.04.0———4.959.9514.95———0.050.050.05———1.53.04.0VdcVdcVdc(V O = 0.5 or 4.5 Vdc)(V O = 1.0 or 9.0 Vdc)(V O = 1.5 or 13.5 Vdc)“1” LevelV IH5.010153.57.011———3.57.0112.755.508.25———3.57.011———VdcOutput Drive Current(V OH = 2.5 Vdc) Source(V OH = 4.6 Vdc)(V OH = 9.5 Vdc)(V OH = 13.5 Vdc)I OH5.05.01015– 3.0– 0.64– 1.6– 4.2————– 2.4– 0.51– 1.3– 3.4– 4.2– 0.88– 2.25– 8.8————– 1.7– 0.36– 0.9– 2.4————mAdc(V OL = 0.4 Vdc) Sink(V OL = 0.5 Vdc)(V OL = 1.5 Vdc)I OL 5.010150.641.64.2Input Current I in 15 — ± 0.1 — ±0.00001 ± 0.1 — ± 1.0 µAdcInput Capacitance(V in = 0)———0.511.33.40.882.258.8C in — — — — 5.0 7.5 — — pF———0.360.92.4———mAdcQuiescent Current(Per Package)Total Supply Current (5.) (6.)(Dynamic plus Quiescent,Per Package)(C L = 50 pF on all outputs, allbuffers switching)I DD 5.01015I T 5.01015———5.01020———0.0050.0100.0155.01020I T = (0.58 µA/kHz) f + I DDI T = (1.20 µA/kHz) f + I DDI T = (1.70 µA/kHz) f + I DD4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.5. The formulas given are for the typical characteristics only at 25 C.6. To calculate total supply current at loads other than 50 pF:I T (C L ) = I T (50 pF) + (C L – 50) Vfkwhere: I T is in µA (per package), C L in pF, V = (V DD – V SS ) in volts, f in kHz is input frequency, and k = 0.001.———150300600µAdcµAdchttp://onsemi.com277

SWITCHING CHARACTERISTICS (7.) (C L = 50 pF, T A = 25 C)MC14516BAll TypesCharacteristic Symbol V DD Min Typ (8.) Max UnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Rise and Fall Timet TLH , t THL = (1.5 ns/pF) C L + 25 nst TLH , t THL = (0.75 ns/pF) C L + 12.5 nst TLH , t THL = (0.55 ns/pF) C L + 9.5 nsPropagation Delay TimeClock to Qt PLH , t PHL = (1.7 ns/pF) C L + 230 nst PLH , t PHL = (0.66 ns/pF) C L + 97 nst PLH , t PHL = (0.5 ns/pF) C L + 75 nsClock to Carry Outt PLH , t PHL = (1.7 ns/pF) C L + 230 nst PLH , t PHL = (0.66 ns/pF) C L + 97 nst PLH , t PHL = (0.5 ns/pF) C L + 75 nsCarry In to Carry Outt PLH , t PHL = (1.7 ns/pF) C L + 230 nst PLH , t PHL = (0.66 ns/pF) C L + 97 nst PLH , t PHL = (0.5 ns/pF) C L + 75 nsPreset or Reset to Qt PLH , t PHL = (1.7 ns/pF) C L + 230 nst PLH , t PHL = (0.66 ns/pF) C L + 97 nst PLH , t PHL = (0.5 ns/pF) C L + 75 nsPreset or Reset to Carry Outt PLH , t PHL = (1.7 ns/pF) C L + 465 nst PLH , t PHL = (0.66 ns/pF) C L + 192 nst PLH , t PHL = (0.5 ns/pF) C L + 125 nst TLH ,t THL 5.01015t PLH ,t PHL5.01015t PLH ,t PHL 5.01015t PLH ,t PHL 5.01015t PLH ,t PHL 5.01015t PLH ,t PHL 5.01015Reset Pulse Width t w 5.01015Clock Pulse Width t WH 5.01015Clock Pulse Frequency f cl 5.010157. The formulas given are for the typical characteristics only at 25 C.8. Data labelled “Typ” is not to be used for design purposes but is intended as an Indication of the IC’s potential performance.——————————————————380200160350170140———1005040315130100315130100180806031513010055022515019010080200100753.06.08.0200100806302602006302602003601601206303602001100450300——————1.53.04.0nsnsnsnsnsnsnsnsMHzhttp://onsemi.com278

MC14516BSWITCHING CHARACTERISTICS (9.) (C L = 50 pF, T A = 25 C) (continued)All TypesCharacteristic Symbol V DD Min Typ (10.) Max Unitt rem 5.0 650 325 — ns10 230 11515 180 90 —ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPreset or Reset Removal TimeThe Preset or Reset signal must be low prior to apositive–going transition of the clock.Clock Rise and Fall Time t TLH , 5.0t THL 1015Setup TimeCarry In to ClockHold TimeClock to Carry InSetup TimeUp/Down to ClockHold TimeClock to Up/DownSetup TimePn to PEHold TimePE to Pnt su 5.01015t h 5.01015t su 5.01015t h 5.01015t su 5.01015t h 5.01015Preset Enable Pulse Width t WH 5.01015———26012010002020500200150– 70– 100– 40– 30– 2548042042020010080———1306050– 60– 20025010075– 160– 60– 40– 120– 70– 5024021021010050409. The formulas given are for the typical characteristics only at 25 C.10.Data labelled “Typ” is not to be used for design purposes but is intended as an Indication of the IC’s potential performance.1554—————————————————————µsnsnsnsnsnsnsnshttp://onsemi.com279

MC14516BV DD500 pFI D 0.01 µFCERAMICPEQ0PULSEGENERATORCARRY INRUP/DOWNCLOCKP0P1P2P3Q1Q2Q3CARRYOUTC LC LC LC L20 nsCLOCK50%VARIABLEWIDTH90%10%20 nsV DDV SSC LFigure 1. Power Dissipation Test Circuit and WaveformLOGIC DIAGRAMP04Q06P112Q111P213Q214P33Q32RESET9PRESETENABLE1CLOCK15PPEQPPEQPPEQPPEQCARRY OUT7CTQCTQCTQCTQCARRY IN5UP/DOWN 10http://onsemi.com280

MC14516BTOGGLE FLIP–FLOPPARALLEL INPPE QCT QFLIP–FLOP FUNCTIONAL TRUTH TABLEPresetEnable Clock T Q n+11 X X Parallel In0 0 Q n0 1 Q n0 X Q nX = Don’t CareCARRY IN ORUP/DOWNPRESET ENABLERESETCLOCKQ 0 OR CARRY OUT50%t sut rem1t hf cl50%50%t t w(H)w(H)CARRY OUT ONLY90%10%t PHLt THLt PLHt remt w90%10%t TLHt PLHV DDV SSV DDV SSV DDV SSV OHV OLV DDV SSFigure 2. Switching Time WaveformsPIN DESCRIPTIONSINPUTSP0, P1, P2, P3, Preset Inputs (Pins 4, 12, 13, 3) — Dataon these inputs is loaded into the counter when PE is takenhigh.Carry In, (Pin 5) — This active–low input is used whenCascading stages. Carry In is usually connected to Carry Outof the previous stage. While high, Clock is inhibited.Clock, (Pin 15) — Binary data is incremented ordecremented, depending on the direction of count, on thepositive transition of this input.OUTPUTSQ0, Q1, Q2, Q3, Binary outputs (Pins 6, 11, 14, 2) —Binary data is present on these outputs with Q0corresponding to the least significant bit.Carry Out, (Pin 7) — Used when cascading stages, CarryOut is usually connected to Carry In of the next stage. Thissynchronous output is active low and may also be used toindicate terminal count.CONTROLSPE, Preset Enable, (Pin 1) — Asynchronously loads dataon the Preset Inputs. This pin is active high and inhibits theclock when high.R, Reset, (Pin 9) — Asynchronously resets the Q out–puts to a low state. This pin is active high and inhibits theclock when high.Up/Down, (Pin 10) — Controls the direction of count,high for up count, low for down count.SUPPLY PINSV SS , Negative Supply Voltage, (Pin 8) — This pin isusually connected to ground.V DD , Positive Supply Voltage, (Pin 16) — This pin isconnected to a positive supply voltage ranging from 3.0volts to 18.0 volts.http://onsemi.com281

MC14516B0 = COUNT1 = PRESET1 = UP0 = DOWNPRESETENABLEQ0 Q1 Q2 Q3PEC inC outCLOCKU/DRQ0 Q1 Q2 Q3 Q4 Q5 Q6 Q7L.S.D.MC14516BP0 P1 P2 P3Q0 Q1 Q2 Q3PEC inC outCLOCKU/DRM.S.D.MC14516BP0 P1 P2 P3TERMINAL COUNTINDICATORP0 P1 P2 P3 P4 P5 P6 P7CLOCK+V DDTHUMBWHEEL SWITCHES(OPEN FOR “0”)RESISTORS = 10 k+V DDRESET+V DDOPEN = COUNTNOTE: The Least Significant Digit (L.S.D.) counts from a preset value once Preset Enable (PE) goes low. The Most SignificantDigit (M.S.D.) is disabled while C in is high. When the count of the L.S.D. reaches 0 (count down mode) or reaches 15 (countup mode), C out goes low for one complete clock cycle, thus allowing the next counter to decrement/increment one count.(See Timing Diagram) The L.S.D. now counts through another cycle (15 clock pulses) and the above cycle is repeated.Figure 3. Presettable Cascaded 8–Bit Up/Down Counterhttp://onsemi.com282

MC14516BTIMING DIAGRAM FOR THE PRESETTABLE CASCADED 8–BIT UP/DOWN COUNTERCLOCKUP/DOWNCARRY IN(MSD)PEP7P6P5P4P3P2P1P0CARRY OUT(MSD)Q7Q6Q5Q4Q3Q2Q1Q0CARRY OUT(LSD)RESETCOUNT13 14 15 16 17 18 19 18 17 16 15 14 13 251 252 253 254 255 0 1 2 3 2 1 0 1 2PRESET ENABLEPRESETENABLEUP COUNT DOWN COUNT UP COUNT DOWNCOUNTUP COUNTRESEThttp://onsemi.com283

MC14516Bf outQ0 Q1 Q2 Q3 Q4 Q5 Q6 Q7BUFFERCLOCK (f in )RESET+V DDOPEN = COUNTQ0 Q1 Q2 Q3PEC inCLOCKU/DRL.S.D.MC14516BP0 P1 P2 P3P0 P1 P2 P3+V DDC outTHUMBWHEEL SWITCHES(OPEN FOR “0”)Q0 Q1 Q2 Q3PEC inC outCLOCKM.S.D.MC14516BU/DRP0 P1 P2 P3P4 P5 P6 P7+V DDRESISTORS = 10 kff out = innNOTE: The programmable frequency divider can be set by applying the desired divide ratio, in binary, to the preset inputs. For example,the maximum divide ratio of 255 may be obtained by applying a 1111 1111 to the preset inputs P0 to P7. For this divide operation,both counters should be configured in the count down mode. The divide ratio of zero is an undefined state and should be avoided.Figure 4. Programmable Cascaded Frequency Dividerhttp://onsemi.com284

The MC14517B dual 64–bit static shift register consists of twoidentical, independent, 64–bit registers. Each register has separate clockand write enable inputs, as well as outputs at bits 16, 32, 48, and 64. Dataat the data input is entered by clocking, regardless of the state of the writeenable input. An output is disabled (open circuited) when the write enableinput is high. During this time, data appearing at the data input as well asthe 16–bit, 32–bit, and 48–bit taps may be entered into the device byapplication of a clock pulse. This feature permits the register to be loadedwith 64 bits in 16 clock periods, and also permits bus logic to be used.This device is useful in time delay circuits, temporary memory storagecircuits, and other serial shift register applications.• Diode Protection on All Inputs• Fully Static Operation• Output Transitions Occur on the Rising Edge of the Clock Pulse• Exceedingly Slow Input Transition Rates May Be Applied to theClock Input• 3–State Output at 64th–Bit Allows Use in Bus Logic Applications• Shift Registers of any Length may be Fully Loaded with 16 ClockPulses• Supply Voltage Range = 3.0 Vdc to 18 Vdc• Capable of Driving Two Low–power TTL Loads or One Low–powerSchottky TTL Load Over the Rated Temperature RangeMAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 1.)Symbol Parameter Value UnitV DD DC Supply Voltage Range –0.5 to +18.0 VV in , V out Input or Output Voltage Range(DC or Transient)–0.5 to V DD + 0.5 VI in , I outP DInput or Output Current(DC or Transient) per PinPower Dissipation,per Package (Note 2.)±10 mA500 mWhttp://onsemi.comPDIP–16P SUFFIXCASE 648SOIC–16DW SUFFIXCASE 751GA = Assembly LocationWL or L = Wafer LotYY or Y = YearWW or W = Work WeekORDERING INFORMATIONMARKINGDIAGRAMS16Device Package ShippingMC14517BCP PDIP–16 2000/BoxMC14517BDW SOIC–16 47/Rail1MC14517BCPAWLYYWWMC14517BDWR2 SOIC–16 1000/Tape & Reel16114517BAWLYYWWT A Operating Temperature Range –55 to +125 °CT stg Storage Temperature Range –65 to +150 °CT LLead Temperature(8–Second Soldering)260 °C1. Maximum Ratings are those values beyond which damage to the devicemay occur.2. Temperature Derating:Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 CThis device contains protection circuitry to guard against damage due to highstatic voltages or electric fields. However, precautions must be taken to avoidapplications of any voltage higher than maximum rated voltages to thishigh–impedance circuit. For proper operation, V in and V out should be constrainedto the range V SS (V in or V out ) V DD .Unused inputs must always be tied to an appropriate logic voltage level (e.g.,either V SS or V DD ). Unused outputs must be left open.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 3285 Publication Order Number:MC14517B/D

MC14517BPIN ASSIGNMENTQ16 A116V DDQ48 A215Q16 BWE A314Q48 BC A413WE BQ64 A512C BQ32 A611Q64 BD A710Q32 BV SS89D BClockFUNCTIONAL TRUTH TABLE (X = Don’t Care)WriteEnable Data 16–Bit Tap 32–Bit Tap 48–Bit Tap 64–Bit Tap0 0 X Content of 16–BitDisplayedContent of 32–BitDisplayedContent of 48–BitDisplayedContent of 64–BitDisplayed0 1 X High Impedance High Impedance High Impedance High Impedance1 0 X Content of 16–BitDisplayedContent of 32–BitDisplayedContent of 48–BitDisplayedContent of 64–BitDisplayed1 1 X High Impedance High Impedance High Impedance High Impedance0 Data enteredinto 1st Bit1 Data enteredinto 1st BitContent of 16–BitDisplayedData at tapentered into 17–Bit0 X Content of 16–BitDisplayedContent of 32–BitDisplayedData at tapentered into 33–BitContent of 32–BitDisplayedContent of 48–BitDisplayedData at tapentered into 49–BitContent of 48–BitDisplayedContent of 64–BitDisplayedHigh ImpedanceContent of 64–BitDisplayed1 X High Impedance High Impedance High Impedance High Impedancehttp://onsemi.com286

MC14517BELECTRICAL CHARACTERISTICS (Voltages Referenced to V SS )– 55 C 25 C 125 CV DDVdc Min Max Min Typ (3.) Max Min Max UnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCharacteristicOutput VoltageV in = V DD or 0“0” LevelSymbolV OL 5.01015V 5.0“1” LevelV in = 0 or V DDOH1015Input Voltage“0” Level(V O = 4.5 or 0.5 Vdc)(V O = 9.0 or 1.0 Vdc)(V O = 13.5 or 1.5 Vdc)V IL5.01015———4.959.9514.95———0.050.050.05———1.53.04.0———4.959.9514.95———0005.010152.254.506.750.050.050.05———1.53.04.0———4.959.9514.95———0.050.050.05———1.53.04.0VdcVdcVdc(V O = 0.5 or 4.5 Vdc)(V O = 1.0 or 9.0 Vdc)(V O = 1.5 or 13.5 Vdc)“1” LevelV IH5.010153.57.011———3.57.0112.755.508.25———3.57.011———VdcOutput Drive Current(V OH = 2.5 Vdc) Source(V OH = 4.6 Vdc)(V OH = 9.5 Vdc)(V OH = 13.5 Vdc)I OH5.05.01015– 3.0– 0.64– 1.6– 4.2————– 2.4– 0.51– 1.3– 3.4– 4.2– 0.88– 2.25– 8.8————– 1.7– 0.36– 0.9– 2.4————mAdc(V OL = 0.4 Vdc) Sink(V OL = 0.5 Vdc)(V OL = 1.5 Vdc)I OL 5.010150.641.64.2Input Current I in 15 — ± 0.1 — ±0.00001 ± 0.1 — ± 1.0 µAdcInput Capacitance(V in = 0)———0.511.33.40.882.258.8C in — — — — 5.0 7.5 — — pF———0.360.92.4———mAdcQuiescent Current(Per Package)I DD 5.01015———5.01020———0.0050.0100.0155.01020———150300600µAdcTotal Supply Current (4.) (5.)(Dynamic plus Quiescent,Per Package)(C L = 50 pF on all outputs, allbuffers switching)I T 5.01015I T = (4.2 µA/kHz) f + I DDI T = (8.8 µA/kHz) f + I DDI T = (13.7 µA/kHz) f + I DDµAdcThree–State Leakage Current I TL 15 — ± 0.1 — ± 0.0001 ± 0.1 — ± 3.0 µAdc3. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.4. The formulas given are for the typical characteristics only at 25 C.5. To calculate total supply current at loads other than 50 pF:I T (C L ) = I T (50 pF) + (C L – 50) Vfkwhere: I T is in µA (per package), C L in pF, V = (V DD – V SS ) in volts, f in kHz is input frequency, and k = 0.004.http://onsemi.com287

MC14517BSWITCHING CHARACTERISTICS (6.) (C L = 50 pF, T A = 25 C)Characteristic Symbol V DD Min Typ (7.) Max UnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Rise and Fall Timet TLH , t THL = (1.5 ns/pF) C L + 25 nst TLH , t THL = (0.75 ns/pF) C L + 12.5 nst TLH , t THL = (0.65 ns/pF) C L + 9.5 nsPropagation Delay Timet PLH , t PHL = (1.7 ns/pF) C L + 390 nst PLH , t PHL = (0.66 ns/pF) C L + 177 nst PLH , t PHL = (0.5 ns/pF) C L + 115 nst TLH , t THL5.01015t PLH , t PHL5.01015Clock Pulse Width t WH 5.01015Clock Pulse Frequency f cl 5.01015Clock Pulse Rise and Fall Time t TLH , t THL 5.01015Data to Clock Setup Time t su 5.01015Data to Clock Hold Time t h 5.01015Write Enable to Clock Setup Time t su 5.01015Write Enable to Clock Release Time t rel 5.01015——————330125100———010151507535400200110100504047521014017075603.06.78.320010080770300215———1.54.05.3nsnsnsMHzSee Note (8.) —6. The formulas given are for the typical characteristics only at 25 C.7. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.8. When shift register sections are cascaded, the maximum rise and fall time of the clock input should be equal to or less than the rise and falltime of the data outputs, driving data inputs, plus the propagation delay of the output driving stage.380180100– 40– 15075251017065501605540————————————nsnsnsnsC Lf oCREPETITIVE WAVEFORMV DDV SSDCV DDQ16 Q32 Q48 Q64DCWEC LC LC LD(f = 1/2 f o )V DDV SSDCWEQ16 Q32 Q48Q6450 µFI DV SSC L C L C L C LFigure 1. Power Dissipation Test Circuit and Waveformhttp://onsemi.com288

MC14517BV out = V OHV out = V OLV DD = V GSV DD = V GSDCWEQ16Q32 Q48 Q64DCWEQ16Q32 Q48 Q64DCWEI OHDCWEI OLQ16Q32 Q48 Q64Q16Q32 Q48 Q64V SSEXTERNALPOWERSUPPLYV SSEXTERNALPOWERSUPPLY(Output being tested should be in the high–logic state)Figure 2. Typical Output Source CurrentCharacteristics Test Circuit(Output being tested should be in the low–logic state)Figure 3. Typical Output Sink CurrentCharacteristics Test CircuitPIN NO’SCLOCK 4 (12)WRITE 3 (13)1 2 16 17 18 19 90%10%33t relt suV DD50%V SSV DDt su1DATA IN 7 (9)t su116–BIT OUTPUT 1 (15)17–BIT INPUTt su132–BIT OUTPUT 6 (10)33–BIT INPUTt su148–BIT OUTPUT 2 (14)49–BIT INPUT64–BIT OUTPUT 5 (11)t h1t h1t h1t h1t h0t su0t su0t h0t su0t h050%t su0t h0V DD20 nsV DD20 nsV DD20 ns20 nst WHt THLt PHLt PLHt PHL t TLHt PLH90%90%t PHLt TLHt PHLt PLHt TLHt PLHt TLHt WL90%50%10%V OH10%Vt OL THLV OH50%10%V OLt THLV OHt THLV OLV SSV DDV SSV DDV SSV DDV SSV DDV SSV DDV SSFigure 4. AC Test WaveformsEXPANDED BLOCK DIAGRAM (1/2 OF DEVICE SHOWN)CLOCKDATADC1QDC2QD QC163–STATEDC17WEQD QC323–STATEDC33WEQD QC483–STATEDC49WEQDC64Q3–STATEWRITEENABLEWRITE ENABLE = 0, 16–BIT OUTPUTWRITE ENABLE = 1, 17–BIT INPUT32–BIT OUTPUT33–BIT INPUT48–BIT OUTPUT49–BIT INPUT64–BIT OUTPUTHIGH IMPEDANCEhttp://onsemi.com289

The MC14518B dual BCD counter and the MC14520B dual binarycounter are constructed with MOS P–channel and N–channelenhancement mode devices in a single monolithic structure. Eachconsists of two identical, independent, internally synchronous 4–stagecounters. The counter stages are type D flip–flops, withinterchangeable Clock and Enable lines for incrementing on either thepositive–going or negative–going transition as required whencascading multiple stages. Each counter can be cleared by applying ahigh level on the Reset line. In addition, the MC14518B will count outof all undefined states within two clock periods. These complementaryMOS up counters find primary use in multi–stage synchronous orripple counting applications requiring low power dissipation and/orhigh noise immunity.• Diode Protection on All Inputs• Supply Voltage Range = 3.0 Vdc to 18 Vdc• Internally Synchronous for High Internal and External Speeds• Logic Edge–Clocked Design — Incremented on Positive Transitionof Clock or Negative Transition on Enable• Capable of Driving Two Low–power TTL Loads or One Low–powerSchottky TTL Load Over the Rated Temperature RangeMAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 2.)Symbol Parameter Value UnitV DD DC Supply Voltage Range –0.5 to +18.0 VV in , V out Input or Output Voltage Range(DC or Transient)–0.5 to V DD + 0.5 VI in , I outP DInput or Output Current(DC or Transient) per PinPower Dissipation,per Package (Note 3.)±10 mA500 mWT A Operating Temperature Range –55 to +125 °CT stg Storage Temperature Range –65 to +150 °CT LLead Temperature(8–Second Soldering)260 °C2. Maximum Ratings are those values beyond which damage to the devicemay occur.3. Temperature Derating:Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 CThis device contains protection circuitry to guard against damage due to highstatic voltages or electric fields. However, precautions must be taken to avoidapplications of any voltage higher than maximum rated voltages to thishigh–impedance circuit. For proper operation, V in and V out should be constrainedto the range V SS (V in or V out ) V DD .Unused inputs must always be tied to an appropriate logic voltage level (e.g.,either V SS or V DD ). Unused outputs must be left open.http://onsemi.comPDIP–16P SUFFIXCASE 648SOIC–16DW SUFFIXCASE 751GSOEIAJ–16F SUFFIXCASE 966A = Assembly LocationWL or L = Wafer LotYY or Y = YearWW or W = Work WeekORDERING INFORMATIONMARKINGDIAGRAMS16Device Package ShippingMC14518BCP PDIP–16 2000/BoxMC14518BDW SOIC–16 47/Rail1MC14518BCPAWLYYWWMC14518BDWR2 SOIC–16 1000/Tape & Reel16114518BAWLYYWW1. For ordering information on the EIAJ version ofthe SOIC packages, please contact your localON Semiconductor representative.161MC14518BAWLYWWMC14518BF SOEIAJ–16 See Note 1.MC14518BFEL SOEIAJ–16 See Note 1.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 3290 Publication Order Number:MC14518B/D

MC14518BPIN ASSIGNMENTC A116V DDE A215R BQ0 A314Q3 BQ1 A413Q2 BQ2 A512Q1 BQ3 A611Q0 BR A710E BV SS89C BCLOCK12ENABLE7CLOCK910ENABLE15BLOCK DIAGRAMCCQ0Q1Q2Q3RQ0Q1Q2R Q3V DD = PIN 16V SS = PIN 8345611121314TRUTH TABLEClock Enable Reset Action1 0 Increment Counter0 0 Increment CounterX 0 No ChangeX 0 No Change0 0 No Change1 0 No ChangeX X 1 Q0 thru Q3 = 0X = Don’t Carehttp://onsemi.com291

MC14518BELECTRICAL CHARACTERISTICS (Voltages Referenced to V SS )– 55 C 25 C 125 CV DDVdc Min Max Min Typ (4.) Max Min Max UnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCharacteristicOutput VoltageV in = V DD or 0“0” LevelSymbolV OL 5.01015V 5.0“1” LevelV in = 0 or V DDOH1015Input Voltage“0” Level(V O = 4.5 or 0.5 Vdc)(V O = 9.0 or 1.0 Vdc)(V O = 13.5 or 1.5 Vdc)V IL5.01015———4.959.9514.95———0.050.050.05———1.53.04.0———4.959.9514.95———0005.010152.254.506.750.050.050.05———1.53.04.0———4.959.9514.95———0.050.050.05———1.53.04.0VdcVdcVdc(V O = 0.5 or 4.5 Vdc)(V O = 1.0 or 9.0 Vdc)(V O = 1.5 or 13.5 Vdc)“1” LevelV IH5.010153.57.011———3.57.0112.755.508.25———3.57.011———VdcOutput Drive Current(V OH = 2.5 Vdc) Source(V OH = 4.6 Vdc)(V OH = 9.5 Vdc)(V OH = 13.5 Vdc)I OH5.05.01015– 3.0– 0.64– 1.6– 4.2————– 2.4– 0.51– 1.3– 3.4– 4.2– 0.88– 2.25– 8.8————– 1.7– 0.36– 0.9– 2.4————mAdc(V OL = 0.4 Vdc) Sink(V OL = 0.5 Vdc)(V OL = 1.5 Vdc)I OL 5.010150.641.64.2Input Current I in 15 — ± 0.1 — ±0.00001 ± 0.1 — ± 1.0 µAdcInput Capacitance(V in = 0)———0.511.33.40.882.258.8C in — — — — 5.0 7.5 — — pF———0.360.92.4———mAdcQuiescent Current(Per Package)Total Supply Current (5.) (6.)(Dynamic plus Quiescent,Per Package)(C L = 50 pF on all outputs, allbuffers switching)I DD 5.01015I T 5.01015———5.01020———0.0050.0100.0155.01020I T = (0.6 µA/kHz) f + I DDI T = (1.2 µA/kHz) f + I DDI T = (1.7 µA/kHz) f + I DD4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.5. The formulas given are for the typical characteristics only at 25 C.6. To calculate total supply current at loads other than 50 pF:I T (C L ) = I T (50 pF) + (C L – 50) Vfkwhere: I T is in µA (per package), C L in pF, V = (V DD – V SS ) in volts, f in kHz is input frequency, and k = 0.002.———150300600µAdcµAdchttp://onsemi.com292

SWITCHING CHARACTERISTICS (7.) (C L = 50 pF, T A = 25 C)MC14518BAll TypesÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCharacteristic Symbol V DD Min Typ (8.) Max UnitOutput Rise and Fall Timet TLH , t THL = (1.5 ns/pF) C L + 25 nst TLH , t THL = (0.75 ns/pF) C L + 12.5 nst TLH , t THL = (0.55 ns/pF) C L + 9.5 nsPropagation Delay TimeClock to Q/Enable to Qt PLH , t PHL = (1.7 ns/pF) C L + 215 nst PLH , t PHL = (0.66 ns/pF) C L + 97 nst PLH , t PHL = (0.5 ns/pF) C L + 75 nst TLH ,t THL 5.01015t PLH ,t PHL5.01015——————10050402801158020010080560230160nsnsReset to Qt PHL = (1.7 ns/pF) C L + 265 nst PHL = (0.66 ns/pF) C L + 117 nst PHL = (0.66 ns/pF) C L + 95 nsClock Pulse Widtht PHL5.01015t w(H)5.0t w(L) 1015Clock Pulse Frequency f cl 5.01015Clock or Enable Rise and Fall Time t THL , t TLH 5.01015Enable Pulse Width t WH(E) 5.01015Reset Pulse Width t WH(R) 5.01015Reset Removal Time t rem 5.010157. The formulas given are for the typical characteristics only at 25 C.8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.———20010070——————44020014028012090– 515203301309010050352.56.08.0———220100701255540– 45– 15– 5650230170———1.53.04.01554—————————nsnsMHzµsnsnsnsPULSEGENERATORV DDV SS500 µF0.01 µFCERAMICCERI DQ3Q0Q1Q2C LCLC LC L20 ns50%VARIABLEWIDTH90%10%20 nsV SSFigure 1. Power Dissipation Test Circuit and Waveformhttp://onsemi.com293

MC14518BPULSEGENERATORCERV DDQ0Q1Q2Q3V SSC LC LC LC L20 nsCLOCKINPUTQV DDt WHt f20 ns90%t r50%10%V SSt WLt PLH t PHL90%50%10%Figure 2. Switching Time Test Circuit and Waveforms123456789101112131415161718CLOCKENABLERESET12345678901234567890Q0MC14518BQ1Q2Q31 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4Q0MC14520BQ1Q2Q3Figure 3. Timing Diagramhttp://onsemi.com294

MC14518BQ0 Q1 Q2 Q3DQC RQDQC RQDQC RQDQC RQRESETENABLECLOCKFigure 4. Decade Counter (MC14518B) Logic Diagram(1/2 of Device Shown)Q0 Q1 Q2 Q3D QC Q RD QC Q RD QC Q RD QC Q RRESETENABLECLOCKFigure 5. Binary Counter (MC14520B) Logic Diagram(1/2 of Device Shown)http://onsemi.com295

The MC14521B consists of a chain of 24 flip–flops with an inputcircuit that allows three modes of operation. The input will function asa crystal oscillator, an RC oscillator, or as an input buffer for anexternal oscillator. Each flip–flop divides the frequency of theprevious flip–flop by two, consequently this part will count up to 2 24 =16,777,216. The count advances on the negative going edge of theclock. The outputs of the last seven–stages are available for addedflexibility.• All Stages are Resettable• Reset Disables the RC Oscillator for Low Standby Power Drain• RC and Crystal Oscillator Outputs Are Capable of Driving ExternalLoads• Test Mode to Reduce Test Time• V DD ′ and V SS ′ Pins Brought Out on Crystal Oscillator Inverter toAllow the Connection of External Resistors for Low–PowerOperation• Supply Voltage Range = 3.0 Vdc to 18 Vdc• Capable of Driving Two Low–power TTL Loads or One Low–powerSchottky TTL Load over the Rated Temperature Range.MAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 2.)Symbol Parameter Value UnitV DD DC Supply Voltage Range –0.5 to +18.0 VV in , V out Input or Output Voltage Range(DC or Transient)–0.5 to V DD + 0.5 VI in , I outP DInput or Output Current(DC or Transient) per PinPower Dissipation,per Package (Note 3.)±10 mA500 mWT A Ambient Temperature Range –55 to +125 °CT stg Storage Temperature Range –65 to +150 °CT LLead Temperature(8–Second Soldering)260 °C2. Maximum Ratings are those values beyond which damage to the devicemay occur.3. Temperature Derating:Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 CThis device contains protection circuitry to guard against damage due to highstatic voltages or electric fields. However, precautions must be taken to avoidapplications of any voltage higher than maximum rated voltages to thishigh–impedance circuit. For proper operation, V in and V out should be constrainedto the range V SS (V in or V out ) V DD .Unused inputs must always be tied to an appropriate logic voltage level (e.g.,either V SS or V DD ). Unused outputs must be left open.http://onsemi.comPDIP–16P SUFFIXCASE 648SOIC–16D SUFFIXCASE 751BSOEIAJ–16F SUFFIXCASE 966A = Assembly LocationWL or L = Wafer LotYY or Y = YearWW or W = Work WeekORDERING INFORMATIONMARKINGDIAGRAMSDevice Package ShippingMC14521BCP PDIP–16 2000/BoxMC14521BD SOIC–16 48/RailMC14521BDR2 SOIC–16 2500/Tape & Reel1. For ordering information on the EIAJ version ofthe SOIC packages, please contact your localON Semiconductor representative.161161161MC14521BCPAWLYYWW14521BAWLYWWMC14521BAWLYWWMC14521BF SOEIAJ–16 See Note 1.MC14521BFEL SOEIAJ–16 See Note 1.MC14521BFR2 SOEIAJ–16 See Note 1.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 3296 Publication Order Number:MC14521B/D

MC14521BPIN ASSIGNMENTQ24116V DDRESET215Q23V SS ′314Q22OUT 2413Q21V DD ′512Q20IN 2611Q19710Q18V SS89IN 1BLOCK DIAGRAMRESET29IN 17OUT 16IN 25V DD ′43 OUT2V SS ′STAGES1 THRU 17V DD = PIN 16V SS = PIN 8STAGES18 THRU 24Q18 Q19 Q20 Q21 Q22 Q23 Q2410 11 12 13 14 15 1Output Count CapacityQ18 2 18 = 262,144Q19 2 19 = 524,288Q20 2 20 = 1,048,576Q21 2 21 = 2,097,152Q22 2 22 = 4,194,304Q23 2 23 = 8,388,608Q24 2 24 = 16,777,216http://onsemi.com297

MC14521BELECTRICAL CHARACTERISTICS (Voltages Referenced to V SS )– 55 C 25 C 125 CV DDVdc Min Max Min Typ (4.) Max Min Max UnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCharacteristicOutput VoltageV in = V DD or 0“0” LevelSymbolV OL 5.01015V 5.0“1” LevelV in = 0 or V DDOH1015Input Voltage“0” Level(V O = 4.5 or 0.5 Vdc)(V O = 9.0 or 1.0 Vdc)(V O = 13.5 or 1.5 Vdc)V IL5.01015———4.959.9514.95———0.050.050.05———1.53.04.0———4.959.9514.95———0005.010152.254.506.750.050.050.05———1.53.04.0———4.959.9514.95———0.050.050.05———1.53.04.0VdcVdcVdc(V O = 0.5 or 4.5 Vdc)(V O = 1.0 or 9.0 Vdc)(V O = 1.5 or 13.5 Vdc)“1” LevelV IH5.010153.57.011———3.57.0112.755.508.25———3.57.011———VdcOutput Drive Current(V OH = 2.5 Vdc) Source(V OH = 4.6 Vdc) Pins 4 & 7(V OH = 9.5 Vdc)(V OH = 13.5 Vdc)I OH5.05.01015– 1.2– 0.25– 0.62– 1.8————– 1.0– 0.2– 0.5– 1.5– 1.7– 0.36– 0.9– 3.5————– 0.7– 0.14– 0.35– 1.1————mAdc(V OH = 2.5 Vdc) Source(V OH = 4.6 Vdc) Pins 1, 10,(V OH = 9.5 Vdc) 11, 12, 13, 14(V OH = 13.5 Vdc) and 155.05.01015– 3.0– 0.64– 1.6– 4.2————– 2.4– 0.51– 1.3– 3.4– 4.2– 0.88– 2.25– 8.8————– 1.7– 0.36– 0.9– 2.4————mAdc(V OL = 0.4 Vdc) Sink(V OL = 0.5 Vdc)(V OL = 1.5 Vdc)I OL 5.010150.641.64.2———0.511.33.40.882.258.8———0.360.92.4———mAdcInput Current I in 15 — ± 0.1 — ±0.00001 ± 0.1 — ± 1.0 µAdcInput Capacitance(V in = 0)C in — — — — 5.0 7.5 — — pFQuiescent Current(Per Package)Total Supply Current (5.) (6.)(Dynamic plus Quiescent,Per Package)(C L = 50 pF on all outputs, allbuffers switching)I DD 5.01015I T 5.01015———5.01020———0.0050.0100.0155.01020I T = (0.42 µA/kHz) f + I DDI T = (0.85 µA/kHz) f + I DDI T = (1.40 µA/kHz) f + I DD4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.5. The formulas given are for the typical characteristics only at 25 C.6. To calculate total supply current at loads other than 50 pF:I T (C L ) = I T (50 pF) + (C L – 50) Vfkwhere: I T is in µA (per package), C L in pF, V = (V DD – V SS ) in volts, f in kHz is input frequency, and k = 0.003.———150300600µAdcµAdchttp://onsemi.com298

MC14521BSWITCHING CHARACTERISTICS (7.) (C L = 50 pF, T A = 25 C)CharacteristicSymbolV DDVdc Min Typ (8.) Max UnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Rise and Fall Time (Counter Outputs)t TLH , t THL = (1.5 ns/pF) C L + 25 nst TLH , t THL = (0.75 ns/pF) C L + 12.5 nst TLH , t THL = (0.55 ns/pF) C L + 12.5 nsPropagation Delay TimeClock to Q18t PHL , t PLH = (1.7 ns/pF) C L + 4415 nst PHL , t PLH = (0.66 ns/pF) C L + 1667 nst PHL , t PLH = (0.5 ns/pF) C L + 1275 nst TLH , t THL5.01015t PHL , t PLH5.01015——————10050404.51.71.3200100809.03.52.7nsµsClock to Q24t PHL , t PLH = (1.7 ns/pF) C L + 5915 nst PHL , t PLH = (0.66 ns/pF) C L + 2167 nst PHL , t PLH = (0.5 ns/pF) C L + 1675 nsPropagation Delay TimeReset to Q nt PHL = (1.7 ns/pF) C L + 1215 nst PHL = (0.66 ns/pF) C L + 467 nst PHL = (0.5 ns/pF) C L + 350 ns5.01015t PHL5.01015Clock Pulse Width t WH(cl) 5.01015Clock Pulse Frequency f cl 5.01015Clock Rise and Fall Time t TLH , t THL 5.01015Reset Pulse Width t WH(R) 5.01015Reset Removal Time t rem 5.01015——————385150120——————1400600450300– 406.02.21.7130050037514055403.59.012———700300225– 200– 160– 1107. The formulas given are for the typical characteristics only at 25 C.8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.124.53.526001000750———2.05.06.5155.04.0——————nsnsMHzµsnsnsV DD500 µFI D0.01 µFCERAMICV DDV DDPULSEGENERATORIN 2RV SSQ18Q19Q20Q21Q22Q23Q24V SSC LC LC LC LC LC LC LV in20 ns 20 ns90%V DD50%10%0 V50% DUTY CYCLEFigure 1. Power Dissipation Test Circuit and Waveformhttp://onsemi.com299

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMC14521BV DD20 ns 20 ns 20 nsPULSEGENERATORV DD V DD ′Q18IN 2 Q19C LCQ20LCQ21LQ22C LRQ23C LQ24C LC LV SS V SS ′IN 250% 90%10%Q nt WLt WH50%90%10%t PLH t PHLt TLHt THLFigure 2. Switching Time Test Circuit and WaveformsC SR oC T18 MIN 1IN 2V DDR*V DD V DD ′OUT 1OUT 2Q18Q19Q20Q21Q22Q23Q24*Optional for low power operation,10 kΩ ≤ R ≤ 70 kΩ.Figure 3. Crystal Oscillator CircuitRV SS V SS ′R*Characteristic500 kHzCircuitCrystal CharacteristicsResonant FrequencyEquivalent Resistance, R S5001.0External Resistor/Capacitor ValuesR o47C T82C S 20Frequency StabilityFrequency Change as a Functionof V DD (T A = 25 C)V DD Change from 5.0 V to 10 VV DD Change from 10 V to 15 VFrequency Change as a Functionof Temperature (V DD = 10 V)T A Change from – 55 C to + 25 CMC14521 onlyComplete Oscillator*T A Change from + 25 C to +125 CMC14521 onlyComplete Oscillator*+ 6.0+ 2.0– 4.0+ 100– 2.0– 16050 kHzCircuit506.27508220+ 2.0+ 2.0– 2.0+ 120– 2.0– 560*Complete oscillator includes crystal, capacitors, and resistors.ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎFigure 4. Typical Data for Crystal Oscillator CircuitUnitkHzkΩkΩpFpFppmppmppmppmppmppmhttp://onsemi.com300

MC14521BFREQUENCY DEVIATION (%)8.04.00–4.0–8.0V DD = 15 V10 V5.0 VFigure 5. RC Oscillator StabilityTEST CIRCUITFIGURE 7–12R TC = 56 kΩ, R S = 0, f = 10.15 kHz @ V DD = 10 V, T A = 25°C{C = 1000 pF R–16S = 120 kΩ, f = 7.8 kHz @ V DD = 10 V, T A = 25°C–55 –25 0 25 50 75 100 125T A , AMBIENT TEMPERATURE (°C), DEVICE ONLYf, OSCILLATOR FREQUENCY (kHz)1005020105.02.01.00.50.2f AS A FUNCTIONOF C(R TC = 56 kΩ)(R S = 120 k)V DD = 10 VTEST CIRCUITFIGURE 7f AS A FUNCTIONOF R TC(C = 1000 pF)(R S ≈ 2R TC )0.11.0 k 10 k 100 k 1.0 mR TC , RESISTANCE (OHMS)0.0001 0.001 0.01 0.1C, CAPACITANCE (µF)Figure 6. RC Oscillator Frequency as aFunction of R TC and CR SR TCV DDV DDCIN 1IN 2RV DD V DD ′OUT 1OUT 2Q18Q19Q20Q21Q22Q23Q24V SS V SS ′PULSEGENERATORIN 1IN 2RQ18Q19Q20Q21Q22Q23Q24OUT 1OUT 2V SSV DD ′V SSFigure 7. RC Oscillator CircuitFigure 8. Functional Test Circuithttp://onsemi.com301

MC14521BFUNCTIONAL TEST SEQUENCEInputs Outputs CommentsÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎA test function (see Figure 8) has beenincluded for the reduction of test time required toexercise all 24 counter stages. This test functiondivides the counter into three 8–stage sections,and 255 counts are loaded in each of the8–stage sections in parallel. All flip–flops arenow at a logic “1”. The counter is now returnedto the normal 24–stages in series configuration.One more pulse is entered into Input 2 (In 2)which will cause the counter to ripple from an all“1” state to an all “0” state.Reset In 2 Out 2 V SS ′ V DD ′ Q18 thruQ24Counter is in three 8–stagesections in parallel modeCounter is reset. In 2 and1 0 0 V DD Gnd 0 Out 2 are connectedtogether0 1 1 First “0” to “1” transitionon In 2, Out 2 node.01———01———1 1 100001 0Gnd11V DD11 0 10 1 0255 “0” to “1” transitionsare clocked into this In 2,Out 2 node.The 255th “0” to “1”transition.Counter converted back to24–stages in series mode.Out 2 converts back to anoutput.Counter ripples from an all“1” state to an all “0” stage.http://onsemi.com302

MC14521BLOGIC DIAGRAMV DD5RESET29IN 11 2 STAGES 83 THRU 77OUT 16IN 24OUT 23V SS9 10 STAGES 1611 THRU 1517 18 19 20 21 22 23 2410Q1811Q1912Q2013Q2114Q2215Q231Q24V DD = PIN 16V SS = PIN 8http://onsemi.com303

The MC14526B binary counter is constructed with MOS P–channeland N–channel enhancement mode devices in a monolithic structure.This device is presettable, cascadable, synchronous down counterwith a decoded “0” state output for divide–by–N applications. Insingle stage applications the “0” output is applied to the Preset Enableinput. The Cascade Feedback input allows cascade divide–by–Noperation with no additional gates required. The Inhibit input allowsdisabling of the pulse counting function. Inhibit may also be used as anegative edge clock.This complementary MOS counter can be used in frequencysynthesizers, phase–locked loops, and other frequency divisionapplications requiring low power dissipation and/or high noiseimmunity.• Supply Voltage Range = 3.0 Vdc to 18 Vdc• Logic Edge–Clocked Design — Incremented on Positive Transitionof Clock or Negative Transition of Inhibit• Asynchronous Preset Enable• Capable of Driving Two Low–power TTL Loads or One Low–powerSchottky TTL Load Over the Rated Temperature RangeMAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 2.)Symbol Parameter Value UnitV DD DC Supply Voltage Range –0.5 to +18.0 VV in , V out Input or Output Voltage Range(DC or Transient)–0.5 to V DD + 0.5 VI in , I outP DInput or Output Current(DC or Transient) per PinPower Dissipation,per Package (Note 3.)±10 mA500 mWT A Operating Temperature Range –55 to +125 °CT stg Storage Temperature Range –65 to +150 °CT LLead Temperature(8–Second Soldering)260 °C2. Maximum Ratings are those values beyond which damage to the devicemay occur.3. Temperature Derating:Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 CThis device contains protection circuitry to guard against damage due to highstatic voltages or electric fields. However, precautions must be taken to avoidapplications of any voltage higher than maximum rated voltages to thishigh–impedance circuit. For proper operation, V in and V out should be constrainedto the range V SS (V in or V out ) V DD .Unused inputs must always be tied to an appropriate logic voltage level (e.g.,either V SS or V DD ). Unused outputs must be left open.http://onsemi.comPDIP–16P SUFFIXCASE 648SOIC–16DW SUFFIXCASE 751GSOEIAJ–16F SUFFIXCASE 966A = Assembly LocationWL or L = Wafer LotYY or Y = YearWW or W = Work WeekORDERING INFORMATIONMARKINGDIAGRAMS16Device Package ShippingMC14526BCP PDIP–16 2000/BoxMC14526BDW SOIC–16 47/Rail1MC14526BCPAWLYYWWMC14526BDWR2 SOIC–16 1000/Tape & Reel16114526BAWLYYWW1. For ordering information on the EIAJ version ofthe SOIC packages, please contact your localON Semiconductor representative.161MC14526BAWLYWWMC14526BF SOEIAJ–16 See Note 1.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 3304 Publication Order Number:MC14526B/D

MC14526BPIN ASSIGNMENTQ3116V DDP3215Q2PE314P2INHIBIT413CFP0512“0”CLOCK611P1710RESETV SS89Q1FUNCTION TABLEInputsOutputClock Reset InhibitPresetEnableCascadeFeedback “0”ResultingFunctionX H X L L L Asynchronous reset*XXHHXXHXLHHHAsynchronous resetAsynchronous resetX L X H X L Asynchronous presetL H L X L Decrement inhibitedL L L X L Decrement inhibitedL L L L L No change** (inactive edge)H LL L L No change** (inactive edge)LLLLLDecrement**H L L L L Decrement**X = Don’t CareNOTES:** Output “0” is low when reset goes high only it PE and CF are low.** Output “0” is high when reset is low, only if CF is high and count is 0000.http://onsemi.com305

MC14526BELECTRICAL CHARACTERISTICS (Voltages Referenced to V SS )V DD– 55 C 25 C 125 CÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput VoltageV in = V DD or 0Characteristic Symbol Vdc Min Max Min Typ (4.) Max Min Max Unit“0” LevelV OL 5.01015V 5.0“1” LevelV in = 0 or V DDOH1015Input Voltage“0” Level(V O = 4.5 or 0.5 Vdc)(V O = 9.0 or 1.0 Vdc)(V O = 13.5 or 1.5 Vdc)V IL5.01015———4.959.9514.95———0.050.050.05———1.53.04.0———4.959.9514.95———0005.010152.254.506.750.050.050.05———1.53.04.0———4.959.9514.95———0.050.050.05———1.53.04.0VdcVdcVdc(V O = 0.5 or 4.5 Vdc)(V O = 1.0 or 9.0 Vdc)(V O = 1.5 or 13.5 Vdc)“1” LevelV IH5.010153.57.011———3.57.0112.755.508.25———3.57.011———VdcOutput Drive Current(V OH = 2.5 Vdc) Source(V OH = 4.6 Vdc)(V OH = 9.5 Vdc)(V OH = 13.5 Vdc)I OH5.05.01015– 3.0– 0.64– 1.6– 4.2————– 2.4– 0.51– 1.3– 3.4– 4.2– 0.88– 2.25– 8.8————– 1.7– 0.36– 0.9– 2.4————mAdc(V OL = 0.4 Vdc) Sink(V OL = 0.5 Vdc)(V OL = 1.5 Vdc)I OL 5.010150.641.64.2Input Current I in 15 — ± 0.1 — ±0.00001 ± 0.1 — ± 1.0 µAdcInput Capacitance(V in = 0)———0.511.33.40.882.258.8C in — — — — 5.0 7.5 — — pF———0.360.92.4———mAdcQuiescent Current(Per Package)Total Supply Current (5.) (6.)(Dynamic plus Quiescent,Per Package)(C L = 50 pF on all outputs, allbuffers switching)I DD 5.01015I T 5.01015———5.01020———0.0050.0100.0155.01020I T = (1.7 µA/kHz) f + I DDI T = (3.4 µA/kHz) f + I DDI T = (5.1 µA/kHz) f + I DD4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.5. The formulas given are for the typical characteristics only at 25 C.6. To calculate total supply current at loads other than 50 pF:I T (C L ) = I T (50 pF) + (C L – 50) Vfkwhere: I T is in µA (per package), C L in pF, V = (V DD – V SS ) in volts, f in kHz is input frequency, and k = 0.001.———150300600µAdcµAdchttp://onsemi.com306

MC14526BSWITCHING CHARACTERISTICS (7.) (C L = 50 pF, T A = 25 C)Characteristic Symbol V DD Min Typ (8.) Max UnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Rise and Fall Timet TLH , t THL = (1.5 ns/pF) C L + 25 nst TLH , t THL = (0.75 ns/pF) C L + 12.5 nst TLH , t THL = (0.55 ns/pF) C L + 9.5 nsPropagation Delay Time (Inhibit Used as NegativeEdge Clock)Clock or Inhibit to Qt PLH , t PHL = (1.7 ns/pF) C L + 465 nst PLH , t PHL = (0.66 ns/pF) C L + 197 nst PLH , t PHL = (0.5 ns/pF) C L + 135 nsClock or Inhibit to “0”t PLH , t PHL = (1.7 ns/pF) C L + 155 nst PLH , t PHL = (0.66 ns/pF) C L + 87 nst PLH , t PHL = (0.5 ns/pF) C L + 65 nst TLH ,t THL(Figures 4, 5)t PLH ,t PHL(Figures 4, 5, 6)5.010155.010155.01015—————————1005040550225160240130100200100801100450320480260200nsnsPropagation Delay TimePn to QPropagation Delay TimeReset to QPropagation Delay TimePreset Enable to “0”Clock or Inhibit Pulse WidthClock Pulse Frequency (with PE = low)t PLH ,t PHL(Figures 4, 7)t PHL(Figure 8)t PHL ,t PLH(Figures 4, 9)t w(Figures 5, 6)f max(Figures 4, 5, 6)Clock or Inhibit Rise and Fall Time t r ,t f(Figures 5, 6)Setup TimePn to Preset EnableHold TimePreset Enable to PnPreset Enable Pulse WidthReset Pulse WidthReset Removal Timet su(Figure 10)t h(Figure 10)t w(Figure 10)t w(Figure 8)t rem(Figure 8)7. The formulas given are for the typical characteristics only at 25 C.8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.5.010155.010155.010155.010155.010155.010155.010155.010155.010155.010155.01015—————————25010080——————90504030303025010080350250200102030260120100250110802201008012550402.05.06.6———401510– 15– 501255040175125100– 110– 30– 20520240200500220160440200160———1.53.04.01554———————————————nsnsnsnsMHzµsnsnsnsnsnshttp://onsemi.com307

MC14526BCFPEP0P1P2P3RESETINHIBITCLOCKQ0Q1Q2Q3“0”V SSV DD = –V GSV OHI OHEXTERNALPOWERSUPPLYCFPEP0P1P2P3RESETINHIBITCLOCKQ0Q1Q2Q3“0”V SSV DD = V GSV OLI OLEXTERNALPOWERSUPPLYFigure 1. Typical Output SourceCharacteristics Test CircuitFigure 2. Typical Output SinkCharacteristics Test CircuitV DDCF Q0PEP0 Q1P1P2 Q2P3C LRESET Q3C LINHIBITC LCLOCK “0”C LV SS C LPULSEGENERATOR 20 ns 20 nsCLOCK90%V DD50%10%VVARIABLESSWIDTH 50% DUTY CYCLEFigure 3. Power DissipationDEVICEUNDERTESTQ or “0”Figure 4. Test CircuitTEST POINT*Includes all probe and jig capacitance.C L *http://onsemi.com308

MC14526BSWITCHING WAVEFORMSCLOCKANY QOR “0”ANY P90%50%10%90%50%10%90%50%10%t f t rt w t wt ft rt ft rV DD90%INHIBIT 50%V SS10%1/f max 1/f maxt PLHt PHLt PLHANY Q90%OR “0” 50%10%t TLHt THLt TLHt wRESET50%Figure 5. Figure 6.V DDV SSANY Q50%t PHLt PHLt THLV DDV SSV DDV SSt PLHt PHLt remANY Q50%CLOCK50%V DDV SSFigure 7. Figure 8.VALIDt r t fV DDV DDPRESETENABLE90%50%10%GNDANY P50%t sut hV SS“0”t PHL50%t PLHPRESETENABLE50%V DDV SSt wFigure 9. Figure 10.http://onsemi.com309

MC14526BPIN DESCRIPTIONSPreset Enable (Pin 3) — If Reset is low, a high level onthe Preset Enable input asynchronously loads the counterwith the programmed values on P0, P1, P2, and P3.Inhibit (Pin 4) — A high level on the Inhibit input pre–vents the Clock from decrementing the counter. With Clock(pin 6) held high, Inhibit may be used as a negative edgeclock input.Clock (Pin 6) — The counter decrements by one for eachrising edge of Clock. See the Function Table for levelrequirements on the other inputs.Reset (Pin 10) — A high level on Reset asynchronouslyforces Q0, Q1, Q2, and Q3 low and, if Cascade Feedback ishigh, causes the “0” output to go high.“0” (Pin 12) — The “0” (Zero) output issues a pulse oneclock period wide when the counter reaches terminal count(Q0 = Q1 = Q2 = Q3 = low) if Cascade Feedback is high andPreset Enable is low. When presetting the counter to a valueother than all zeroes, the “0” output is valid after the risingedge of Preset Enable (when Cascade Feedback is high). Seethe Function Table.Cascade Feedback (Pin 13) — If the Cascade Feedbackinput is high, a high level is generated at the “0” output whenthe count is all zeroes. If Cascade Feedback is low, the “0”output depends on the Preset Enable input level. See theFunction Table.P0, P1, P2, P3 (Pins 5, 11, 14, 2) — These are the presetdata inputs. P0 is the LSB.Q0, Q1, Q2, Q3 (Pins 7, 9, 15, 1) — These are thesynchronous counter outputs. Q0 is the LSB.V SS (Pin 8) — The most negative power supply potential.This pin is usually ground.V DD (Pin 16) — The most positive power supplypotential. V DD may range from 3 to 18 V with respect to V SS .STATE DIAGRAMMC14526B0123415514613712 11 10 9 8http://onsemi.com310

MC14526BMC14526B LOGIC DIAGRAM (Binary Down Counter)P0 Q0 P1 Q1 P2 Q2 P3 Q35 7 11 9 14 15 2 1DRDR QCCT PE Q T PE QV DDV DDDR QCT PE QDR QCT PE QCF13PEINHIBITCLOCKRESET3461012“0”http://onsemi.com311

MC14526BAPPLICATIONS INFORMATIONDivide–By–N, Single StageFigure 11 shows a single stage divide–by–N application.To initialize counting a number, N is set on the parallelinputs (P0, P1, P2, and P3) and reset is taken highasynchronously. A zero is forced into the master and slaveof each bit and, at the same time, the “0” output goes high.Because Preset Enable is tied to the “0” output, preset isenabled. Reset must be released while the Clock is high sothe slaves of each bit may receive N before the Clock goeslow. When the Clock goes low and Reset is low, the “0”output goes low (if P0 through P3 are unequal to zero).The counter downcounts with each rising edge of theClock. When the counter reaches the zero state, an outputpulse occurs on “0” which presets N. The propagation delaysfrom the Clock’s rising and falling edges to the “0” output’srising and falling edges are about equal, making the “0”output pulse approximately equal to that of the Clock pulse.The Inhibit pin may be used to stop pulse counting. Whenthis pin is taken high, decrementing is inhibited.Cascaded, Presettable Divide–By–NFigure 12 shows a three stage cascade application. TakingReset high loads N. Only the first stage’s Reset pin (leastsignificant counter) must be taken high to cause the presetfor all stages, but all pins could be tied together, as shown.When the first stage’s Reset pin goes high, the “0” outputis latched in a high state. Reset must be released while Clockis high and time allowed for Preset Enable to load N into allstages before Clock goes low.When Preset Enable is high and Clock is low, time mustbe allowed for the zero digits to propagate a CascadeFeedback to the first non–zero stage. Worst case is from themost significant bit (M.S.B.) to the L.S.B., when the L.S.B.is equal to one (i.e. N = 1).After N is loaded, each stage counts down to zero witheach rising edge of Clock. When any stage reaches zero andthe leading stages (more significant bits) are zero, the “0”output goes high and feeds back to the preceding stage.When all stages are zero, the Preset Enable automaticallyloads N while the Clock is high and the cycle is renewed.f inNV DDV SSP0P1P2P3CFRESETINHIBITCLOCKQ0Q1Q2Q3“0”BUFFERf inNPEFigure 11. ÷ N CounterLSBN0 N1 N2 N3N4 N5 N6 N7MSBN8 N9 N10 N11f inV SSV DDLOADP0 P1 P2 P3 Q0 Q1 Q2 Q3CLOCKCFINHIBITRESET “0” PEV SS RESET “0” PEP0 P1 P2 P3 Q0 Q1 Q2 Q3CLOCKINHIBITCFV SSP0 P1 P2 P3CLOCKQ0 Q1 Q2 Q3INHIBITRESET “0” PECFV DDN10 KΩV SSBUFFERf inNFigure 12. 3 Stages Cascadedhttp://onsemi.com312

The MC14528B is a dual, retriggerable, resettable monostablemultivibrator. It may be triggered from either edge of an input pulse,and produces an output pulse over a wide range of widths, the durationof which is determined by the external timing components, C X andR X .• Separate Reset Available• Diode Protection on All Inputs• Triggerable from Leading or Trailing Edge Pulse• Supply Voltage Range = 3.0 Vdc to 18 Vdc• Capable of Driving Two Low–power TTL Loads or One Low–powerSchottky TTL Load Over the Rated Temperature Range• Pin–for–Pin Replacement with the MC14538BMAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 2.)Symbol Parameter Value UnitV DD DC Supply Voltage Range –0.5 to +18.0 VV in , V out Input or Output Voltage Range(DC or Transient)–0.5 to V DD + 0.5 VI in , I outP DInput or Output Current(DC or Transient) per PinPower Dissipation,per Package (Note 3.)±10 mA500 mWT A Ambient Temperature Range –55 to +125 °CT stg Storage Temperature Range –65 to +150 °CT LLead Temperature(8–Second Soldering)260 °C2. Maximum Ratings are those values beyond which damage to the devicemay occur.3. Temperature Derating:Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 CThis device contains protection circuitry to guard against damage due to highstatic voltages or electric fields. However, precautions must be taken to avoidapplications of any voltage higher than maximum rated voltages to thishigh–impedance circuit. For proper operation, V in and V out should be constrainedto the range V SS (V in or V out ) V DD .Unused inputs must always be tied to an appropriate logic voltage level (e.g.,either V SS or V DD ). Unused outputs must be left open.http://onsemi.comPDIP–16P SUFFIXCASE 648SOIC–16D SUFFIXCASE 751BSOEIAJ–16F SUFFIXCASE 966A = Assembly LocationWL or L = Wafer LotYY or Y = YearWW or W = Work WeekORDERING INFORMATIONMARKINGDIAGRAMSDevice Package ShippingMC14528BCP PDIP–16 2000/BoxMC14528BD SOIC–16 48/RailMC14528BDR2 SOIC–16 2500/Tape & Reel1. For ordering information on the EIAJ version ofthe SOIC packages, please contact your localON Semiconductor representative.161161161MC14528BCPAWLYYWW14528BAWLYWWMC14528BAWLYWWMC14528BF SOEIAJ–16 See Note 1.MC14528BFEL SOEIAJ–16 See Note 1.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 3313 Publication Order Number:MC14528B/D

MC14528BPIN ASSIGNMENTV SS116V DDC X 1/R X 1215V SSRESET 1314C X 2/R X 2A1413RESET 2B1512A2Q1611B2Q1710Q2V SS89Q2BLOCK DIAGRAMC X 1R X 1V DD1 2A1B14567Q1Q1RESET 13C X 2 R X 2V DD1514A2B21211109Q2Q2RESET 213V DD = PIN 16V SS = PIN 1, PIN 8, PIN 15R X AND C X ARE EXTERNAL COMPONENTSONE–SHOT SELECTION GUIDE100 ns 1 s 10 s 100 s 1 ms 10 ms 100 ms 1 s 10 sMC14528BMC14536BMC14538BMC14541BMC4538A*23 HR5 MIN.*LIMITED OPERATING VOLTAGE (2–6 V)TOTAL OUTPUT PULSE WIDTH RANGERECOMMENDED PULSE WIDTH RANGEhttp://onsemi.com314

MC14528BELECTRICAL CHARACTERISTICS (Voltages Referenced to V SS )V DD– 55 C 25 C 125 CÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput VoltageV in = V DD or 0Characteristic Symbol Vdc Min Max Min Typ (4.) Max Min Max Unit“0” LevelV OL 5.01015V 5.0“1” LevelV in = 0 or V DDOH1015Input Voltage“0” Level(V O = 4.5 or 0.5 Vdc)(V O = 9.0 or 1.0 Vdc)(V O = 13.5 or 1.5 Vdc)V IL5.01015———4.959.9514.95———0.050.050.05———1.53.04.0———4.959.9514.95———0005.010152.254.506.750.050.050.05———1.53.04.0———4.959.9514.95———0.050.050.05———1.53.04.0VdcVdcVdc(V O = 0.5 or 4.5 Vdc)(V O = 1.0 or 9.0 Vdc)(V O = 1.5 or 13.5 Vdc)“1” LevelV IH5.010153.57.011———3.57.0112.755.508.25———3.57.011———VdcOutput Drive Current(V OH = 2.5 Vdc) Source(V OH = 4.6 Vdc)(V OH = 9.5 Vdc)(V OH = 13.5 Vdc)I OH5.05.01015– 1.2– 0.64– 1.6– 4.2————– 1.0– 0.51– 1.3– 3.4– 1.7– 0.88– 2.25– 8.8————– 0.7– 0.36– 0.9– 2.4————mAdc(V OL = 0.4 Vdc) Sink(V OL = 0.5 Vdc)(V OL = 1.5 Vdc)I OL5.010150.641.64.2Input Current I in 15 — ± 0.1 — ±0.00001 ± 0.1 — ± 1.0 µAdcInput Capacitance(V in = 0)———0.511.33.40.882.258.8C in — — — — 5.0 7.5 — — pF———0.360.92.4———mAdcQuiescent Current(Per Package)I DD 5.01015———5.01020———0.0050.0100.015Total Supply Current at anexternal load Capacitance (C L )and at external timingcapacitance (C X ), use theformula — (5.) I T — I T (C L , C X ) = [(C L + 0.36C X )V DD f + 2x10 –8R X C X (V –2 DD ) 2 f] x 10 –3where: I T in µA (per circuit), C L and C X in pF, R X in megohms,V DD in Vdc, f in kHz is input frequency.4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.5. The formulas given are for the typical characteristics only at 25 C.5.01020———150300600µAdcµAdchttp://onsemi.com315

MC14528BSWITCHING CHARACTERISTICS (8.) (C L = 50 pF, T A = 25 C)CharacteristicOutput Rise and Fall Timet TLH , t THL = (1.5 ns/pF) C L + 25 nst TLH , t THL = (0.75 ns/pF) C L + 12.5 nst TLH , t THL = (0.55 ns/pF) C L + 9.5 nsTurn–Off, Turn–On Delay Time — A or B to Q or Qt PLH , t PHL = (1.7 ns/pF) C L + 240 nst PLH , t PHL = (0.66 ns/pF) C L + 87 nst PLH , t PHL = (0.5 ns/pF) C L + 65 nsTurn–Off, Turn–On Delay Time — A or B to Q or Qt PLH , t PHL = (1.7 ns/pF) C L + 620 nst PLH , t PHL = (0.66 ns/pF) C L + 257 nst PLH , t PHL = (0.5 ns/pF) C L + 185 nsSymbolC XpFR XkΩt TLH , — —t THLt PLH , 15 5.0t PHLt PLH , 1000 10t PHLInput Pulse Width — A or B t WH 15 5.0 5.01015Output Pulse Width — Q or Q(For C X < 0.01 µF use graph forappropriate V DD level.)V DDVdc Min Typ (9.) Max Unitns5.010155.010155.01015t WL 1000 10 5.01015t W 15 5.0 5.01015Output Pulse Width — Q or Qt W 10,000 10 5.0t W = 0.2 R X C X Ln [V DD – V SS ]) (6.) 15(For C X > 0.01 µF use formula:10Pulse Width Match between Circuits in the samepackaget1 – t2 10,000 10 5.0101515 5.0 5.0Reset Propagation Delay — Reset to Q or Q t PLH ,t PHL 10151000 10 5.01015Retrigger Time t rr 15 5.0 5.010151000 10 5.01015External Timing Resistance R X — — — 5.0 — 1000 kΩExternal Timing Capacitance C X — — — No Limits (7.) µF6. R X is in Ohms, C X is in farads, V DD and V SS in volts, PW out in seconds.7. If C X > 15 µF, Use Discharge Protection Diode D X , per Fig. 9.8. The formulas given are for the typical characteristics only at 25 C.9. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.—————————1507555——————151015—————————0000001005040325120907052902107030307030305503503003050556.08.08.032590601000300250——————20010080650240180————————————459095253535600225170—————————nsnsnsnsnsµs%nsnsnsnshttp://onsemi.com316

MC14528BInputsFUNCTION TABLEOutputsReset A B Q QHHLHH L Not TriggeredH H Not TriggeredH L, H, H Not TriggeredH L L, H, Not TriggeredL X X L HX X Not TriggeredV DD16V DD16I OLABRESET8Q OPENA QV OLBV OHQRESET Q OPENV SSI OH8 V SSFigure 1. Output Source Current Test CircuitFigure 2. Output Sink Current Test CircuitV DDDUTY CYCLE = 50%500 pFI D0.1 FCERAMICV inR X R X ′C XC X ′20 ns 20 nsBQV in 10%C LA90%RESETQC LA′Q′C LB′Q′C LRESET′V DD0 VV SSFigure 3. Power Dissipation Test Circuit and Waveformshttp://onsemi.com317

MC14528BC XR XV DDR X ′C X ′*C X = 15 pF*C L = 15 pFR X = 5.0 kINPUT CONNECTIONSCharacteristics Reset A Bt PLH , t PHL , t TLH , t THL V DD PG1 V DDt WÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPULSEGENERATORPULSEGENERATORPULSEGENERATORABRESETA′B′RESET′V SSQQQ′Q′C Lt PLH , t PHL , t TLH , t THL V DD V SS PG2t Wt PLH(R) , t PHL(R) , t W PG3 PG1 PG2C L*Includes capacitance of probes, PG1 =C LNOTE: AC test waveforms forPG2 =C Lwiring, and fixture parasitic.PG1, PG2, and PG3 onnext page.PG3 =Figure 4. AC Test CircuitA50%90%10%50%V DDV SSB50%t WLt TLH t THLt THL90%10%t TLHV DDV SSRESETQ50% 50%t THL t TLH90%50%10%t THL t WLt PLH t TLHt PHL90%50% 10%50%t rrV DDV SSV OHV OLt PHLt WHt TLH t THLt PHLt PHLQ50% 50%90%50%10%50%V OHV OLFigure 5. AC Test Waveformst WFigure 6. Pulse Width versus C X100,000t W , PULSE WIDTH ( s)1000100R X = 100 k10R X = 10 k1.00.11015 V10 V5.0 VV DD = 15 V10 V15 V5.0 V10 V5.0 VR X = 5.0 k1001000 10,000C X , EXTERNAL CAPACITANCE (pF)15 V10 V5.0 Vhttp://onsemi.com318

MC14528BTYPICAL APPLICATIONSC xR xC xR xV DDV DDRISING EDGETRIGGERV DDABQQRESETV DDRISING EDGETRIGGERABQQRESETV DDC xR xC xR xV DDV DDFALLING EDGETRIGGERABQQRESETV DDFALLING EDGETRIGGERABQQRESETV DDFigure 7. RetriggerableMonostables CircuitryFigure 8. Non–RetriggerableMonostables CircuitryD XC xR xV DDNC1, 15 2, 14V DDQQRESETV DDV DDNCVDDAQV DDBQ NCRESETFigure 9. Use of a Diode to LimitPower Down Current SurgeFigure 10. Connection of Unused Sectionshttp://onsemi.com319

The MC14532B is constructed with complementary MOS (CMOS)enhancement mode devices. The primary function of a priorityencoder is to provide a binary address for the active input with thehighest priority. Eight data inputs (D0 thru D7) and an enable input(E in) are provided. Five outputs are available, three are address outputs(Q0 thru Q2), one group select (GS) and one enable output (E out ).• Diode Protection on All Inputs• Supply Voltage Range = 3.0 Vdc to 18 Vdc• Capable of Driving Two Low–power TTL Loads or One Low–PowerSchottky TTL Load over the Rated Temperature RangeMAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 2.)Symbol Parameter Value UnitV DD DC Supply Voltage Range –0.5 to +18.0 VV in , V out Input or Output Voltage Range(DC or Transient)–0.5 to V DD + 0.5 VI in , I outP DInput or Output Current(DC or Transient) per PinPower Dissipation,per Package (Note 3.)±10 mA500 mWT A Ambient Temperature Range –55 to +125 °CT stg Storage Temperature Range –65 to +150 °CT LLead Temperature(8–Second Soldering)260 °C2. Maximum Ratings are those values beyond which damage to the devicemay occur.3. Temperature Derating:Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 CThis device contains protection circuitry to guard against damage due to highstatic voltages or electric fields. However, precautions must be taken to avoidapplications of any voltage higher than maximum rated voltages to thishigh–impedance circuit. For proper operation, V in and V out should be constrainedto the range V SS (V in or V out ) V DD .Unused inputs must always be tied to an appropriate logic voltage level (e.g.,either V SS or V DD ). Unused outputs must be left open.http://onsemi.comPDIP–16P SUFFIXCASE 648SOIC–16D SUFFIXCASE 751BSOEIAJ–16F SUFFIXCASE 966A = Assembly LocationWL or L = Wafer LotYY or Y = YearWW or W = Work WeekORDERING INFORMATIONMARKINGDIAGRAMSDevice Package ShippingMC14532BCP PDIP–16 2000/BoxMC14532BD SOIC–16 48/RailMC14532BDR2 SOIC–16 2500/Tape & Reel161161161MC14532BCPAWLYYWW14532BAWLYWWMC14532BAWLYWWMC14532BF SOEIAJ–16 See Note 1.MC14532BFEL SOEIAJ–16 See Note 1.MC14532BFR1 SOEIAJ–16 See Note 1.1. For ordering information on the EIAJ version ofthe SOIC packages, please contact your localON Semiconductor representative.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 3320 Publication Order Number:MC14532B/D

MC14532BPIN ASSIGNMENTD4116V DDD5215E outD6314GSD7413D3512D2E inTRUTH TABLEQ2611D1Q1710D0V SS89Q0InputOutputE in D7 D6 D5 D4 D3 D2 D1 D0 GS Q2 Q1 Q0 E out0 X X X X X X X X 0 0 0 0 01 0 0 0 0 0 0 0 0 0 0 0 0 11 1 X X X X X X X 1 1 1 1 01 0 1 X X X X X X 1 1 1 0 01 0 0 1 X X X X X 1 1 0 1 01 0 0 0 1 X X X X 1 1 0 0 01 0 0 0 0 1 X X X 1 0 1 1 01 0 0 0 0 0 1 X X 1 0 1 0 01 0 0 0 0 0 0 1 X 1 0 0 1 01 0 0 0 0 0 0 0 1 1 0 0 0 0X = Don’t Carehttp://onsemi.com321

MC14532BELECTRICAL CHARACTERISTICS (Voltages Referenced to V SS )– 55 C 25 C 125 CV DDVdc Min Max Min Typ (4.) Max Min Max UnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCharacteristicOutput VoltageV in = V DD or 0“0” LevelSymbolV OL 5.01015V 5.0“1” LevelV in = 0 or V DDOH1015Input Voltage“0” Level(V O = 4.5 or 0.5 Vdc)(V O = 9.0 or 1.0 Vdc)(V O = 13.5 or 1.5 Vdc)V IL5.01015———4.959.9514.95———0.050.050.05———1.53.04.0———4.959.9514.95———0005.010152.254.506.750.050.050.05———1.53.04.0———4.959.9514.95———0.050.050.05———1.53.04.0VdcVdcVdc(V O = 0.5 or 4.5 Vdc)(V O = 1.0 or 9.0 Vdc)(V O = 1.5 or 13.5 Vdc)“1” LevelV IH5.010153.57.011———3.57.0112.755.508.25———3.57.011———VdcOutput Drive Current(V OH = 2.5 Vdc) Source(V OH = 4.6 Vdc)(V OH = 9.5 Vdc)(V OH = 13.5 Vdc)I OH5.05.01015– 3.0– 0.64– 1.6– 4.2————– 2.4– 0.51– 1.3– 3.4– 4.2– 0.88– 2.25– 8.8————– 1.7– 0.36– 0.9– 2.4————mAdc(V OL = 0.4 Vdc) Sink(V OL = 0.5 Vdc)(V OL = 1.5 Vdc)I OL 5.010150.641.64.2Input Current I in 15 — ± 0.1 — ±0.00001 ± 0.1 — ± 1.0 µAdcInput Capacitance(V in = 0)———0.511.33.40.882.258.8C in — — — — 5.0 7.5 — — pF———0.360.92.4———mAdcQuiescent Current(Per Package)Total Supply Current (5.) (6.)(Dynamic plus Quiescent,Per Package)(C L = 50 pF on all outputs, allbuffers switching)I DD 5.01015I T 5.01015———5.01020———0.0050.0100.0155.01020I T = (1.74 µA/kHz) f + I DDI T = (3.65 µA/kHz) f + I DDI T = (5.73 µA/kHz) f + I DD4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.5. The formulas given are for the typical characteristics only at 25 C.6. To calculate total supply current at loads other than 50 pF:I T (C L ) = I T (50 pF) + (C L – 50) Vfkwhere: I T is in µA (per package), C L in pF, V = (V DD – V SS ) in volts, f in kHz is input frequency, and k = 0.005.———150300600µAdcµAdchttp://onsemi.com322

MC14532BSWITCHING CHARACTERISTICS (7.) (C L = 50 pF, T A = 25 C)Characteristic Symbol V DD Min Typ (8.) Max UnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Rise and Fall Timet TLH , t THL = (1.5 ns/pF) C L + 25 nst TLH , t THL = (0.75 ns/pF) C L + 12.5 nst TLH , t THL = (0.55 ns/pF) C L + 9.5 nsPropagation Delay Time — E in to E outt PLH , t PHL = (1.7 ns/pF) C L + 120 nst PLH , t PHL = (0.66 ns/pF) C L + 77 nst PLH , t PHL = (0.5 ns/pF) C L + 55 nsPropagation Delay Time — E in to GSt PLH , t PHL = (1.7 ns/pF) C L + 90 nst PLH , t PHL = (0.66 ns/pF) C L 57 nst PLH , t PHL = (0.5 ns/pF) C L + 40 nsPropagation Delay Time — E in to Q nt PLH , t PHL = (1.7 ns/pF) C L + 195 nst PLH , t PHL = (0.66 ns/pF) C L + 107 nst PLH , t PHL = (0.5 ns/pF) C L + 75 nsPropagation Delay Time — D n to Q nt PLH , t PHL = (1.7 ns/pF) C L + 265 nst PLH , t PHL = (0.66 ns/pF) C L + 137 nst PLH , t PHL = (0.5 ns/pF) C L + 85 nsPropagation Delay Time — D n to GSt PLH , t PHL = (1.7 ns/pF) C L + 195 nst PLH , t PHL = (0.66 ns/pF) C L + 107 nst PLH , t PHL = (0.5 ns/pF) C L + 75 nst TLH ,t THL 5.01015t PLH ,t PHL 5.01015t PLH ,t PHL 5.01015t PHL ,t PLH 5.01015t PLH ,t PHL 5.01015t PLH ,t PHL 5.010157. The formulas given are for the typical characteristics only at 25 C.8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.——————————————————100504020511080175906528014010030017011028014010020010080410220160350180130560280200600340220560280200nsnsnsnsnsnsE inD0D1E outV outPULSESWITCHMATRIXD2D3D4D5D6D7Q0Q1V GS = V DDV GS = – V DDVOutputDS = V out V DS = V out – V DDSink Current Source CurrentUnderTest D0 thru D7 E in D0 thru D6 D7 E inE out X 0 0 0 1Q0 X 0 0 1 1Q1Q2XX00001111GS X 0 0 1 1Q2GSI DEXTERNALPOWERSUPPLY500 µFGENERATOR(f o )E inD0D1D2D3D4D5D6D7V DDI D0.01 µFE outQ0C LQ1C LQ2C LGSC LV SSC LFigure 1. Typical Sink and SourceCurrent CharacteristicsFigure 2. Typical Power Dissipation Test Circuithttp://onsemi.com323

MC14532BPROGRAMMABLEPULSEGENERATORE inD0D1D2D3D4D5D6D7V DDV SSE outQ0Q1Q2GSC LC LC LC LC LNOTE: Input rise and fall times are 20 nsD0PINNO.1050%D11150%D21250%D31350%D4150%D5250%D6350%D7450%E inE outGS51514t PLH90%50%10%t TLHt TLHt PHLt THLt PLHt PLHt PLH50%t PHL90%50%10%t THLt PLHt PHL t PHL t PHLQ0Q1Q2976t PLHt PLHt PLHt PLHt PHLt TLHt TLHt TLHt PHL90%50%10%t THLt PHL90%50%10%t THLt PHL90%50%10%t THLFigure 3. AC Test Circuit and Waveformshttp://onsemi.com324

MC14532BLOGIC DIAGRAM(Positive Logic)LOGIC EQUATIONS10D0E out = E in D0 D1 D2 D3 D4 D5 D6 D7Q0 = E in (D1 D2 D4 D6 + D3 D4 D6 + D5 D6 + D7)Q1 = E in (D2 D4 D5 + D3 D4 D5 + D6 + D7)Q2 = E in (D4 + D5 + D6 + D7)GS = E in (D0 + D1 + D2 + D3 + D4 + 05 + D6 + D7)11D1912D213D31D472D53D64D765E inQ0Q1Q214GS15E outhttp://onsemi.com325

MC14532BD15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0V DD E in E out E in E outE out = “1”WITH D in = “0”GSQ2 Q1 Q0Q2 Q1 Q03/4 MC14071BQ3Q2Q1Q0Figure 4. Two MC14532B’s Cascaded for 4–Bit OutputV DDV SSDIGITAL TO ANALOG CONVERSIONThe digital eight–bit word to be converted is applied to theinputs of the MC14512 with the most significant bit atX7 and the least significant bit at X0. A clock input of up to2.5 MHz (at V DD = 10 V) is applied to the MC14520B.A compromise between I bias for the MC1710 and ∆Rbetween N and P–channel outputs gives a value of R of33 k ohms. In order to filter out the switching frequencies,RC should be about 1.0 ms (if R = 33 k ohms, C 0.03 µF).The analog 3.0 dB bandwidth would then be dc to 1.0 kHz.ANALOG TO DIGITAL CONVERSIONAn analog signal is applied to the analog input of theMC1710. A digital eight–bit word known to represent a digitizedlevel less than the analog input is applied to theMC14512 as in the D to A conversion. The word is incrementedat rates sufficient to allow steady state to be reachedbetween incrementations (i.e. 3.0 ms). The output of theMC1710 will change when the digital input represents thefirst digitized level above the analog input. This word is thedigital representation of the analog word.CLOCKINPUTV DDC E R C E R1/2 MC14520B 1/2 MC14520BQ1 Q2 Q3 Q4 Q1 Q2 Q3 Q4E inD0 D1 D2 D3 D4 D5 D6 D7STOPWORDINCREMENTATIONQ2 Q1 Q0X7 X6 X5 X4 X3 X2 X1 X0AB MC14512CZMC1710DIGITAL INPUT/OUTPUT8–BIT WORDTO BE CONVERTEDRCANALOGOUTPUTANALOGINPUTFigure 5. Digital to Analog and Analog to Digital Converterhttp://onsemi.com326

The MC14536B programmable timer is a 24–stage binary ripplecounter with 16 stages selectable by a binary code. Provisions for anon–chip RC oscillator or an external clock are provided. An on–chipmonostable circuit incorporating a pulse–type output has beenincluded. By selecting the appropriate counter stage in conjunctionwith the appropriate input clock frequency, a variety of timing can beachieved.• 24 Flip–Flop Stages — Will Count From 2 0 to 2 24• Last 16 Stages Selectable By Four–Bit Select Code• 8–Bypass Input Allows Bypassing of First Eight Stages• Set and Reset Inputs• Clock Inhibit and Oscillator Inhibit Inputs• On–Chip RC Oscillator Provisions• On–Chip Monostable Output Provisions• Clock Conditioning Circuit Permits Operation With Very Long Riseand Fall Times• Test Mode Allows Fast Test Sequence• Supply Voltage Range = 3.0 Vdc to 18 Vdc• Capable of Driving Two Low–power TTL Loads or One Low–powerSchottky TTL Load Over the Rated Temperature RangeMAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 2.)Symbol Parameter Value UnitV DD DC Supply Voltage Range –0.5 to +18.0 VV in , V out Input or Output Voltage Range(DC or Transient)–0.5 to V DD + 0.5 Vhttp://onsemi.comPDIP–16P SUFFIXCASE 648SOIC–16DW SUFFIXCASE 751GSOEIAJ–16F SUFFIXCASE 966A = Assembly LocationWL or L = Wafer LotYY or Y = YearWW or W = Work WeekMARKINGDIAGRAMS161MC14536BCPAWLYYWW16116114536BAWLYYWWMC14536BAWLYWWI in , I outP DInput or Output Current(DC or Transient) per PinPower Dissipation,per Package (Note 3.)±10 mA500 mWORDERING INFORMATIONDevice Package ShippingT A Operating Temperature Range –55 to +125 °CT stg Storage Temperature Range –65 to +150 °CT LLead Temperature(8–Second Soldering)260 °C2. Maximum Ratings are those values beyond which damage to the devicemay occur.3. Temperature Derating:Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 CThis device contains protection circuitry to guard against damage due to highstatic voltages or electric fields. However, precautions must be taken to avoidapplications of any voltage higher than maximum rated voltages to thishigh–impedance circuit. For proper operation, V in and V out should be constrainedto the range V SS (V in or V out ) V DD .Unused inputs must always be tied to an appropriate logic voltage level (e.g.,either V SS or V DD ). Unused outputs must be left open.MC14536BCP PDIP–16 2000/BoxMC14536BDW SOIC–16 47/RailMC14536BDWR2 SOIC–16 1000/Tape & ReelMC14536BF SOEIAJ–16 See Note 1.1. For ordering information on the EIAJ version ofthe SOIC packages, please contact your localON Semiconductor representative.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 5327 Publication Order Number:MC14536B/D

MC14536BPIN ASSIGNMENTSET116V DDRESET215MONO ININ 1314OSC INHOUT 1413DECODEOUT 2512D8–BYPASS611CCLOCK INH710BV SS89ABLOCK DIAGRAMCLOCK INH. RESET SET 8 BYPASS7 2 1 6OSC. INHIBIT 14IN 13STAGES1 THRU 8Q9Q10Q11Q12Q13Q14STAGES 9 THRU 24Q Q Q Q15 16 17 18Q19Q20Q21Q22Q23Q244OUT 15OUT 2V DD = PIN 16V SS = PIN 8A 9B 10C 11D 12MONO–IN 15DECODERMONOSTABLEMULTIVIBRATOR13DECODEOUThttp://onsemi.com328

MC14536BELECTRICAL CHARACTERISTICS (Voltages Referenced to V SS )– 55 C 25 C 125 CV DDVdc Min Max Min Typ (4.) Max Min Max UnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCharacteristicOutput VoltageV in = V DD or 0“0” LevelSymbolV OL 5.01015V 5.0“1” LevelV in = 0 or V DDOH1015Input Voltage“0” Level(V O = 4.5 or 0.5 Vdc)(V O = 9.0 or 1.0 Vdc)(V O = 13.5 or 1.5 Vdc)(V O = 0.5 or 4.5 Vdc)(V O = 1.0 or 9.0 Vdc)(V O = 1.5 or 13.5 Vdc)“1” LevelOutput Drive Current(V OH = 2.5 Vdc) Source(V OH = 4.6 Vdc) Pins 4 & 5(V OH = 9.5 Vdc)(V OH = 13.5 Vdc)(V OH = 2.5 Vdc) Source(V OH = 4.6 Vdc) Pin 13(V OH = 9.5 Vdc)(V OH = 13.5 Vdc)(V OL = 0.4 Vdc) Sink(V OL = 0.5 Vdc)(V OL = 1.5 Vdc)V IL5.01015V IH5.01015I OH5.05.010155.05.01015I OL 5.01015———4.959.9514.95———3.57.011– 1.2– 0.25– 0.62– 1.8– 3.0– 0.64– 1.6– 4.20.641.64.20.050.050.05———1.53.04.0——————————————4.959.9514.95———3.57.011– 1.0– 0.25– 0.5– 1.5– 2.4– 0.51– 1.3– 3.40005.010152.254.506.752.755.508.25– 1.7– 0.36– 0.9– 3.5– 4.2– 0.88– 2.25– 8.80.050.050.05———1.53.04.0——————————————4.959.9514.95———3.57.011– 0.7– 0.14– 0.35– 1.1– 1.7– 0.36– 0.9– 2.4Input Current I in 15 — ±0.1 — ±0.00001 ±0.1 — ±1.0 µAdcInput Capacitance(V in = 0)———0.511.33.40.882.258.80.050.050.05C in — — — — 5.0 7.5 — — pF———0.360.92.4———1.53.04.0——————————————VdcVdcVdcVdcmAdcmAdcmAdcQuiescent Current(Per Package)Total Supply Current (5.) (6.)(Dynamic plus Quiescent,Per Package)(C L = 50 pF on all outputs, allbuffers switching)I DD 5.01015I T 5.01015———5.01020———0.0100.0200.0305.01020I T = (1.50 µA/kHz) f + I DDI T = (2.30 µA/kHz) f + I DDI T = (3.55 µA/kHz) f + I DD4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.5. The formulas given are for the typical characteristics only at 25 C.6. To calculate total supply current at loads other than 50 pF:I T (C L ) = I T (50 pF) + (C L – 50) Vfkwhere: I T is in µA (per package), C L in pF, V = (V DD – V SS ) in volts, f in kHz is input frequency, and k = 0.003.———150300600µAdcµAdchttp://onsemi.com329

MC14536BSWITCHING CHARACTERISTICS (7.) (C L = 50 pF, T A = 25 C)Characteristic Symbol V DD Min Typ (8.) Max UnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Rise and Fall Time (Pin 13)t TLH , t THL = (1.5 ns/pF) C L + 25 nst TLH , t THL = (0.75 ns/pF) C L + 12.5 nst TLH , t THL = (0.55 ns/pF) C L + 9.5 nsPropagation Delay TimeClock to Q1, 8–Bypass (Pin 6) Hight PLH , t PHL = (1.7 ns/pF) C L + 1715 nst PLH , t PHL = (0.66 ns/pF) C L + 617 nst PLH , t PHL = (0.5 ns/pF) C L + 425 nst TLH ,t THL 5.01015t PLH ,t PHL5.01015——————1005040180065045020010080360013001000nsnsClock to Q1, 8–Bypass (Pin 6) Lowt PLH , t PHL = (1.7 ns/pF) C L + 3715 nst PLH , t PHL = (0.66 ns/pF) C L + 1467 nst PLH , t PHL = (0.5 ns/pF) C L + 1075 nsClock to Q16t PHL , t PLH = (1.7 ns/pF) C L + 6915 nst PHL , t PLH = (0.66 ns/pF) C L + 2967 nst PHL , t PLH = (0.5 ns/pF) C L + 2175 nsReset to Q nt PHL = (1.7 ns/pF) C L + 1415 nst PHL = (0.66 ns/pF) C L + 567 nst PHL = (0.5 ns/pF) C L + 425 nst PLH ,t PHL 5.01015t PLH ,t PHL 5.01015t PHL5.01015Clock Pulse Width t WH 5.01015Clock Pulse Frequency(50% Duty Cycle)f cl 5.01015Clock Rise and Fall Time t TLH , 5.0t THL 1015Reset Pulse Width t WH 5.01015—————————600200170———3.81.51.17.03.02.21500600450300100851.23.05.0No Limit7. The formulas given are for the typical characteristics only at 25 C.8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.10004003005002001507.63.02.3146.04.530001200900———0.41.52.0———µsµsnsnsMHz—nshttp://onsemi.com330

MC14536BPIN DESCRIPTIONSINPUTSSET (Pin 1) — A high on Set asynchronously forcesDecode Out to a high level. This is accomplished by settingan output conditioning latch to a high level while at the sametime resetting the 24 flip–flop stages. After Set goes low(inactive), the occurrence of the first negative clocktransition on IN 1 causes Decode Out to go low. Thecounter’s flip–flop stages begin counting on the secondnegative clock transition of IN 1 . When Set is high, theon–chip RC oscillator is disabled. This allows for verylow–power standby operation.RESET (Pin 2) — A high on Reset asynchronouslyforces Decode Out to a low level; all 24 flip–flop stages arealso reset to a low level. Like the Set input, Reset disablesthe on–chip RC oscillator for standby operation.IN 1 (Pin 3) — The device’s internal counters advance onthe negative–going edge of this input. IN 1 may be used as anexternal clock input or used in conjunction with OUT 1 andOUT 2 to form an RC oscillator. When an external clock isused, both OUT 1 and OUT 2 may be left unconnected orused to drive 1 LSTTL or several CMOS loads.8–BYPASS (Pin 6) — A high on this input causes the first8 flip–flop stages to be bypassed. This device essentiallybecomes a 16–stage counter with all 16 stages selectable.Selection is accomplished by the A, B, C, and D inputs. (Seethe truth tables.)CLOCK INHIBIT (Pin 7) — A high on this inputdisconnects the first counter stage from the clocking source.This holds the present count and inhibits further counting.However, the clocking source may continue to run.Therefore, when Clock Inhibit is brought low, no oscillatorstart–up time is required. When Clock Inhibit is low, thecounter will start counting on the occurrence of the firstnegative edge of the clocking source at IN 1 .OSC INHIBIT (Pin 14) — A high level on this pin stopsthe RC oscillator which allows for very low–power standbyoperation. May also be used, in conjunction with an externalclock, with essentially the same results as the Clock Inhibitinput.MONO–IN (Pin 15) — Used as the timing pin for theon–chip monostable multivibrator. If the Mono–In input isconnected to V SS , the monostable circuit is disabled, andDecode Out is directly connected to the selected Q output.The monostable circuit is enabled if a resistor is connectedbetween Mono–In and V DD . This resistor and the device’sinternal capacitance will determine the minimum outputpulse widths. With the addition of an external capacitor toV SS , the pulse width range may be extended. For reliableoperation the resistor value should be limited to the range of5 kΩ to 100 kΩ and the capacitor value should be limited toa maximum of 1000 pf. (See figures 3, 4, 5, and 10).A, B, C, D (Pins 9, 10, 11, 12) — These inputs select theflip–flop stage to be connected to Decode Out. (See the truthtables.)OUTPUTSOUT 1 , OUT 2 (Pin 4, 5) — Outputs used in conjunctionwith IN 1 to form an RC oscillator. These outputs arebuffered and may be used for 2 0 frequency division of anexternal clock.DECODE OUT (Pin 13) — Output function depends onconfiguration. When the monostable circuit is disabled, thisoutput is a 50% duty cycle square wave during free run.TEST MODEThe test mode configuration divides the 24 flip–flopstages into three 8–stage sections to facilitate a fast testsequence. The test mode is enabled when 8–Bypass, Set andReset are at a high level. (See Figure 8.)http://onsemi.com331

MC14536BInput8–Bypass D C B AStage Selectedfor Decode Out0 0 0 0 0 90 0 0 0 1 100 0 0 1 0 110 0 0 1 1 120 0 1 0 0 130 0 1 0 1 140 0 1 1 0 150 0 1 1 1 160 1 0 0 0 170 1 0 0 1 180 1 0 1 0 190 1 0 1 1 200 1 1 0 0 210 1 1 0 1 220 1 1 1 0 230 1 1 1 1 24In 1 Set ResetTRUTH TABLESFUNCTION TABLEClockInhInput8–Bypass D C B AStage Selectedfor Decode Out1 0 0 0 0 11 0 0 0 1 21 0 0 1 0 31 0 0 1 1 41 0 1 0 0 51 0 1 0 1 61 0 1 1 0 71 0 1 1 1 81 1 0 0 0 91 1 0 0 1 101 1 0 1 0 111 1 0 1 1 121 1 1 0 0 131 1 1 0 1 141 1 1 1 0 151 1 1 1 1 16OSCInh Out 1 Out 2DecodeOut0 0 0 0 NoChange0 0 0 0 Advance tonext stateX 1 0 0 0 0 1 1X 0 1 0 0 0 1 0X 0 0 1 0 — — NoChangeX 0 0 0 1 0 1 NoChange0 0 0 0 X 0 1 NoChange1 0 0 0 Advance tonext stateX = Don’t Carehttp://onsemi.com332

MC14536BLOGIC DIAGRAMOSC INHIBIT143IN 14OUT 1SET1OUT 2 57CLOCKINHIBITC S QEn R2RESETT 1STAGES2 THRU 788–BYPASS6T 9A 9B10C11D1215MONO–INSTAGES10 THRU1516DECODER13DECODEROUT17STAGES18 THRU23V DD = PIN 16V SS = PIN 824http://onsemi.com333

MC14536BFREQUENCY DEVIATION (%)8.04.00– 4.0– 8.010 V5.0 V–12R TC = 56 kΩ, R S = 0, f = 10.15 kHz @ V DD = 10 V, T A = 25°CC = 1000 pF R S = 120 kΩ, f = 7.8 kHz @ V DD = 10 V, T A = 25°C–16– 55 – 25 0 25 50 75 100 125*Device Only. T A , AMBIENT TEMPERATURE (°C)*TYPICAL RC OSCILLATOR CHARACTERISTICS(For Circuit Diagram See Figure 11 In Application)100V DD = 15 V50Figure 1. RC Oscillator Stabilityf, OSCILLATOR FREQUENCY (kHz)20105.02.01.00.50.2f AS A FUNCTIONOF C(R TC = 56 kΩ)(R S = 120 k)V DD = 10 Vf AS A FUNCTIONOF R TC(C = 1000 pF)(R S ≈ 2R TC )0.11.0 k 10 k 100 kR TC , RESISTANCE (OHMS)1.0 M0.0001 0.001 0.01 0.1C, CAPACITANCE (µF)Figure 2. RC Oscillator Frequency as aFunction of R TC and Ct W , PULSE WIDTH ( µs)100101.00.11.0FORMULA FOR CALCULATING t W INMICROSECONDS IS AS FOLLOWS:t W = 0.00247 R X • C X 0.85WHERE R IS IN kΩ, C X IN pF.R X = 100 kΩ50 kΩ10 kΩ5 kΩT A = 25°CV DD = 5 V10100C X , EXTERNAL CAPACITANCE (pF)Figure 3. Typical C X versus Pulse Width@ V DD = 5.0 VMONOSTABLE CHARACTERISTICS(For Circuit Diagram See Figure 10 In Application)1000t W , PULSE WIDTH ( µs)100101.00.11.0FORMULA FOR CALCULATING t W INMICROSECONDS IS AS FOLLOWS:t W = 0.00247 R X • C X 0.85WHERE R IS IN kΩ, C X IN pF.R X = 100 kΩ50 kΩ10 kΩ5 kΩ T A = 25°CV DD = 10 V10100C X , EXTERNAL CAPACITANCE (pF)Figure 4. Typical C X versus Pulse Width@ V DD = 10 V1000t W , PULSE WIDTH ( µs)100101.00.11.0FORMULA FOR CALCULATING t W INMICROSECONDS IS AS FOLLOWS:t W = 0.00247 R X • C X 0.85WHERE R IS IN kΩ, C X IN pF.R X = 100 kΩ50 kΩ10 kΩ5 kΩ T A = 25°CV DD = 15 V10100C X , EXTERNAL CAPACITANCE (pF)Figure 5. Typical C X versus Pulse Width@ V DD = 15 V1000http://onsemi.com334

MC14536BV DD0.01 µFCERAMIC500 µF I DC LPULSEGENERATORSETRESET OUT 18–BYPASSIN 1C INHMONO IN OUTOSC INH 2ABCDDECODEOUTV SS20 ns 20 ns90% 50%10%50%DUTY CYCLEFigure 6. Power Dissipation TestCircuit and WaveformC LC LPULSEGENERATOR50%V DD IN 1 50%20 ns 20 nsSETOUT 1RESET90%OUT8–BYPASS10%t WL t WHIN 1t PHLt PLHt TLH t THLC INHMONO INOSC INHABCDOUT2DECODEOUTV SSC LFigure 7. Switching Time Test Circuit and WaveformsFUNCTIONAL TEST SEQUENCETest function (Figure 8) has been included for thereduction of test time required to exercise all 24 counterstages. This test function divides the counter into three8–stage sections and 255 counts are loaded in each of the8–stage sections in parallel. All flip–flops are now at a “1”.The counter is now returned to the normal 24–stages inseries configuration. One more pulse is entered into In 1which will cause the counter to ripple from an all “1” stateto an all “0” state.PULSEGENERATORV DDSETRESET OUT 18–BYPASSIN 1C INHMONO INOSC INHABCDOUT2DECODEOUTV SSFigure 8. Functional Test Circuithttp://onsemi.com335

MC14536BFUNCTIONAL TEST SEQUENCEInputs Outputs CommentsDecade OutIn 1 Set Reset 8–Bypass Q1 thru Q241 0 1 1 0All 24 stages are in Reset mode.1 1 1 1 0 Counter is in three 8 stage sections in parallel mode.0 1 1 1 0 First “1” to “0” transition of clock.10———1 1 1 255 “1” to “0” transitions are clocked in the counter.0 1 1 1 1 The 255 “1” to “0” transition.0 0 0 0 1 Counter converted back to 24 stages in series mode.Set and Reset must be connected together and simultaneouslygo from “1” to “0”.1 0 0 0 1 In 1 Switches to a “1”.0 0 0 0 0 Counter Ripples from an all “1” state to an all “0” state.http://onsemi.com336

MC14536B+V16PULSEGEN.PULSEGEN.CLOCK68–BYPASSV DD9AOUT 141011122141517BCDRESETOSC INHMONO–INSETCLOCK INHOUT 253IN 1DECODE OUT13V SS8CLOCK INHIN 1SETPOWER UPDECODE OUTNOTE: When power is first applied to the device, Decode Out can be either at a high or low state.On the rising edge of a Set pulse the output goes high if initially at a low state. The outputremains high if initially at a high state. Because Clock Inh is held high, the clock source onthe input pin has no effect on the output. Once Clock Inh is taken low, the output goes lowon the first negative clock transition. The output returns high depending on the 8–Bypass,A, B, C, and D inputs, and the clock input period. A 2 n frequency division (where n = thenumber of stages selected from the truth table) is obtainable at Decode Out. A 2 0 –dividedoutput of IN 1 can be obtained at OUT 1 and OUT 2 .Figure 9. Time Interval Configuration Using an External Clock, Set,and Clock Inhibit Functions(Divide–by–2 Configured)http://onsemi.com337

MC14536B+VPULSEGEN.CLOCKR X1668–BYPASSV DD9AOUT 141011122171514BCDRESETSETCLOCK INHMONO–INCLOCK INHOUT 253IN 1DECODE OUT13V SS8C X*t w ≈ .00247 • R X • C X 0.85IN 1RESETDECODE OUTPOWER UP*t wt w in µsecR X in kΩC X in pFNOTE: When Power is first applied to the device with the Reset input going high, Decode Out initializes low. Bringing the Resetinput low enables the chip’s internal counters. After Reset goes low, the 2 n /2 negative transition of the clock input causesDecode Out to go high. Since the Mono–In input is being used, the output becomes monostable. The pulse width of theoutput is dependent on the external timing components. The second and all subsequent pulses occur at 2 n x (the clockperiod) intervals where n = the number of stages selected from the truth table.Figure 10. Time Interval Configuration Using an External Clock, Reset,and Output Monostable to Achieve a Pulse Output(Divide–by–4 Configured)http://onsemi.com338

MC14536B+V16R SPULSEGEN.68–BYPASSV DD9AOUT 141011122141517BCDRESETSETCLOCK INHMONO–INCLOCK INHOUT 253IN 1DECODE OUT13V SS8CR TCRESETOUT 1OUT 2DECODE OUTPOWER UPt wfosc 12.3 Rtc CR s ≥ R tcF = HzR = OhmsC = FARADSNOTE: This circuit is designed to use the on–chip oscillation function. The oscillator frequency is determinedby the external R and C components. When power is first applied to the device, Decode Outinitializes to a high state. Because this output is tied directly to the Osc–Inh input, the oscillator isdisabled. This puts the device in a low–current standby condition. The rising edge of the Reset pulsewill cause the output to go low. This in turn causes Osc–Inh to go low. However, while Reset is high,the oscillator is still disabled (i.e.: standy condition). After Reset goes low, the output remains lowfor 2 n /2 of the oscillator’s period. After the part times out, the output again goes high.Figure 11. Time Interval Configuration Using On–Chip RC Oscillator andReset Input to Initiate Time Interval(Divide–by–2 Configured)http://onsemi.com339

The MC14538B is a dual, retriggerable, resettable monostablemultivibrator. It may be triggered from either edge of an input pulse,and produces an accurate output pulse over a wide range of widths, theduration and accuracy of which are determined by the external timingcomponents, C X and R X .Output Pulse Width = (Cx) (Rx) where:Rx is in kCx is in F• Unlimited Rise and Fall Time Allowed on the A Trigger Input• Pulse Width Range = 10 µs to 10 s• Latched Trigger Inputs• Separate Latched Reset Inputs• 3.0 Vdc to 18 Vdc Operational Limits• Triggerable from Positive (A Input) or Negative–Going Edge(B–Input)• Capable of Driving Two Low–power TTL Loads or One Low–powerSchottky TTL Load Over the Rated Temperature Range• Pin–for–pin Compatible with MC14528B and CD4528B (CD4098)• Use the MC54/74HC4538A for Pulse Widths Less Than 10 µs withSupplies Up to 6 V.MAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 2.)Symbol Parameter Value UnitV DD DC Supply Voltage Range –0.5 to +18.0 VV in , V out Input or Output Voltage Range(DC or Transient)–0.5 to V DD + 0.5 VI in , I outP DInput or Output Current(DC or Transient) per PinPower Dissipation,per Package (Note 3.)±10 mA500 mWT A Operating Temperature Range –55 to +125 °CT stg Storage Temperature Range –65 to +150 °CT LLead Temperature(8–Second Soldering)260 °C2. Maximum Ratings are those values beyond which damage to the devicemay occur.3. Temperature Derating:Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 CThis device contains protection circuitry to guard against damage due to highstatic voltages or electric fields. However, precautions must be taken to avoidapplications of any voltage higher than maximum rated voltages to thishigh–impedance circuit. For proper operation, V in and V out should be constrainedto the range V SS (V in or V out ) V DD .Unused inputs must always be tied to an appropriate logic voltage level (e.g.,either V SS or V DD ). Unused outputs must be left open.http://onsemi.com16PDIP–16P SUFFIXCASE 648116SOIC–16D SUFFIXCASE 751B1TSSOP–16DT SUFFIXCASE 948FSOIC–16DW SUFFIXCASE 751G116ORDERING INFORMATIONMARKINGDIAGRAMSMC14538BCPAWLYYWWDevice Package ShippingMC14538BCP PDIP–16 2000/BoxMC14538BD SOIC–16 48/RailMC14538BDR2 SOIC–16 2500/Tape & Reel16SOEIAJ–16F SUFFIXCASE 9661A = Assembly LocationWL or L = Wafer LotYY or Y = YearWW or W = Work Week14538BAWLYWW14538BALYW14538BAWLYYWWMC14538BAWLYWWMC14538BDT TSSOP–16 96/RailMC14538BDTR2 TSSOP–16 2500/Tape & Reel1. For ordering information on the EIAJ version ofthe SOIC packages, please contact your localON Semiconductor representative.16MC14538BDW SOIC–16 47/RailMC14538BDWR2 SOIC–16 1000/Tape & ReelMC14538BF SOEIAJ–16 See Note 1.MC14538BFEL SOEIAJ–16 See Note 1.1© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 3340 Publication Order Number:MC14538B/D

MC14538BPIN ASSIGNMENTV SS116V DDC X /R X A215V SSRESET A314C X /R X BA A413RESET B512A BB ABLOCK DIAGRAMQ A611B BQ A710Q BV SS89Q BC XRXV DD45AB1 2Q1Q1RESET673C XRXV DD1211AB15 14Q2Q2RESET10913R X AND C X ARE EXTERNAL COMPONENTS.V DD = PIN 16V SS = PIN 8, PIN 1, PIN 15ONE–SHOT SELECTION GUIDE100 nsMC14528BMC14536BMC14538BMC14541BMC4538A*1 µs 10 µs 100 µs 1 ms 10 ms 100 ms 1 s 10 s23 HR5 MIN.TOTAL OUTPUT PULSE WIDTH RANGERECOMMENDED PULSE WIDTH RANGE*LIMITED OPERATING VOLTAGE (2 – 6 V)http://onsemi.com341

ELECTRICAL CHARACTERISTICS (Voltages Referenced to V SS )MC14538BV DD– 55 C 25 C 125 CÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput VoltageV in = V DD or 0Characteristic Symbol Vdc Min Max Min Typ (4.) Max Min Max Unit“0” LevelV OL 5.01015V 5.0“1” LevelV in = 0 or V DDOH1015Input Voltage“0” Level(V O = 4.5 or 0.5 Vdc)(V O = 9.0 or 1.0 Vdc)(V O = 13.5 or 1.5 Vdc)(V O = 0.5 or 4.5 Vdc)(V O = 1.0 or 9.0 Vdc)(V O = 1.5 or 13.5 Vdc)“1” LevelOutput Drive Current(V OH = 2.5 Vdc) Source(V OH = 4.6 Vdc)(V OH = 9.5 Vdc)(V OH = 13.5 Vdc)(V OL = 0.4 Vdc) Sink(V OL = 0.5 Vdc)(V OL = 1.5 Vdc)V IL5.01015V IH5.01015I OH5.05.01015I OL 5.01015———4.959.9514.95———3.57.011– 3.0– 0.64– 1.6– 4.20.641.64.20.050.050.05———1.53.04.0——————————4.959.9514.95———3.57.011– 2.4– 0.51– 1.3– 3.40005.010152.254.506.752.755.508.25– 4.2– 0.88– 2.25– 8.80.050.050.05———1.53.04.0——————————4.959.9514.95———3.57.011– 1.7– 0.36– 0.9– 2.4Input Current, Pin 2 or 14 I in 15 — ±0.05 — ±0.00001 ±0.05 — ±0.5 µAdcInput Current, Other Inputs I in 15 — ±0.1 — ±0.00001 ±0.1 — ±1.0 µAdcInput Capacitance, Pin 2 or 14 C in — — — — 25 — — — pFInput Capacitance, Other Inputs(V in = 0)———0.511.33.40.882.258.80.050.050.05C in — — — — 5.0 7.5 — — pF———0.360.92.4———1.53.04.0——————————VdcVdcVdcVdcmAdcmAdcQuiescent Current(Per Package)Q = Low, Q = HighQuiescent Current, Active State(Both) (Per Package)Q = High, Q = LowI DD 5.01015I DD 5.01015Total Supply Current at an external I T 5.0external timing network (R X , C X ) (5.)load capacitance (C L ) and at10——————5.010202.02.02.0——————0.0050.0100.0150.040.080.135.010200.200.450.70——————I T = (3.5 x 10 –2 ) R X C X f + 4C X f + 1 x 10 –5 C L fI T = (8.0 x 10 –2 ) R X C X f + 9C X f + 2 x 10 –5 C L fI T = (1.25 x 10 –1 ) R X C X f + 12C X f + 3 x 10 –5 C L fwhere: I T in µA (one monostable switching only),where: C X in µF, C L in pF, R X in k ohms, andwhere: f in Hz is the input frequency.4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.5. The formulas given are for the typical characteristics only at 25 C.1503006002.02.02.0µAdcmAdcµAdchttp://onsemi.com342

SWITCHING CHARACTERISTICS (6.) (C L = 50 pF, T A = 25 C)MC14538BV DDAll TypesVdc Min Typ (7.) Max UnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCharacteristicOutput Rise Timet TLH = (1.35 ns/pF) C L + 33 nst TLH = (0.60 ns/pF) C L + 20 nst TLH = (0.40 ns/pF) C L + 20 nsOutput Fall Timet THL = (1.35 ns/pF) C L + 33 nst THL = (0.60 ns/pF) C L + 20 nst THL = (0.40 ns/pF) C L + 20 nsPropagation Delay TimeA or B to Q or Qt PLH , t PHL = (0.90 ns/pF) C L + 255 nst PLH , t PHL = (0.36 ns/pF) C L + 132 nst PLH , t PHL = (0.26 ns/pF) C L + 87 nsSymbolt TLH5.01015t THL5.01015t PLH ,t PHL5.01015—————————100504010050403001501002001008020010080600300220nsnsnsReset to Q or Qt PLH , t PHL = (0.90 ns/pF) C L + 205 nst PLH , t PHL = (0.36 ns/pF) C L + 107 nst PLH , t PHL = (0.26 ns/pF) C L + 82 ns5.01015———25012595500250190nsInput Rise and Fall TimesResett r , t f 51015——————1554µsB Input 51015———3001.20.41.00.10.05msA Input 51015No Limit—Input Pulse WidthA, B, or Resett WH ,5.0t WL 10151709080854540———nsRetrigger Time t rr 5.01015000——————nsOutput Pulse Width — Q or QRefer to Figures 8 and 9C X = 0.002 µF, R X = 100 kΩT5.01015198200202210212214230232234µsC X = 0.1 µF, R X = 100 kΩ 5.01015C X = 10 µF, R X = 100 kΩ 5.01015Pulse Width Match between circuits inthe same package.C X = 0.1 µF, R X = 100 kΩ100[(T 1 – T 2 )/T 1 ]9.39.49.59.861010.146. The formulas given are for the typical characteristics only at 25 C.7. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.5.010150.910.920.93———0.9650.980.99± 1.0± 1.0± 1.010.510.610.71.031.041.06± 5.0± 5.0± 5.0mss%http://onsemi.com343

OPERATING CONDITIONSMC14538BExternal Timing Resistance R X — 5.0 — (8.) kΩÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎExternal Timing Capacitance C X — 0 — NoLimit (9.) µF8. The maximum usable resistance R X is a function of the leakage of the capacitor C X , leakage of the MC14538B, and leakage due to boardlayout and surface resistance. Susceptibility to externally induced noise signals may occur for R X > 1 MΩ..9. If C X > 15 µF, use discharge protection diode per Fig. 11.V DDV DDP1R X2C X1(14)(15)N1ENABLE++C1 C2V ref1 – ENABLE V ref2 –R QOUTPUTLATCHS Q6 (10)7 (9)4 (12)A5 (11)B3 (13)RESETV SSCONTROLQ RSRESET LATCHQ RRNOTE: Pins 1, 8 and 15 mustbe externally groundedFigure 1. Logic Diagram(1/2 of DevIce Shown)V DD0.1 µF500 pFI DCERAMICV SSR X R X ′C XC X ′V SSV inACX /R XBRESETA′B′RESET′QQQ′Q′V in90%10%C L20 ns 20 nsV DD0 VFigure 2. Power Dissipation Test Circuit and Waveformshttp://onsemi.com344

MC14538BV DDINPUT CONNECTIONSV SSR X R X ′C XC X ′V SS*C L = 50 pFCharacteristics Reset A Bt PLH , t PHL , t TLH , t THL , V DD PG1 V DDT, t WH , t WLPULSEGENERATORPULSEGENERATORPULSEGENERATORC X /R XABRESETA′B′RESET′V SSQQQ′Q′C LC LC LC Lt PLH , t PHL , t TLH , t THL , V DD V SS PG2T, t WH , t WLt PLH(R) , t PHL(R) ,PG3 PG1 PG2t WH , t WL*Includes capacitance of probes,wiring, and fixture parasitic.NOTE: Switching test waveformsfor PG1, PG2, PG3 are shownIn Figure 4.PG1 =PG2 =PG3 =Figure 3. Switching Test CircuitA50%90%10%t WH t TLHt THL50% V DDB50%t THL90%10%t TLHV DDRESETQt PLHT50% 50% 50%t WLt THL t PHLt PLH t THL tTLHt PHLt WL90%10%90%10%50%50%t rrV DDt PHL t PHLt TLH t THLt PLHQ50% 50%90%10%50%50%Figure 4. Switching Test WaveformsRELATIVE FREQUENCY OF OCCURRENCE1.00.80.60.40.20T A = 25°CR X = 100 kΩC X = 0.1 µF–4 –2 0 2 4T, OUTPUT PULSE WIDTH (%)0% POINT PULSE WIDTHV DD = 5.0 V, T = 9.8 msV DD = 10 V, T = 10 msV DD = 15 V, T = 10.2 msNORMALIZED PULSE WIDTH CHANGEWITH RESPECT TO VALUE AT V DD = 10 V (%)21012567R X = 100 kΩC X = 0.1 µF8 9 10 11 12V DD , SUPPLY VOLTAGE (VOLTS)131415Figure 5. Typical Normalized Distributionof Units for Output Pulse WidthFigure 6. Typical Pulse Width Variation asa Function of Supply Voltage V DDhttp://onsemi.com345

MC14538B1000FUNCTION TABLETOTAL SUPPLY CURRENT ( µ A)100101.0R X = 100 kΩ, C L = 50 pFONE MONOSTABLE SWITCHING ONLY10 VV DD = 15 V5.0 VInputsOutputsReset A B Q QHHHLH L Not TriggeredH H Not TriggeredH L, H, H Not TriggeredH L L, H, Not TriggeredL X X L HX X Not Triggered0.10.001 0.1 1.0 10 100OUTPUT DUTY CYCLE (%)Figure 7. Typical Total Supply Currentversus Output Duty CycleTYPICAL NORMALIZED ERRORWITH RESPECT TO 25 °C VALUE AT V DD = 10 V (%)210–1–2R X = 100 kΩC X = 0.1 µFV DD = 15 VV DD = 10 VV DD = 5 V– 60 – 40 – 20 0 20 40 60 80 100 120 140T A , AMBIENT TEMPERATURE (°C)TYPICAL NORMALIZED ERRORWITH RESPECT TO 25 °C VALUE AT V DD = 10 V (%)3.02.01.00– 1.0– 2.0– 3.0V DD = 15 VV DD = 10 VV DD = 5.0 VR X = 100 kΩC X = .002 µF– 60 – 40 – 20 0 20 40 60 80 100 120 140T A , AMBIENT TEMPERATURE (°C)Figure 8. Typical Error of Pulse WidthEquation versus TemperatureFigure 9. Typical Error of Pulse WidthEquation versus Temperaturehttp://onsemi.com346

MC14538BTHEORY OF OPERATION13 4A2B5RESETV ref 2V ref 2 V ref 2 V ref 2C X /R XQV ref 1 V ref 1 V ref 1 V ref 1T T T1Positive edge trigger4Positive edge re–trigger (pulse lengthening)2Negative edge triggerPositive edge trigger5Positive edge re–trigger (pulse lengthening)3Figure 10. Timing OperationTRIGGER OPERATIONThe block diagram of the MC14538B is shown inFigure 1, with circuit operation following.As shown in Figure 1 and 10, before an input triggeroccurs, the monostable is in the quiescent state with the Qoutput low, and the timing capacitor C X completely chargedto V DD . When the trigger input A goes from V SS to V DD(while inputs B and Reset are held to V DD ) a valid trigger isrecognized, which turns on comparator C1 and N–channeltransistor N1 . At the same time the output latch is set. Withtransistor N1 on, the capacitor C X rapidly discharges towardV SS until V ref1 is reached. At this point the output ofcomparator C1 changes state and transistor N1 turns off.Comparator C1 then turns off while at the same timecomparator C2 turns on. With transistor N1 off, the capacitorC X begins to charge through the timing resistor, R X , towardV DD . When the voltage across C X equals V ref 2, comparatorC2 changes state, causing the output latch to reset (Q goeslow) while at the same time disabling comparator C2 . Thisends at the timing cycle with the monostable in the quiescentstate, waiting for the next trigger.In the quiescent state, C X is fully charged to V DD causingthe current through resistor R X to be zero. Both comparatorsare “off” with total device current due only to reversejunction leakages. An added feature of the MC14538B isthat the output latch is set via the input trigger without regardto the capacitor voltage. Thus, propagation delay fromtrigger to Q is independent of the value of C X , R X , or the dutycycle of the input waveform.RETRIGGER OPERATIONThe MC14538B is retriggered if a valid trigger occursfollowed by another valid trigger before the Q output hasreturned to the quiescent (zero) state. Any retrigger, after thetiming node voltage at pin 2 or 14 has begun to rise fromV ref 1 , but has not yet reached V ref 2 , will cause an increasein output pulse width T. When a valid retrigger is initiated, the voltage at C X /R X will again drop to V ref 1 beforeprogressing along the RC charging curve toward V DD . TheQ output will remain high until time T, after the last validretrigger.RESET OPERATIONThe MC14538B may be reset during the generation of theoutput pulse. In the reset mode of operation, an input pulseon Reset sets the reset latch and causes the capacitor to befast charged to V DD by turning on transistor P1 . When thevoltage on the capacitor reaches V ref 2, the reset latch willclear, and will then be ready to accept another pulse. It theReset input is held low, any trigger inputs that occur will beinhibited and the Q and Q outputs of the output latch will notchange. Since the Q output is reset when an input low levelis detected on the Reset input, the output pulse T can be madesignificantly shorter than the minimum pulse widthspecification.POWER–DOWN CONSIDERATIONSLarge capacitance values can cause problems due to thelarge amount of energy stored. When a system containinghttp://onsemi.com347

the MC14538B is powered down, the capacitor voltage maydischarge from V DD through the standard protection diodesat pin 2 or 14. Current through the protection diodes shouldbe limited to 10 mA and therefore the discharge time of theV DD supply must not be faster than (V DD ). (C)/(10 mA).For example, if V DD = 10 V and C X = 10 µF, the V DD supplyshould discharge no faster than (10 V) x (10 µF)/(10 mA)= 10 ms. This is normally not a problem since powersupplies are heavily filtered and cannot discharge at this rate.When a more rapid decrease of V DD to zero volts occurs,the MC14538B can sustain damage. To avoid this possibilityuse an external clamping diode, D X , connected as shown inFig. 11.MC14538BTYPICAL APPLICATIONSD xC x R V x DDV SSV DDFigure 11. Use of a Diode to LimitPower Down Current SurgeQQRESETRISING–EDGETRIGGERC X RXV DDQC X RXV DDQABQRISING–EDGETRIGGERABQB = V DDRESET = V DDRESET = V DDC X RXV DDQA = V SSAC X RXV DDQBFALLING–EDGETRIGGERRESET = V DDQBFALLING–EDGETRIGGERRESET = V DDQFigure 12. RetriggerableMonostables CircuitryFigure 13. Non–RetriggerableMonostables CircuitryNCABQQC DNCNCV DDV DDFigure 14. Connection of Unused Sectionshttp://onsemi.com348

The MC14541B programmable timer consists of a 16–stage binarycounter, an integrated oscillator for use with an external capacitor andtwo resistors, an automatic power–on reset circuit, and output controllogic.Timing is initialized by turning on power, whereupon the power–onreset is enabled and initializes the counter, within the specified V DDrange. With the power already on, an external reset pulse can beapplied. Upon release of the initial reset command, the oscillator willoscillate with a frequency determined by the external RC network. The16–stage counter divides the oscillator frequency (f osc ) with the n thstage frequency being f osc /2 n .• Available Outputs 2 8 , 2 10 , 2 13 or 2 16• Increments on Positive Edge Clock Transitions• Built–in Low Power RC Oscillator (± 2% accuracy over temperaturerange and ± 20% supply and ± 3% over processing at < 10 kHz)• Oscillator May Be Bypassed if External Clock Is Available (Applyexternal clock to Pin 3)• External Master Reset Totally Independent of Automatic ResetOperation• Operates as 2 n Frequency Divider or Single Transition Timer• Q/Q Select Provides Output Logic Level Flexibility• Reset (auto or master) Disables Oscillator During Resetting toProvide No Active Power Dissipation• Clock Conditioning Circuit Permits Operation with Very Slow ClockRise and Fall Times• Automatic Reset Initializes All Counters On Power Up• Supply Voltage Range = 3.0 Vdc to 18 Vdc with Auto ResetSupply Voltage Range = Disabled (Pin 5 = V DD )Supply Voltage Range = 8.5 Vdc to 18 Vdc with Auto ResetSupply Voltage Range = Enabled (Pin 5 = V SS )MAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 2.)Symbol Parameter Value UnitV DD DC Supply Voltage Range –0.5 to +18.0 VV in , V out Input or Output Voltage Range(DC or Transient)–0.5 to V DD + 0.5 VI in Input Current (DC or Transient) ±10 (per Pin) mAI out Output Current (DC or Transient) ±45 (per Pin) mAP DPower Dissipation,per Package (Note 3.)500 mWT A Ambient Temperature Range –55 to +125 °CT stg Storage Temperature Range –65 to +150 °CT LLead Temperature(8–Second Soldering)260 °C2. Maximum Ratings are those values beyond which damage to the devicemay occur.3. Temperature Derating:Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 Chttp://onsemi.comPDIP–14P SUFFIXCASE 646SOIC–14D SUFFIXCASE 751ATSSOP–14DT SUFFIXCASE 948GSOEIAJ–14F SUFFIXCASE 9651141A = Assembly LocationWL or L = Wafer LotYY or Y = YearWW or W = Work WeekORDERING INFORMATIONMARKINGDIAGRAMSDevice Package ShippingMC14541BCP PDIP–14 2000/BoxMC14541BD SOIC–14 55/RailMC14541BDR2 SOIC–14 2500/Tape & ReelMC14541BDT TSSOP–14 96/RailMC14541BDTR2 TSSOP–14 2500/Tape & ReelMC14541BF SOEIAJ–14 See Note 1.MC14541BFEL SOEIAJ–14 See Note 1.1. For ordering information on the EIAJ version ofthe SOIC packages, please contact your localON Semiconductor representative.This device contains protection circuitry to guardagainst damage due to high static voltages or electricfields. However, precautions must be taken to avoid applicationsof any voltage higher than maximum ratedvoltages to this high–impedance circuit. For properoperation, V in and V out should be constrained to therange V SS (V in or V out ) V DD .Unused inputs must always be tied to an appropriatelogic voltage level (e.g., either V SS or V DD ). Unused outputsmust be left open.1411414MC14541BCPAWLYYWW14541BAWLYWW114541BALYWMC14541BAWLYWW© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 6349 Publication Order Number:MC14541B/D

MC14541BPIN ASSIGNMENTR tc114V DDC tc213BR S312ANC411NCAR510MODEMR69Q/Q SELV SS78QNC = NO CONNECTIONELECTRICAL CHARACTERISTICS (Voltages Referenced to V SS )ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎV DD– 55 C 25 C 125 COutput VoltageV in = V DD or 0Characteristic Symbol Vdc Min Max Min Typ (4.) Max Min Max Unit“0” LevelV OL 5.01015V 5.0“1” LevelV in = 0 or V DDOH1015Input Voltage“0” Level(V O = 4.5 or 0.5 Vdc)(V O = 9.0 or 1.0 Vdc)(V O = 13.5 or 1.5 Vdc)(V O = 0.5 or 4.5 Vdc)(V O = 1.0 or 9.0 Vdc)(V O = 1.5 or 13.5 Vdc)“1” LevelOutput Drive Current(V OH = 2.5 Vdc) Source(V OH = 9.5 Vdc)(V OH = 13.5 Vdc)(V OL = 0.4 Vdc) Sink(V OL = 0.5 Vdc)(V OL = 1.5 Vdc)V IL5.01015V IH5.01015I OH5.01015I OL 5.01015———4.959.9514.95———3.57.011– 7.96– 4.19– 16.31.934.9619.30.050.050.05———1.53.04.0—————————4.959.9514.95———3.57.011– 6.42– 3.38– 13.20005.010152.254.506.752.755.508.25– 12.83– 6.75– 26.330.050.050.05———1.53.04.0—————————4.959.9514.95———3.57.011– 4.49– 2.37– 9.24Input Current I in 15 — ± 0.1 — ±0.00001 ± 0.1 — ± 1.0 µAdcInput Capacitance(V in = 0)Quiescent Current(Pin 5 is High)Auto Reset DisabledAuto Reset Quiescent Current(Pin 5 is low)Supply Current (5.) (6.)(Dynamic plus Quiescent)———1.564.015.63.128.031.2———1.092.810.90.050.050.05C in — — — — 5.0 7.5 — — pFI DD 5.01015I DDR 1015I D 5.01015—————5.01020250500—————0.0050.0100.01530825.01020250500I D = (0.4 µA/kHz) f + I DDI D = (0.8 µA/kHz) f + I DDI D = (1.2 µA/kHz) f + I DD4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.5. The formulas given are for the typical characteristics only at 25 C.6. When using the on chip oscillator the total supply current (in µAdc) becomes: I T = I D + 2 C tc V DD f x 10 –3 where I D is in µA, C tc is in pF,V DD in Volts DC, and f in kHz. (see Fig. 3) Dissipation during power–on with automatic reset enabled is typically 50 µA @ V DD = 10 Vdc.————————1.53.04.0—————————15030060015002000VdcVdcVdcVdcmAdcmAdcµAdcµAdcµAdchttp://onsemi.com350

MC14541BSWITCHING CHARACTERISTICS (7.) (C L = 50 pF, T A = 25 C)Characteristic Symbol V DD Min Typ (8.) Max UnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Rise and Fall Timet TLH , t THL = (1.5 ns/pF) C L + 25 nst TLH , t THL = (0.75 ns/pF) C L + 12.5 nst TLH , t THL = (0.55 ns/pF) C L + 9.5 nsPropagation Delay, Clock to Q (2 8 Output)t PLH , t PHL = (1.7 ns/pF) C L + 3415 nst PLH , t PHL = (0.66 ns/pF) C L + 1217 nst PLH , t PHL = (0.5 ns/pF) C L + 875 nsPropagation Delay, Clock to Q (2 16 Output)t PHL , t PLH = (1.7 ns/pF) C L + 5915 nst PHL , t PLH = (0.66 ns/pF) C L + 3467 nst PHL , t PLH = (0.5 ns/pF) C L + 2475 nst TLH ,t THL 5.01015t PLHt PHL 5.01015t PHLt PLH 5.01015Clock Pulse Width t WH(cl) 5.01015Clock Pulse Frequency (50% Duty Cycle) f cl 5.01015MR Pulse Width t WH(R) 5.01015Master Reset Removal Time t rem 5.010157. The formulas given are for the typical characteristics only at 25 C.8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.—————————900300225———90030022542020020010050403.51.250.96.03.52.5300100851.54.06.0300100852101001002001008010.53.82.918107.5———0.752.03.0——————nsµsµsnsMHznsnsV DDV DDPULSEGENERATORR SARQ/Q SELECTMODEABMRQC LPULSEGENERATORR SARQ/Q SELECTMODEABMRQC LV SSV SS(R tc AND C tc OUTPUTS ARE LEFT OPEN)20 ns 20 ns90% 50%10%50%DUTY CYCLE20 ns20 nsR SQt PLH90% 50% 50%10%50% 90% 10%t TLH50%t PHLt THLFigure 1. Power Dissipation Test Circuitand WaveformFigure 2. Switching Time Test Circuitand Waveformshttp://onsemi.com351

MC14541BEXPANDED BLOCK DIAGRAMA12B13R tc 1C tc 2R S 3OSCRESET8–STAGEC 2COUNTER8RESET2 10 2 13 2 16C 8–STAGECOUNTERRESET1 OF 4MUX8QAUTO RESET5POWER–ONRESETV DD = PIN 14V SS = PIN 76MASTER RESET10MODE9Q/QSELECTAFREQUENCY SELECTION TABLEBNumber ofCounter StagesnCount2 n0 0 13 81920 1 10 10241 0 8 2561 1 16 65536TRUTH TABLEStatePin 0 1Auto Reset, 5 Auto ResetOperatingAuto Reset DisabledMaster Reset, 6 Timer Operational Master Reset OnQ/Q, 9 Output Initially LowAfter ResetOutput Initially HighAfter ResetMode, 10 Single Cycle Mode Recycle Mode3TO CLOCKCIRCUITINTERNALRESET2 1C tcR SR TCFigure 3. Oscillator Circuit Using RC Configurationhttp://onsemi.com352

MC14541BTYPICAL RC OSCILLATOR CHARACTERISTICSFREQUENCY DEVIATION (%)8.04.00– 4.0– 8.0–12R TC = 56 kΩ,C = 1000 pF–16–55 –2510 VV DD = 15 V5.0 VR S = 0, f = 10.15 kHz @ V DD = 10 V, T A = 25°CR S = 120 kΩ, f = 7.8 kHz @ V DD = 10 V, T A = 25°C0 25 50 75T A , AMBIENT TEMPERATURE (°C)Figure 4. RC Oscillator Stability100125f, OSCILLATOR FREQUENCY (kHz)1005020105.02.01.00.50.2f AS A FUNCTIONOF C(R TC = 56 kΩ)(R S = 120 kΩ)V DD = 10 Vf AS A FUNCTIONOF R TC(C = 1000 pF)(R S ≈ 2R TC )0.11.0 k 10 k 100 k 1.0 mR TC , RESISTANCE (OHMS)0.0001 0.001 0.01 0.1C, CAPACITANCE (µF)OPERATING CHARACTERISTICSFigure 5. RC Oscillator Frequency as aFunction of R tc and C tcWith Auto Reset pin set to a “0” the counter circuit isinitialized by turning on power. Or with power already on,the counter circuit is reset when the Master Reset pin is setto a “1”. Both types of reset will result in synchronouslyresetting all counter stages independent of counter state.Auto Reset pin when set to a “1” provides a low poweroperation.The RC oscillator as shown in Figure 3 will oscillate witha frequency determined by the external RC network i.e.,1f =2.3 R tc C tcif (1 kHz f 100 kHz)and R S ≈ 2 R tc where R S ≥ 10 kΩThe time select inputs (A and B) provide a two–bit addressto output any one of four counter stages (2 8 , 2 10 , 2 13 and2 16 ). The 2 n counts as shown in the Frequency SelectionTable represents the Q output of the N th stage of the counter.When A is “1”, 2 16 is selected for both states of B. However,when B is “0”, normal counting is interrupted and the 9thcounter stage receives its clock directly from the oscillator(i.e., effectively outputting 2 8 ).The Q/Q select output control pin provides for a choice ofoutput level. When the counter is in a reset condition andQ/Q select pin is set to a “0” the Q output is a “0”,correspondingly when Q/Q select pin is set to a “1” the Qoutput is a “1”.When the mode control pin is set to a “1”, the selectedcount is continually transmitted to the output. But, withmode pin “0” and after a reset condition the R S flip–flop (seeExpanded Block Diagram) resets, counting commences,and after 2 n–1 counts the R S flip–flop sets which causes theoutput to change state. Hence, after another 2 n–1 counts theoutput will not change. Thus, a Master Reset pulse must beapplied or a change in the mode pin level is required to resetthe single cycle operation.DIGITAL TIMER APPLICATIONt MRINPUTR tcC tcNCR SARMR114213312411510697 8MODEQ/Qt + t MRV DDBAN.C.V DDOUTPUTWhen Master Reset (MR) receives a positive pulse, theinternal counters and latch are reset. The Q output goes highand remains high until the selected (via A and B) number ofclock pulses are counted, the Q output then goes low andremains low until another input pulse is received.This “one shot” is fully retriggerable and as accurate as theinput frequency. An external clock can be used (pin 3 is theclock input, pins 1 and 2 are outputs) if additional accuracyis needed.Notice that a setup time equal to the desired pulse widthoutput is required immediately following initial power up,during which time Q output will be high.http://onsemi.com353

The MC14543B BCD–to–seven segment latch/decoder/driver isdesigned for use with liquid crystal readouts, and is constructed withcomplementary MOS (CMOS) enhancement mode devices. Thecircuit provides the functions of a 4–bit storage latch and an 8421BCD–to–seven segment decoder and driver. The device has thecapability to invert the logic levels of the output combination. Thephase (Ph), blanking (BI), and latch disable (LD) inputs are used toreverse the truth table phase, blank the display, and store a BCD code,respectively. For liquid crystal (LC) readouts, a square wave is appliedto the Ph input of the circuit and the electrically common backplane ofthe display. The outputs of the circuit are connected directly to thesegments of the LC readout. For other types of readouts, such aslight–emitting diode (LED), incandescent, gas discharge, andfluorescent readouts, connection diagrams are given on this data sheet.Applications include instrument (e.g., counter, DVM etc.) displaydriver, computer/calculator display driver, cockpit display driver, andvarious clock, watch, and timer uses.• Latch Storage of Code• Blanking Input• Readout Blanking on All Illegal Input Combinations• Direct LED (Common Anode or Cathode) Driving Capability• Supply Voltage Range = 3.0 V to 18 V• Capable of Driving 2 Low–power TTL Loads, 1 Low–power SchottkyTTL Load or 2 HTL Loads Over the Rated Temperature Range• Pin–for–Pin Replacement for CD4056A (with Pin 7 Tied to V SS ).• Chip Complexity: 207 FETs or 52 Equivalent GatesMAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 2.)Symbol Parameter Value UnitV DD DC Supply Voltage Range –0.5 to +18.0 VV in Input Voltage Range, All Inputs –0.5 to V DD + 0.5 VI in DC Input Current per Pin ±10 mAP DPower Dissipation,per Package (Note 3.)500 mWT A Operating Temperature Range –55 to +125 °CT stg Storage Temperature Range –65 to +150 °CI OHmaxI OLmaxP OHmaxP OLmaxMaximum Continuous OutputDrive Current (Source or Sink)10(per Output)Maximum Continuous OutputPower (Source or Sink) (4.) 70(per Output)2. Maximum Ratings are those values beyond which damage to the devicemay occur.3. Temperature Derating:Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C4. P OHmax = I OH (V OH – V DD ) and P OLmax = I OL (V OL – V SS )mAmWhttp://onsemi.comPDIP–16P SUFFIXCASE 648SOIC–16D SUFFIXCASE 751BSOEIAJ–16F SUFFIXCASE 966A = Assembly LocationWL or L = Wafer LotYY or Y = YearWW or W = Work WeekORDERING INFORMATIONMARKINGDIAGRAMSDevice Package ShippingMC14543BCP PDIP–16 2000/BoxMC14543BD SOIC–16 48/RailMC14543BDR2 SOIC–16 2500/Tape & Reel1. For ordering information on the EIAJ version ofthe SOIC packages, please contact your localON Semiconductor representative.161161161MC14543BCPAWLYYWW14543BAWLYWWMC14543BAWLYWWMC14543BF SOEIAJ–16 See Note 1.MC14543BFEL SOEIAJ–16 See Note 1.This device contains protection circuitry to guardagainst damage due to high static voltages or electricfields. However, precautions must be taken to avoid applicationsof any voltage higher than maximum ratedvoltages to this high–impedance circuit. For properoperation, V in and V out should be constrained to therange V SS (V in or V out ) V DD .Unused inputs must always be tied to an appropriatelogic voltage level (e.g., either V SS or V DD ). Unused outputsmust be left open.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 3354 Publication Order Number:MC14543B/D

MC14543BPIN ASSIGNMENTLD116V DDC215fB314gD413eA512dPH611cBI710bV SS89aTRUTH TABLEInputsOutputsLD BI Ph* D C B A a b c d e f g DisplayX 1 0 X X X X 0 0 0 0 0 0 0 Blank1 0 0 0 0 0 0 1 1 1 1 1 1 0 01 0 0 0 0 0 1 0 1 1 0 0 0 0 11 0 0 0 0 1 0 1 1 0 1 1 0 1 21 0 0 0 0 1 1 1 1 1 1 0 0 1 31 0 0 0 1 0 0 0 1 1 0 0 1 1 41 0 0 0 1 0 1 1 0 1 1 0 1 1 51 0 0 0 1 1 0 1 0 1 1 1 1 1 61 0 0 0 1 1 1 1 1 1 0 0 0 0 71 0 0 1 0 0 0 1 1 1 1 1 1 1 81 0 0 1 0 0 1 1 1 1 1 0 1 1 91 0 0 1 0 1 0 0 0 0 0 0 0 0 Blank1 0 0 1 0 1 1 0 0 0 0 0 0 0 Blank1 0 0 1 1 0 0 0 0 0 0 0 0 0 Blank1 0 0 1 1 0 1 0 0 0 0 0 0 0 Blank1 0 0 1 1 1 0 0 0 0 0 0 0 0 Blank1 0 0 1 1 1 1 0 0 0 0 0 0 0 Blank0 0 0 X X X X ** **† † † † Inverse of Output DisplayCombinations as aboveAboveX = Don’t care† = Above Combinations* = For liquid crystal readouts, apply a square wave to PhFor common cathode LED readouts, select Ph = 0For common anode LED readouts, select Ph = 1** = Depends upon the BCD code previously applied when LD = 1http://onsemi.com355

MC14543BELECTRICAL CHARACTERISTICS (Voltages Referenced to V SS )V DD– 55 C 25 C 125 CÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput VoltageV in = V DD or 0Characteristic Symbol Vdc Min Max Min Typ (5.) Max Min Max Unit“0” LevelV OL 5.01015V 5.0“1” LevelV in = 0 or V DDOH1015Input Voltage“0” Level(V O = 4.5 or 0.5 Vdc)(V O = 9.0 or 1.0 Vdc)(V O = 13.5 or 1.5 Vdc)(V O = 0.5 or 4.5 Vdc)(V O = 1.0 or 9.0 Vdc)(V O = 1.5 or 13.5 Vdc)“1” LevelOutput Drive Current(V OH = 2.5 Vdc) Source(V OH = 4.6 Vdc)(V OH = 0.5 Vdc)(V OH = 9.5 Vdc)(V OH = 13.5 Vdc)(V OL = 0.4 Vdc) Sink(V OL = 0.5 Vdc)(V OL = 9.5 Vdc)(V OL = 1.5 Vdc)V IL5.01015V IH5.01015I OH5.05.0101015I OL 5.0101015———4.959.9514.95———3.57.011– 3.0– 0.64—– 1.6– 4.20.641.6—4.20.050.050.05———1.53.04.0———————————4.959.9514.95———3.57.011– 2.4– 0.51—– 1.3– 3.40005.010152.254.506.752.755.508.25– 4.2– 0.88– 10.1– 2.25– 8.80.050.050.05———1.53.04.0———————————4.959.9514.95———3.57.011– 1.7– 0.36—– 0.9– 2.4Input Current I in 15 — ±0.1 — ±0.00001 ±0.1 — ±1.0 µAdcInput Capacitance C in — — — — 5.0 7.5 — — pFQuiescent Current(Per Package) V in = 0 or V DD ,I out = 0 µATotal Supply Current (6.) (7.)(Dynamic plus Quiescent,Per Package)(C L = 50 pF on all outputs, allbuffers switching)I DD 5.01015I T 5.010155. Noise immunity specified for worst–case input combination.Noise Margin for both “1” and “0” level = 1.0 V min @ V DD = 5.0 V= 2.0 V min @ V DD = 10 V= 2.5 V min @ V DD = 15 V6. To calculate total supply current at loads other than 50 pF:I T (C L ) = I T (50 pF) + 3.5 x 10 –3 (C L – 50) V DD fwhere: I T is in µA (per package), C L in pF, V DD in V, and f in kHz is input frequency.7. The formulas given are for the typical characteristics only at 25 C.———————5.010200.511.3—3.4———0.882.2510.18.80.0050.0100.015————5.01020I T = (1.6 µA/kHz) f + I DDI T = (3.1 µA/kHz) f + I DDI T = (4.7 µA/kHz) f + I DD0.360.9—2.4———0.050.050.05———1.53.04.0——————————150300600VdcVdcVdcVdcmAdcmAdcµAdcµAdchttp://onsemi.com356

MC14543BSWITCHING CHARACTERISTICS (8.) (C L = 50 pF, T A = 25 C)Characteristic Symbol V DD Min Typ Max UnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Rise Timet TLH = (3.0 ns/pF) C L + 30 nst TLH = (1.5 ns/pF) C L + 15 nst TLH = (1.1 ns/pF) C L + 10 nsOutput Fall Timet THL = (1.5 ns/pF) C L + 25 nst THL = (0.75 ns/pF) C L + 12.5 nst THL = (0.55 ns/pF) C L + 12.5 nsTurn–Off Delay Timet PLH = (1.7 ns/pF) C L + 520 nst PLH = (0.66 ns/pF) C L + 217 nst PLH = (0.5 ns/pF) C L + 160 nsTurn–On Delay Timet PHL = (1.7 ns/pF) C L + 420 nst PHL = (0.66 ns/pF) C L + 172 nst PHL = (0.5 ns/pF) C L + 130 nst TLH5.01015t THL5.01015t PLH5.01015t PHL5.01015Setup Time t su 5.01015Hold Time t h 5.01015Latch Disable Pulse Width (Strobing Data) t WH 5.010158. The formulas given are for the typical characteristics only.————————————35045050040302025010080100504010050406052501855052051551255040200100802001008012105003701650660495—————————nsnsnsnsnsnsnsLOGIC DIAGRAMV DD = PIN 16V SS = PIN 8BI 7A59a10 bB311 c12 dC213 e15 fD414 gLD 1PHASE 6http://onsemi.com357

MC14543BIOH, SOURCE CURRENT (mAdc)0– 6.0–12P OHmax = 70 mWdcV DD = 10 VdcV DD = 5.0 Vdc–18V DD = 15 VdcV SS = 0 Vdc–24– 16 – 12 – 8.0 – 4.0 0(V OH – V DD ), SOURCE DEVICE VOLTAGE (Vdc)Figure 1. Typical Output SourceCharacteristicsI OL , SINK CURRENT (mAdc)2418126.0V DD = 5.0 VdcV DD = 10 VdcV SS = 0 Vdc00 4.0 8.0 12 16(V OL – V SS ), SINK DEVICE VOLTAGE (Vdc)Figure 2. Typical Output SinkCharacteristicsV DD = 15 VdcP OLmax = 70 mWdc(a) Inputs D, Ph, and BI low, and Inputs A, B, and LD high.Cg20 ns 20 ns90%50%10%t PHLt PLH90%50%10%t THL t TLHV DDV SSV OHV OLInputs BI and Ph low, and Inputs D and LD high.f in respect to a system clock.All outputs connected to respective C L loads.20 ns 20 nsA, B, AND C90%10%50%12f50% DUTY CYCLEANY OUTPUTFigure 3. Dynamic Power DissipationSignal WaveformsV DDV SSV OHV OL(b) Inputs D, Ph, and BI low, and Inputs A and B high.20 nsV DDLD90%50%10%V SSt su t hV DDC50% 50%V SSV OHgV OL(c) Data DCBA strobed into latchesV DDLD50%V SSt WHFigure 4. Dynamic Signal Waveformshttp://onsemi.com358

MC14543BCONNECTIONS TO VARIOUS DISPLAY READOUTSLIQUID CRYSTAL (LC) READOUTINCANDESCENT READOUTMC14543BOUTPUTPhONE OF SEVEN SEGMENTSCOMMONBACKPLANEAPPROPRIATEVOLTAGESQUARE WAVE(V SS TO V DD )MC14543BOUTPUTPhV SSMC14543BOUTPUTPhV SSLIGHT EMITTING DIODE (LED) READOUTCOMMONCATHODE LEDCOMMONANODE LEDMC14543BOUTPUTPhNOTE: Bipolar transistors may be added for gain (for V DD 10 V or I out ≥ 10 mA).V DDV DDGAS DISCHARGE READOUTMC14543BOUTPUTPhV SSAPPROPRIATEVOLTAGECONNECTIONS TO SEGMENTSefdagbcV DD = PIN 16V SS = PIN 8DISPLAY0 1 2 3 4 5 6 7 8 9http://onsemi.com359

The MC14549B and MC14559B successive approximationregisters are 8–bit registers providing all the digital control and storagenecessary for successive approximation analog–to–digital conversionsystems. These parts differ in only one control input. The Master Reset(MR) on the MC14549B is required in the cascaded mode when morethan 8 bits are desired. The Feed Forward (FF) of the MC14559B isused for register shortening where End–of–Conversion (EOC) isrequired after less than eight cycles.Applications for the MC14549B and MC14559B includeanalog–to–digital conversion, with serial and parallel outputs.• Totally Synchronous Operation• All Outputs Buffered• Single Supply Operation• Serial Output• Retriggerable• Compatible with a Variety of Digital and Analog Systems such as theMC1408 8–Bit D/A Converter• All Control Inputs Positive–Edge Triggered• Supply Voltage Range = 3.0 Vdc to 18 Vdc• Capable of Driving 2 Low–Power TTL Loads, 1 Low–Power SchottkyTTL Load or 2 HTL Loads Over the Rated Temperature Range• Chip Complexity: 488 FETs or 122 Equivalent GatesMAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 1.)Symbol Parameter Value UnitV DD DC Supply Voltage Range –0.5 to +18.0 VV in Input Voltage Range, All Inputs –0.5 to V DD + 0.5 VI in DC Input Current, per Pin ±10 mAP DPower Dissipation,per Package (Note 2.)500 mWT A Operating Temperature Range –55 to +125 °CT stg Storage Temperature Range –65 to +150 °C1. Maximum Ratings are those values beyond which damage to the devicemay occur.2. Temperature Derating:Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 Chttp://onsemi.comPDIP–16P SUFFIXCASE 648SOIC–16DW SUFFIXCASE 751GXX = Specific Device CodeA = Assembly LocationWL or L = Wafer LotYY or Y = YearWW or W = Work WeekORDERING INFORMATIONMARKINGDIAGRAMS16MC145XXBCPAWLYYWWDevice Package ShippingMC14549BCP PDIP–16 25/RailMC14549BDWR2 SOIC–16 1000/Tape & Reel1161145XXBAWLYYWWMC14559BCP PDIP–16 25/RailMC14559BDWR2 SOIC–16 1000/Tape & ReelThis device contains protection circuitry to guard against damage due to highstatic voltages or electric fields. However, precautions must be taken to avoidapplications of any voltage higher than maximum rated voltages to thishigh–impedance circuit. For proper operation, V in and V out should be constrainedto the range V SS (V in or V out ) V DD .Unused inputs must always be tied to an appropriate logic voltage level (e.g.,either V SS or V DD ).© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 3360 Publication Order Number:MC14549B/D

MC14549B, MC14559BPIN ASSIGNMENTQ4116V DDQ5215Q3Q6314Q2Q7413Q1S out512Q0D611EOCV SSC78109*SC*For MC14549B Pin 10 is MR input.For MC14559B Pin 10 is FF input.MC14549BTRUTH TABLESSC SC( t–1 ) MR MR( t–1 ) Clock ActionX X X X NoneX X 1 X Reset1 0 0 0 StartConversion1 X 0 1 StartConversion1 1 0 0 ContinueConversion0 X 0 X ContinuePreviousOperationX = Don’t Caret–1 = State at Previous ClockMC14559BSC SC( t–1 ) EOC Clock ActionX X X None1 0 0 StartConversionX 1 0 ContinueConversion0 0 0 ContinueConversion0 X 1 RetainConversionResult1 X 1 StartConversionhttp://onsemi.com361

MC14549B, MC14559BELECTRICAL CHARACTERISTICS (Voltages Referenced to V SS )V DD– 55 C 25 C 125 CÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput VoltageV in = V DD or 0Characteristic Symbol Vdc Min Max Min Typ (3.) Max Min Max Unit“0” LevelV OL 5.01015V 5.0“1” LevelV in = 0 or V DDOH1015Input Voltage (3.) “0” Level(V O = 4.5 or 0.5 Vdc)(V O = 9.0 or 1.0 Vdc)(V O = 13.5 or 1.5 Vdc)(V O = 0.5 or 4.5 Vdc)(V O = 1.0 or 9.0 Vdc)(V O = 1.5 or 13.5 Vdc)“1” LevelOutput Drive Current(V OH = 2.5 Vdc) Source(V OH = 4.6 Vdc)(V OH = 9.5 Vdc)(V OH = 13.5 Vdc)(V OL = 0.4 Vdc) Sink(V OL = 0.5 Vdc) Q Outputs(V OL = 1.5 Vdc)(V OL = 0.4 Vdc) Sink(V OL = 0.5 Vdc) Pin 5, 11 only(V OL = 1.5 Vdc)V IL5.01015V IH5.01015I OH5.05.01015I OL 5.010155.01015———4.959.9514.95———3.57.011– 1.2– 0.25– 0.62– 1.81.283.28.40.641.64.20.050.050.05———1.53.04.0——————————4.959.9514.95———3.57.011– 1.0– 0.2– 0.5– 1.50005.010152.254.506.752.755.508.25– 1.7– 0.36– 0.9– 3.50.050.050.05———1.53.04.0——————————4.959.9514.95———3.57.011– 0.7– 0.14– 0.35– 1.1Input Current I in 15 — ±0.1 — ±0.00001 ±0.1 — ±1.0 µAdcInput Capacitance C in — — — — 5.0 7.5 — — pFQuiescent Current(Per Package)(Clock = 0 V,Other Inputs = V DDor 0 V, I out = 0 µA)Total Supply Current (4.) (5.)(Dynamic plus Quiescent,Per Package)(C L = 50 pF on all outputs, allbuffers switching)I DD 5.01015I T 5.010153. Noise immunity specified for worst–case input combination.Noise Margin for both “1” and “0” level = 1.0 V min @ V DD = 5.0 V= 2.0 V min @ V DD = 10 V= 2.5 V min @ V DD = 15 V4. To calculate total supply current at loads other than 50 pF:I T (C L ) = I T (50 pF) + 3.5 x 10 –3 (C L = 50) V DD fwhere: I T is in µA (per package), C L in pF, V DD in V, and f in kHz is input frequency.5. The formulas given are for the typical characteristics only at 25 C.—————————5.010201.022.66.80.511.33.4———1.764.517.60.882.258.80.0050.0100.015——————5.01020I T = (0.8 µA/kHz) f + I DDI T = (1.6 µA/kHz) f + I DDI T = (2.4 µA/kHz) f + I DD0.721.84.80.360.92.4———0.050.050.05———1.53.04.0—————————————150300600VdcVdcVdcVdcmAdcmAdcmAdcµAdcµAdchttp://onsemi.com362

MC14549B, MC14559BSWITCHING CHARACTERISTICS (6.) (C L = 50 pF, T A = 25 C)Characteristic Symbol V DD Min Typ Max UnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Rise Timet TLH = (3.0 ns/pF) C L + 30 nst TLH = (1.5 ns/pF) C L + 15 nst TLH = (1.1 ns/pF) C L + 10 nsOutput Fall Timet THL = (1.5 ns/pF) C L + 25 nst THL = (0.75 ns/pF) C L + 12.5 nst THL = (0.55 ns/pF) C L + 9.5 nsPropagation Delay TimeClock to Qt PLH , t PHL = (1.7 ns/pF) C L + 415 nst PLH , t PHL = (0.66 ns/pF) C L + 177 nst PLH , t PHL = (0.5 ns/pF) C L + 130 nsClock to S outt PLH , t PHL = (1.7 ns/pF) C L + 665 nst PLH , t PHL = (0.66 ns/pF) C L + 277 nst PLH , t PHL = (0.5 ns/pF) C L + 195 nsClock to EOCt PLH , t PHL = (1.7 ns/pF) C L + 215 nst PLH , t PHL = (0.66 ns/pF) C L + 97 nst PLH , t PHL = (0.5 ns/pF) C L + 75 nst TLH5.01015t THL5.01015t PLH ,t PHL5.01015SC, D, FF or MR Setup Time t su 5.01015Clock Pulse Width t WH(cl) 5.01015Pulse Width — D, SC, FF or MR t WH 5.01015Clock Rise and Fall Time t TLH , 5.0t THL 1015Clock Pulse Frequency f cl 5.010156. The formulas given are for the typical characteristics only.5.010155.01015——————————————2501008070027020050020016018090651005040500210155750310220300130100125504035013510025010080——— ————1.53.04.03601801302001008010004203101500620440600260200—————————151.00.50.81.52.0nsnsnsnsnsnsµsMHzhttp://onsemi.com363

MC14549B, MC14559BSWITCHING TIME TEST CIRCUIT AND WAVEFORMSV DDPROGRAMMABLEPULSEGENERATORCSCFF(MR)DQ7Q6Q5Q4Q3Q2Q1Q0EOCS outV SSC LC LC LC LC LC L1f cltWH(cl)C LC LC LC LC50%SCDQ7S out50%t PLH50%t sut su tsut WH(D)t PHL50% 90% 10%t TLHt THL t PLH50% 90%10%t TLHNOTE: Pin 10 = V SSTIMING DIAGRAMCLOCKSCDQ7Q6Q5Q4Q3Q2Q1Q0EOCS outÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ— Don’t care conditionINH — Indicates Serial Out is inhibited low.* — Q8 is ninth–bit of serial information available from 8–bit register.NOTE: Pin 10 = V SSÉÉÉÉÉÉINH Q7 Q6 INH Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Q8* INHhttp://onsemi.com364

MC14549B, MC14559BOPERATING CHARACTERISTICSBoth the MC14549B and MC14559B can be operated ineither the “free run” or “strobed operation” mode forconversion schemes with any number of bits. Reliablecascading and/or recirculating operation can be achieved ifthe End of Convert (EOC) output is used as the controllingfunction, since with EOC = 0 (and with SC = 1 forMC14549B but either 1 or 0 for MC14559B) no stable stateexists under continual clocked operation. The MC14559Bwill automatically recirculate after EOC = 1 duringexternally strobed operation, provided SC = 1.All data and control inputs for these devices are triggeredinto the circuit on the positive edge of the clock pulse.Operation of the various terminals is as follows:C = Clock — A positive–going transition of the Clock isrequired for data on any input to be strobed into the circuit.SC = Start Convert — A conversion sequence is initiatedon the positive–going transition of the SC input onsucceeding clock cycles.D = Data in — Data on this input (usually from acomparator in A/D applications) is also entered into thecircuit on a positive–going transition of the clock. This inputis Schmitt triggered and synchronized to allow fast responseand guaranteed quality of serial and parallel data.MR = Master Reset (MC14549B Only) — Resets alloutput to 0 on positive–going transitions of the clock. Ifremoved while SC = 0, the circuit will remain reset until SC= 1. This allows easy cascading of circuits.FF = Feed Forward (MC14559B Only) — Providesregister shortening by removing unwanted bits from asystem.For operation with less than 8 bits, tie the output followingthe least significant bit of the circuit to EOC. E.g., for a 6–bitconversion, tie Q1 to FF; the part will respond as shown inthe timing diagram less two bit times. Not that Q1 and Q0will still operate and must be disregarded.For 8–bit operation, FF is tied to V SS .For applications with more than 8 but less than 16 bits, usethe basic connections shown in Figure 1. The FF input of theMC14559B is used to shorten the setup. Tying FF directlyto the least significant bit used in the MC14559B allowsEOC to provide the cascading signal, and results in smoothtransition of serial information from the MC14559B to theMC14549B. The Serial Out (S out ) inhibit structure of theMC14559B remains inactive one cycle after EOC goes high,while S out of the MC14549B remains inhibited until thesecond clock cycle of its operation.Q n = Data Outputs — After a conversion is initiated theQ’s on succeeding cycles go high and are then conditionallyreset dependent upon the state of the D input. Onceconditionally reset they remain in the proper state until thecircuit is either reset or reinitiated.EOC = End of Convert — This output goes high on thenegative–going transition of the clock following FF = 1 (forthe MC14559B) or the conditional reset of Q0. This allowssettling of the digital circuitry prior to the End of Conversionindication. Therefore either level or edge triggering canindicate complete conversion.S out = Serial Out — Transmits conversion in serialfashion. Serial data occurs during the clock period when thecorresponding parallel data bit is conditionally reset. SerialOut is inhibited on the initial period of a cycle, when thecircuit is reset, and on the second cycle after EOC goes high.This provides efficient operation when cascaded.FROM A/DCOMPARATOREXTERNALCLOCK1/4 MC14001CD S outSC MC14559B* FFQ7 Q6 Q5 Q4 •• Q0 EOC**CSCMRQ7 Q6 Q5DMC14549BS outQ4 Q3 Q2 Q1 Q0 EOCSERIAL OUT(CONTINUALUPDATE EVERY13 CLOCK CYCLES)MSBNCTO D/A AND PARALLEL DATATO D/A ANDPARALLEL DATALSBFREE RUN MODEEXTERNAL STROBE* FF allows EOC to activate as if in 4–stage register.** Cascading using EOC guaranteed; no stable unfunctional state.†Completion of conversion automatically re–initiates cycle in free run mode.Figure 1. 12–Bit Conversion Schemehttp://onsemi.com365

MC14549B, MC14559BTYPICAL APPLICATIONSExternally Controlled 6–Bit ADC (Figure 2)Several features are shown in this application:• Shortening of the register to six bits by feeding theseventh output bit into the FF input.• Continuous conversion, if a continuous signal is appliedto SC.• Externally controlled updating (the start pulse must beshorter than the conversion cycle).• The EOC output indicating that the parallel data are validand that the serial output is complete.Continuously Cycling 8–Bit ADC (Figure 3)This ADC is running continuously because the EOCsignal is fed back to the SC input, immediately initiating anew cycle on the next clock pulse.Continuously Cycling 12–Bit ADC (Figure 4)Because each successive approximation register (SAR)has a capability of handling only an eight–bit word, twomust be cascaded to make an ADC with more than eight bits.When it is necessary to cascade two SAR’s, the secondSAR must have a stable resettable state to remain in whileawaiting a subsequent start signal. However, the first stagemust not have a stable resettable state while recycling,because during switch–on or due to outside influences, thefirst stage has entered a reset state, the entire ADC willremain in a stable non–functional condition.This 12–bit ADC is continuously recycling. The serial aswell as the parallel outputs are updated every thirteenthclock pulse. The EOC pulse indicates the completion of the12–bit conversion cycle, the end of the serial output word,and the validity of the parallel data output.SC C MC14559BS outQ7 Q6 Q5Q4 Q3 Q2 Q1 Q0 FF EOCTO DACFigure 2. Externally Controlled 6–Bit ADCSC C MC14559BS outQ7 Q6 Q5Q4 Q3 Q2 Q1 Q0 FF EOCTO DACFigure 3. Continuously Cycling 8–Bit ADChttp://onsemi.com366

MC14549B, MC14559BS outCS outSCMC14559BQ7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 FF EOCSCMRQ7 Q6 Q5CMC14549BS outQ4 Q3 Q2 Q1 Q0 EOCTO DACTO DACFigure 4. Continuously Cycling 12–Bit ADCEOCExternally Controlled 12–Bit ADC (Figure 5)In this circuit the external pulse starts the first SAR andsimultaneously resets the cascaded second SAR. When Q4of the first SAR goes high, the second SAR startsconversion, and the first one stops conversion. EOCindicates that the parallel data are valid and that the serialoutput is complete. Updating the output data is started withevery external control pulse.Additional Motorola Parts for SuccessiveApproximation ADCMonolithic digital–to–analog converters — TheMC1408/1508 converter has eight–bit resolution and isavailable with 6, 7, and 8–bit accuracy. Theamplifier–comparator block — The MC1407/1507contains a high speed operational amplifier and a high speedcomparator with adjustable window.With these two linear parts it is possible to constructSA–ADCs with an accuracy of up to eight bits, using as theregister one MC14549B or one MC14559B. An additionalCMOS block will be necessary to generate the clockfrequency.Additional information on successive approximationADC is found in Motorola Application Note AN–716.CS outSCMC14559BQ7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 FF EOCSCMRQ7 Q6 Q5CMC14549BS outQ4 Q3 Q2 Q1 Q0 EOCTO DACTO DACEOCS outFigure 5. Externally Controlled 12–Bit ADChttp://onsemi.com367

The MC14551B is a digitally–controlled analog switch. This deviceimplements a 4PDT solid state switch with low ON impedance andvery low OFF Leakage current. Control of analog signals up to thecomplete supply voltage range can be achieved.• Triple Diode Protection on All Control Inputs• Supply Voltage Range = 3.0 Vdc to 18 Vdc• Analog Voltage Range (V DD – V EE ) = 3.0 to 18 VNote: V EE must be V SS• Linearized Transfer Characteristics• Low Noise — 12 nV√Cycle, f ≥ 1.0 kHz typical• For Low R ON , Use The HC4051, HC4052, or HC4053 High–SpeedCMOS Devices• Switch Function is Break Before MakeMAXIMUM RATINGS (2.)Symbol Parameter Value UnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎV DDV in , V outI inDC Supply Voltage Range(Referenced to V EE , V SS ≥ V EE )Input or Output Voltage (DC orTransient) (Referenced to V SS forControl Input & V EE for Switch I/O)Input Current (DC or Transient),per Control Pin– 0.5 to + 18.0 V– 0.5 to V DD + 0.5 V± 10 mAI sw Switch Through Current ± 25 mAP D Power Dissipation, per Package (3.) 500 mWT A Ambient Temperature Range – 55 to + 125 CT stg Storage Temperature Range – 65 to + 150 CT LLead Temperature(8–Second Soldering)260 C2. Maximum Ratings are those values beyond which damage to the devicemay occur.3. Temperature Derating:Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 CThis device contains protection circuitry to guard against damage due to highstatic voltages or electric fields. However, precautions must be taken to avoidapplications of any voltage higher than maximum rated voltages to thishigh–impedance circuit. For proper operation, V in and V out should be constrainedto the range V SS (V in or V out ) V DD for control inputs and V EE ≤ (V in or V out ) ≤V DD for Switch I/O.Unused inputs must always be tied to an appropriate logic voltage level (e.g.,either V SS , V EE or V DD ). Unused outputs must be left open.http://onsemi.comPDIP–16P SUFFIXCASE 648SOIC–16D SUFFIXCASE 751BSOEIAJ–16F SUFFIXCASE 966ORDERING INFORMATIONMARKINGDIAGRAMSDevice Package ShippingMC14551BCP PDIP–16 2000/BoxMC14551BD SOIC–16 48/RailMC14551BDR2 SOIC–16 2500/Tape & Reel16116A = Assembly LocationWL or L = Wafer LotYY or Y = YearWW or W = Work Week1161MC14551BCPAWLYYWW14551BAWLYWWMC14551BAWLYWWMC14551BF SOEIAJ–16 See Note 1.1. For ordering information on the EIAJ version ofthe SOIC packages, please contact your localON Semiconductor representative.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 3368 Publication Order Number:MC14551B/D

MC14551BPIN ASSIGNMENTW1116V DDX0215W0X1314WX413ZY512Z1Y0611Z0V EE710Y1V SS89CONTROLSWITCHESIN/OUT9151236101112CONTROLWW0W1 XX0X1Y0 YY1Z0 ZZ1144513COMMONSOUT/INV DD = Pin 16V SS = Pin 8V EE = Pin 7Control ON0 W0 X0 Y0 Z01 W1 X1 Y1 Z1NOTE: Control Input referenced to V SS , Analog Inputs andOutputs reference to V EE . V EE must be V SS .http://onsemi.com369

ELECTRICAL CHARACTERISTICSMC14551B– 55 C 25 C 125 CÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCharacteristic Symbol V DD Test Conditions Min Max Min Typ (4.) Max Min Max UnitSUPPLY REQUIREMENTS (Voltages Referenced to V EE )Power Supply VoltageRangeQuiescent Current PerPackageTotal Supply Current(Dynamic PlusQuiescent, Per Package)V DD — V DD – 3.0 ≥ V SS ≥V EE3.0 18 3.0 — 18 3.0 18 VI DD 5.01015I D(AV) 5.01015CONTROL INPUT (Voltages Referenced to V SS )Low–Level Input Voltage V IL 5.01015High–Level Input Voltage V IH 5.01015Control Inputs: V in =V SS or V DD ,Switch I/O: V EE V I/O V DD , and ∆V switch——— 500 mV (5.)T A = 25 C only (Thechannel component,(V in – V out )/R on , isnot included.)R on = per spec,I off = per specR on = per spec,I off = per spec———5.010201.53.04.0———Typical———0.0050.0100.0155.01020———150300600µAµA(0.07 µA/kHz) f + I DD(0.20 µA/kHz) f + I DD(0.36 µA/kHz) f + I DDInput Leakage Current I in 15 V in = 0 or V DD — ±0.1 — ±0.00001 ±0.1 — ±1.0 µAInput Capacitance C in — — — — 5.0 7.5 — — pFSWITCHES IN/OUT AND COMMONS OUT/IN — W, X, Y, Z (Voltages Referenced to V EE )Recommended Peak–to–Peak Voltage Into or Outof the SwitchRecommended Static orDynamic Voltage Acrossthe Switch (5.) (Figure 3)3.57.011———3.57.0112.254.506.752.755.508.25V I/O — Channel On or Off 0 V DD 0 — V DD 0 V DD V p–p∆V switch — Channel On 0 600 0 — 600 0 300 mVOutput Offset Voltage V OO — V in = 0 V, No Load — — — 10 — — — µVON Resistance R on 5.01015∆ON Resistance BetweenAny Two Channelsin the Same PackageOff–Channel LeakageCurrent (Figure 8)∆R on 5.01015∆V switch 500 mV (5.) ,V in = V IL or V IH(Control), and V in =0 to V DD (Switch)I off 15 V in = V IL or V IH(Control) Channel toChannel or Any OneChannel—————800400220705045——————250120802510101.53.04.0———1050500280705045———3.57.011——————1.53.04.0———12005203001359565— ±100 — ±0.05 ±100 — ±1000 nACapacitance, Switch I/O C I/O — Switch Off — — — 10 — — — pFCapacitance, Common O/I C O/I — — — — 17 — — — pFCapacitance, Feedthrough(Channel Off)C I/O ——Pins Not AdjacentPins Adjacent4. Data labeled “Typ” is not to be used for design purposes, but is intended as an indication of the IC’s potential performance.5. For voltage drops across the switch (∆V switch ) > 600 mV ( > 300 mV at high temperature), excessive V DD current may be drawn; i.e. thecurrent out of the switch may contain both V DD and switch input components. The reliability of the device will be unaffected unless theMaximum Ratings are exceeded. (See first page of this data sheet.)——————0.150.47——————VVΩΩpFhttp://onsemi.com370

MC14551BELECTRICAL CHARACTERISTICS (C L = 50 pF, T A = 25 C, V EE V SS )CharacteristicÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPropagation Delay TimesSwitch Input to Switch Output (R L = 10 kΩ)t PLH , t PHL = (0.17 ns/pF) C L + 26.5 nst PLH , t PHL = (0.08 ns/pF) C L + 11 nst PLH , t PHL = (0.06 ns/pF) C L + 9.0 nsControl Input to Output (R L = 10 kΩ)V EE = V SS (Figure 4)Symbolt PLH , t PHL5.01015t PLH , t PHL5.01015V DD – V EEVdc Min Typ (6.) Max UnitSecond Harmonic Distortion— 10 — 0.07 — %R L = 10 kΩ, f = 1 kHz, V in = 5 V p–p——————351512350140100904030875350250nsnsBandwidth (Figure 5)R L = 1 kΩ, V in = 1/2 (V DD – V EE ) p–p ,20 Log (V out /V in ) = – 3 dB, C L = 50 pFOff Channel Feedthrough Attenuation, Figure 5R L = 1 kΩ, V in = 1/2 (V DD – V EE ) p–p ,f in = 55 MHzChannel Separation (Figure 6)R L = 1 kΩ, V in = 1/2 (V DD – V EE ) p–p ,f in = 3 MHzBW 10 — 17 — MHz— 10 — – 50 — dB— 10 — – 50 — dBCrosstalk, Control Input to Common O/I, Figure 7R1 = 1 kΩ, R L = 10 kΩ,Control t r = t f = 20 ns— 10 — 75 — mV6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.http://onsemi.com371

MC14551BV DDV DDV DDV EEIN/OUTOUT/INV DDLEVELCONVERTEDCONTROLIN/OUTOUT/INV EECONTROLFigure 1. Switch Circuit Schematic16 V DDCONTROL 9LEVELCONVERTERCONTROLW0 15W1 18 V SS 7V EE14 WX0 2X1 34 XY0 6Y1 105 YZ0 11Z1 1213 ZFigure 2. MC14551B Functional Diagramhttp://onsemi.com372

MC14551BTEST CIRCUITSCONTROLSECTIONOF ICON SWITCHVLOADPULSEGENERATORCONTROLR LC LV outSOURCEV DD V EE V EE V DDFigure 3. ∆V Across SwitchFigure 4. Propagation Delay Times,Control to OutputControl input used to turn ON or OFFthe switch under test.R LONCONTROLV outCONTROLR LC L = 50 pFOFFV outR LC L = 50 pFV inV DD – V EE2VDD – V EE2V inFigure 5. Bandwidth and Off–ChannelFeedthrough AttenuationFigure 6. Channel Separation(Adjacent Channels Used for Setup)OFF CHANNEL UNDER TESTV DDCONTROLR LV outC L = 50 pFCONTROLSECTIONOF ICOTHERCHANNEL(S)V EEV EEV DDR1V EEV DDFigure 7. Crosstalk, Control Inputto Common O/IFigure 8. Off Channel LeakageV DDKEITHLEY 160DIGITALMULTIMETER10 kV EE = V SSV DD1 kΩRANGEX/YPLOTTERFigure 9. Channel Resistance (R ON ) Test Circuithttp://onsemi.com373

MC14551BTYPICAL RESISTANCE CHARACTERISTICS350350RON, “ON” RESISTANCE (OHMS)30025020015010050T A = 125°C25°C–55°CRON, “ON” RESISTANCE (OHMS)30025020015010050T A = 125°C25°C–55°C0– 10 – 8.0 – 6.0 – 4.0 – 2.0 0 2.0 4.0 6.0 8.0 10V in , INPUT VOLTAGE (VOLTS)Figure 10. V DD @ 7.5 V, V EE @ – 7.5 V0– 10 – 8.0 – 6.0 – 4.0 – 2.0 0 2.0 4.0 6.0 8.0 10V in , INPUT VOLTAGE (VOLTS)Figure 11. V DD @ 5.0 V, V EE @ – 5.0 VRON, “ON” RESISTANCE (OHMS)700600500400300200100T A = 125°C25°C–55°CRON, “ON” RESISTANCE (OHMS)35030025020015010050T A = 25°CV DD = 2.5 V5.0 V7.5 V0– 10 – 8.0 – 6.0 – 4.0 – 2.0 0 2.0 4.0 6.0 8.0 10V in , INPUT VOLTAGE (VOLTS)Figure 12. V DD @ 2.5 V, V EE @ – 2.5 V0– 10 – 8.0 – 6.0 – 4.0 – 2.0 0 2.0 4.0 6.0 8.0 10V in , INPUT VOLTAGE (VOLTS)Figure 13. Comparison at 25 C, V DD @ – V EEhttp://onsemi.com374

MC14551BAPPLICATIONS INFORMATIONFigure A illustrates use of the on–chip level converterdetailed in Figure 2. The 0–to–5 volt Digital Control signalis used to directly control a 9 V p–p analog signal.The digital control logic levels are determined by V DDand V SS . The V DD voltage is the logic high voltage; the V SSvoltage is logic low. For the example, V DD = + 5 V = logichigh at the control inputs; V SS = GND = 0 V = logic low.The maximum analog signal level is determined by V DDand V EE . The V DD voltage determines the maximumrecommended peak above V SS . The V EE voltagedetermines the maximum swing below V SS . For theexample, V DD – V SS = 5 volt maximum swing above V SS ;V SS – V EE = 5 volt maximum swing below V SS . Theexample shows a ± 4.5 volt signal which allows a 1/2 volt+ 5 Vmargin at each peak. If voltage transients above V DD and/orbelow V EE are anticipated on the analog channels, externaldiodes (D x ) are recommended as shown in Figure B. Thesediodes should be small signal types able to absorb themaximum anticipated current surges during clipping.The absolute maximum potential difference betweenV DD and V EE is 18.0 volts. Most parameters are specifiedup to 15 volts which is the recommended maximumdifference between V DD and V EE .Balanced supplies are not required. However, V SS mustbe greater than or equal to V EE . For example, V DD =+ 10 volts, V SS = + 5 volts, and V EE = – 3 volts is acceptable.See the table below.–5 VV DD V SS V EE+ 4.5 V+ 5 V9 V p–pANALOG SIGNALSWITCHI/OCOMMONO/I9 V p–pANALOG SIGNALGNDEXTERNALCMOSDIGITALCIRCUITRY0–TO–5 V DIGITALCONTROL SIGNALCONTROLMC14551B– 4.5 VFigure A. Application ExampleV DDV DDD xSWITCHI/OCOMMONO/ID xD xD xV EEV EEFigure B. External Schottky or Germanium Clipping DiodesPOSSIBLE SUPPLY CONNECTIONSÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎV DDV SSV EEControl InputsLogic High/Logic LowIn VoltsMaximum Analog Signal RangeIn VoltsÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎIn Volts In Volts In Volts+ÎÎÎÎ8ÎÎÎÎ0 –ÎÎÎÎÎÎÎ8 +ÎÎÎÎÎÎÎÎÎÎ8/0 + 8 to – 8 = 16 V p–pÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ+ ÎÎÎÎ5 ÎÎÎÎ0 – ÎÎÎÎÎÎÎ12 + ÎÎÎÎÎÎÎÎÎÎ5/0 + 5 to – 12 = 17 V p–pÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ+ ÎÎÎÎ5 ÎÎÎÎ0 ÎÎÎÎÎÎÎ0 + ÎÎÎÎÎÎÎÎÎÎ5/0 + 5 to 0 = 5 V p–pÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ+ ÎÎÎÎ5 ÎÎÎÎ0 – ÎÎÎÎÎÎÎ5 + ÎÎÎÎÎÎÎÎÎÎ5/0 + 5 to – 5 = 10 V p–pÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ+ 10 ÎÎÎΖ ÎÎÎÎÎÎÎ5 + 10/ + ÎÎÎÎÎÎÎÎÎÎ5 + 10 to – 5 = 15 V p–pÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎhttp://onsemi.com375ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

The MC14553B 3–digit BCD counter consists of 3 negative edgetriggered BCD counters that are cascaded synchronously. A quad latchat the output of each counter permits storage of any given count. Theinformation is then time division multiplexed, providing one BCDnumber or digit at a time. Digit select outputs provide display control.All outputs are TTL compatible.An on–chip oscillator provides the low–frequency scanning clockwhich drives the multiplexer output selector.This device is used in instrumentation counters, clock displays,digital panel meters, and as a building block for general logicapplications.• TTL Compatible Outputs• On–Chip Oscillator• Cascadable• Clock Disable Input• Pulse Shaping Permits Very Slow Rise Times on Input Clock• Output Latches• Master ResetMAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 1.)Symbol Parameter Value UnitV DD DC Supply Voltage Range –0.5 to +18.0 VV in , V out Input or Output Voltage Range(DC or Transient)–0.5 to V DD + 0.5 Vhttp://onsemi.comPDIP–16P SUFFIXCASE 648SOIC–16DW SUFFIXCASE 751GA = Assembly LocationWL or L = Wafer LotYY or Y = YearWW or W = Work WeekMARKINGDIAGRAMS161MC14553BCPAWLYYWW16114553BAWLYYWWI inI outInput Current(DC or Transient) per PinOutput Current(DC or Transient) per Pin±10 mA+20 mAORDERING INFORMATIONDevice Package ShippingP DPower Dissipation,per Package (Note 2.)500 mWT A Ambient Temperature Range –55 to +125 °CT stg Storage Temperature Range –65 to +150 °CT LLead Temperature(8–Second Soldering)260 °C1. Maximum Ratings are those values beyond which damage to the devicemay occur.2. Temperature Derating:Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 CMC14553BCP PDIP–16 25/RailMC14553BDW SOIC–16 47/RailThis device contains protection circuitry to guard against damage due to highstatic voltages or electric fields. However, precautions must be taken to avoidapplications of any voltage higher than maximum rated voltages to thishigh–impedance circuit. For proper operation, V in and V out should be constrainedto the range V SS (V in or V out ) V DD .Unused inputs must always be tied to an appropriate logic voltage level (e.g.,either V SS or V DD ). Unused outputs must be left open.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 3376 Publication Order Number:MC14553B/D

MC14553BBLOCK DIAGRAM4 3CIACIBQ0912CLOCKQ17101113LEDISMRQ2Q3O.F.DS1DS2DS365142115V DD = PIN 16V SS = PIN 8TRUTH TABLEInputsMasterReset Clock Disable LE Outputs0 0 0 No Change0 0 0 Advance0 X 1 X No Change0 1 0 Advance0 1 0 No Change0 0 X X No Change0 X X Latched0 X X 1 Latched1 X X 0 Q0 = Q1 = Q2 = Q3 = 0X = Don’t Carehttp://onsemi.com377

MC14553BELECTRICAL CHARACTERISTICS (Voltages Referenced to V SS )– 55 C 25 C 125 CV DDVdc Min Max Min Typ (3.) Max Min Max UnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCharacteristicOutput VoltageV in = V DD or 0“0” LevelSymbolV OL 5.01015V 5.0“1” LevelV in = 0 or V DDOH1015Input Voltage“0” Level(V O = 4.5 or 0.5 Vdc)(V O = 9.0 or 1.0 Vdc)(V O = 13.5 or 1.5 Vdc)(V O = 0.5 or 4.5 Vdc)(V O = 1.0 or 9.0 Vdc)(V O = 1.5 or 13.5 Vdc)“1” LevelOutput Drive Current(V OH = 4.6 Vdc) Source —(V OH = 9.5 Vdc) Pin 3(V OH = 13.5 Vdc)(V OH = 4.6 Vdc) Source —(V OH = 9.5 Vdc) Other(V OH = 13.5 Vdc) Outputs(V OL = 0.4 Vdc) Sink —(V OL = 0.5 Vdc) Pin 3(V OL = 1.5 Vdc)(V OL = 0.4 Vdc) Sink — Other(V OL = 0.5 Vdc) Outputs(V OL = 1.5 Vdc)V IL5.01015V IH5.01015I OH5.010155.01015I OL 5.010155.01015———4.959.9514.95———3.57.011– 0.25– 0.62– 1.8– 0.64– 1.6– 4.20.51.11.83.06.0180.050.050.05———1.53.04.0————————————4.959.9514.95———3.57.011– 0.2– 0.5– 1.5– 0.51– 1.3– 3.40005.010152.254.506.752.755.508.25– 0.36– 0.9– 3.5– 0.88– 2.25– 8.80.050.050.05———1.53.04.0—————————4.959.9514.95Input Current I in 15 — ±0.1 — ±0.00001 ±0.1 — ±1.0 µAdcInput Capacitance(V in = 0)——————0.40.91.52.55.0150.882.258.8—————————3.57.0110.140.351.1– 0.36– 0.9– 2.40.280.651.200.050.050.05C in — — — — 5.0 7.5 — — pF4.08.020———1.63.510———1.53.04.0———————————————VdcVdcVdcVdcmAdcmAdcmAdcmAdcQuiescent CurrentI DD 5.0MR = V DD 15(Per Package)10Total Supply Current (4.) (5.)(Dynamic plus Quiescent,Per Package)(C L = 50 pF on all outputs, allbuffers switching)I T 5.01015———5.01020———0.0100.0200.0305.01020I T = (0.35 µA/kHz) f + I DDI T = (0.85 µA/kHz) f + I DDI T = (1.50 µA/kHz) f + I DD3. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.4. The formulas given are for the typical characteristics only at 25 C.5. To calculate total supply current at loads other than 50 pF:I T (C L ) = I T (50 pF) + (C L – 50) Vfkwhere: I T is in µA (per package), C L in pF, V = (V DD – V SS ) in volts, f in kHz is input frequency, and k = 0.004.———150300600µAdcµAdchttp://onsemi.com378

MC14553BSWITCHING CHARACTERISTICS (6.) (C L = 50 pF, T A = 25 C)Characteristic Figure Symbol V DD Min Typ (7.) Max UnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Rise and Fall Timet TLH , t THL = (1.5 ns/pF) C L + 25 nst TLH , t THL = (0.75 ns/pF) C L + 12.5 nst TLH , t THL = (0.55 ns/pF) C L + 9.5 ns2a t TLH ,t THL 5.01015Clock to BCD Out 2a t PLH , 5.0t PHL 1015Clock to Overflow 2a t PHL 5.01015Reset to BCD Out 2b t PHL 5.01015Clock to Latch Enable Setup TimeMaster Reset to Latch Enable Setup TimeRemoval TimeLatch Enable to Clock2b t su 5.010152b t rem 5.01015Clock Pulse Width 2a t WH(cl) 5.01015Reset Pulse Width 2b t WH(R) 5.01015Reset Removal Time — t rem 5.01015Input Clock Frequency 2a f cl 5.01015Input Clock Rise Time 2b t TLH 5.01015Disable, MR, Latch EnableRise and Fall TimesScan Oscillator Frequency(C1 measured in µF)— t TLH , 5.0t THL 10151 f osc 5.01015————————————600400200– 80– 1005502001501200600450– 80020—————————1005040900500200600400200900500300300200100– 200– 70– 5027510075600300225– 180– 50– 301.55.07.0NoLimit———1.5/C14.2/C17.0/C16. The formulas given are for the typical characteristics only at 25 C.7. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.2001008018001000400120080040018001000600———————————————0.92.53.5155.04.0———nsnsnsnsnsnsnsnsnsMHznsµsHzhttp://onsemi.com379

MC14553BUNITS CLOCK101112131415161712345678986878889909192939495969798991001018999009019909919929939949959969979989991000UNITS Q0UNITS Q1UNITS Q2UNITS Q3TENS CLOCKTENS Q0TENS Q3HUNDREDSCLOCKHUNDREDS Q0HUNDREDS Q3DISABLE(DISABLES CLOCK WHEN HIGH)UP AT 80 UP AT 980UP AT 800OVERFLOWMASTERRESETSCANOSCILLATORDIGIT SELECT 1DIGIT SELECT 2DIGIT SELECT 3UNITSTENSHUNDREDSFigure 1. 3–Digit Counter Timing Diagram (Reference Figure 3)(a)PULSEGENERATOR(b)GENERATOR1GENERATOR2GENERATOR3CLEDISMRCLEMRDIS16 V DDQ3Q2Q1Q0O.F.DS1DS2DS38 V SSV DDQ3Q2Q1Q0O.F.DS1DS2DS3V SSC LC LC LC LC LC LC LC LC LC L20 nst WL(cl)20 ns90%CLOCK10%50%t PLHt PHLBCD OUT10% 90%t TLH50%t THLOVERFLOWCLOCKLATCHENABLEBCD OUTMASTER RESET50%t sut TLH90%10%50%50%t PHL , t PLHt rem999100050%1/f clt PHL50%t sut PHLFigure 2. Switching Time Test Circuits and Waveformst WH(R)http://onsemi.com380

MC14553BOPERATING CHARACTERISTICSThe MC14553B three–digit counter, shown in Figure 3,consists of three negative edge–triggered BCD counterswhich are cascaded in a synchronous fashion. A quad latchat the output of each of the three BCD counters permitsstorage of any given count. The three sets of BCD outputs(active high), after going through the latches, are timedivision multiplexed, providing one BCD number or digit ata time. Digit select outputs (active low) are provided fordisplay control. All outputs are TTL compatible.An on–chip oscillator provides the low frequencyscanning clock which drives the multiplexer output selector.The frequency of the oscillator can be controlled externallyby a capacitor between pins 3 and 4, or it can be overriddenand driven with an external clock at pin 4. Multiple devicescan be cascaded using the overflow output, which providesone pulse for every 1000 counts.The Master Reset input, when taken high, initializes thethree BCD counters and the multiplexer scanning circuit.While Master Reset is high the digit scanner is set to digitone; but all three digit select outputs are disabled to prolongdisplay life, and the scan oscillator is inhibited. The Disableinput, when high, prevents the input clock from reaching thecounters, while still retaining the last count. A pulse shapingcircuit at the clock input permits the counters to continueoperating on input pulses with very slow rise times.Information present in the counters when the latch inputgoes high, will be stored in the latches and will be retainedwhile the latch input is high, independent of other inputs.Information can be recovered from the latches after thecounters have been reset if Latch Enable remains highduring the entire reset cycle.LATCH ENABLE10SCANROSCILLATORC1 A43C1 BC1PULSEGENERATORCLOCK12RSCANNERPULSESHAPERCRQ0Q1Q2÷ 10Q3UNITSQUADLATCH9Q011DISABLE(ACTIVEHIGH)CR÷ 10TENSQ0Q1Q2Q3QUADLATCHMULTIPLEXER7Q16Q2BCDOUTPUTS(ACTIVEHIGH)Q0CQ1Q2R÷ 10 Q3HUNDREDSQUADLATCH5Q32 1 15DS1 DS2 DS313 14(LSD) DIGIT SELECT (MSD)MROVERFLOW(ACTIVE LOW)(ACTIVE HIGH)Figure 3. Expanded Block Diagramhttp://onsemi.com381

MC14553BSTROBERESETCLOCKINPUTVDD121110 1310 13LE MR4LE MRC1A 0.00112C1ACLKCLK3 µ FMC14553BC1 BMC14553B C1B11DIS14DISO.F.O.F.Q3 Q2 Q1 Q0 DS3 DS2 DS1Q3 Q2 Q1 Q0 DS3 DS2 DS15 6 7 9 15 1 25 6 7 9 15 1 2VDDVDD5324617ABCDPhLDBIMC14543B5324617ABCDPhLDBIMC14543Bgabcde9101112131514LSDDISPLAYS ARE LOW CURRENT LEDs(I peak < 10 mA PER SEGMENT)MSD4314abcgde9101112131514ffFigure 4. Six–Digit Displayhttp://onsemi.com382

The MC14555B and MC14556B are constructed withcomplementary MOS (CMOS) enhancement mode devices. EachDecoder/Demultiplexer has two select inputs (A and B), an active lowEnable input (E), and four mutually exclusive outputs (Q0, Q1, Q2,Q3). The MC14555B has the selected output go to the “high” state,and the MC14556B has the selected output go to the “low” state.Expanded decoding such as binary–to–hexadecimal (1–of–16), etc.,can be achieved by using other MC14555B or MC14556B devices.Applications include code conversion, address decoding, memoryselection control, and demultiplexing (using the Enable input as a datainput) in digital data transmission systems.• Diode Protection on All Inputs• Active High or Active Low Outputs• Expandable• Supply Voltage Range = 3.0 Vdc to 18 Vdc• All Outputs Buffered• Capable of Driving Two Low–Power TTL Loads or One Low–PowerSchottky TTL Load Over the Rated Temperature Rangehttp://onsemi.comPDIP–16P SUFFIXCASE 648SOIC–16D SUFFIXCASE 751BSOEIAJ–16F SUFFIXCASE 966MARKINGDIAGRAMS16116116MC1455XBCPAWLYYWW1455XBAWLYWWMC1455XBAWLYWW1MAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 2.)Symbol Parameter Value UnitV DD DC Supply Voltage Range –0.5 to +18.0 VV in , V out Input or Output Voltage Range(DC or Transient)–0.5 to V DD + 0.5 VI in , I outP DInput or Output Current(DC or Transient) per PinPower Dissipation,per Package (Note 3.)±10 mA500 mWT A Ambient Temperature Range –55 to +125 °CT stg Storage Temperature Range –65 to +150 °CT LLead Temperature(8–Second Soldering)260 °C2. Maximum Ratings are those values beyond which damage to the devicemay occur.3. Temperature Derating:Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 CThis device contains protection circuitry to guard against damage due to highstatic voltages or electric fields. However, precautions must be taken to avoidapplications of any voltage higher than maximum rated voltages to thishigh–impedance circuit. For proper operation, V in and V out should be constrainedto the range V SS (V in or V out ) V DD .Unused inputs must always be tied to an appropriate logic voltage level (e.g.,either V SS or V DD ). Unused outputs must be left open.X = Specific Device CodeA = Assembly LocationWL or L = Wafer LotYY or Y = YearWW or W = Work WeekORDERING INFORMATIONDevice Package ShippingMC14555BCP PDIP–16 2000/BoxMC14555BD SOIC–16 48/RailMC14555BDR2 SOIC–16 2500/Tape & ReelMC14555BF SOEIAJ–16 See Note 1.MC14555BFEL SOEIAJ–16 See Note 1.MC14556BCP PDIP–16 2000/BoxMC14556BD SOIC–16 48/RailMC14556BDR2 SOIC–16 2500/Tape & ReelMC14556BF SOEIAJ–16 See Note 1.MC14556BFEL SOEIAJ–16 See Note 1.1. For ordering information on the EIAJ version ofthe SOIC packages, please contact your localON Semiconductor representative.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 3383 Publication Order Number:MC14555B/D

MC14555B, MC14556BMC14555BPIN ASSIGNMENTSMC14556BE AA A121615V DDE BE AA A121615B A 3 14 A BB A 3 14Q0 A 4 13 B BQ0 A 4 13Q1 A 5 12 Q0 BQ1 A 5 12Q2 A 6 11 Q1 BQ2 A 6 11Q3 A 7 10 Q2 BQ3 A 7 10V SS 8 9 Q3 BV SS 8 9V DDE BA BB BQ0 BQ1 BQ2 BQ3 BTRUTH TABLEInputsOutputsEnable Select MC14555B MC14556BE B A Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q00 0 0 0 0 0 1 1 1 1 00 0 1 0 0 1 0 1 1 0 10 1 0 0 1 0 0 1 0 1 10 1 1 1 0 0 0 0 1 1 11 X X 0 0 0 0 1 1 1 1X = Don’t CareMC14555BBLOCK DIAGRAMMC14556B2 A Q0 4Q1 53 BQ2 61 EQ3 72 A Q0 4Q1 53 BQ2 61 EQ3 7141315ABEQ0Q1Q2Q31211109141315ABEQ0Q1Q2Q31211109V DD = PIN 16V SS = PIN 8http://onsemi.com384

MC14555B, MC14556BELECTRICAL CHARACTERISTICS (Voltages Referenced to V SS )– 55 C 25 C 125 CV DDVdc Min Max Min Typ (4.) Max Min Max UnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCharacteristicOutput VoltageV in = V DD or 0“0” LevelSymbolV OL 5.01015V 5.0“1” LevelV in = 0 or V DDOH1015Input Voltage“0” Level(V O = 4.5 or 0.5 Vdc)(V O = 9.0 or 1.0 Vdc)(V O = 13.5 or 1.5 Vdc)(V O = 0.5 or 4.5 Vdc)(V O = 1.0 or 9.0 Vdc)(V O = 1.5 or 13.5 Vdc)“1” LevelOutput Drive Current(V OH = 2.5 Vdc) Source(V OH = 4.6 Vdc)(V OH = 9.5 Vdc)(V OH = 13.5 Vdc)(V OL = 0.4 Vdc) Sink(V OL = 0.5 Vdc)(V OL = 1.5 Vdc)V IL5.01015V IH5.01015I OH5.05.01015I OL 5.01015———4.959.9514.95———3.57.011– 3.0– 0.64– 1.6– 4.20.641.64.20.050.050.05———1.53.04.0——————————4.959.9514.95———3.57.011– 2.4– 0.51– 1.3– 3.40005.010152.254.506.752.755.508.25– 4.2– 0.88– 2.25– 8.80.050.050.05———1.53.04.0——————————4.959.9514.95———3.57.011– 1.7– 0.36– 0.9– 2.4Input Current I in 15 — ±0.1 — ±0.00001 ±0.1 — ±1.0 µAdcInput Capacitance(V in = 0)———0.511.33.40.882.258.80.050.050.05C in — — — — 5.0 7.5 — — pF———0.360.92.4———1.53.04.0——————————VdcVdcVdcVdcmAdcmAdcQuiescent Current(Per Package)Total Supply Current (5.) (6.)(Dynamic plus Quiescent,Per Package)(C L = 50 pF on all outputs, allbuffers switching)I DD 5.01015I T 5.01015———5.01020———0.0050.0100.0155.01020I T = (0.85 µA/kHz) f + I DDI T = (1.70 µA/kHz) f + I DDI T = (2.60 µA/kHz) f + I DD4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.5. The formulas given are for the typical characteristics only at 25 C.6. To calculate total supply current at loads other than 50 pF:I T (C L ) = I T (50 pF) + (C L – 50) Vfkwhere: I T is in µA (per package), C L in pF, V = (V DD – V SS ) in volts, f in kHz is input frequency, and k = 0.002.———150300600µAdcµAdchttp://onsemi.com385

MC14555B, MC14556BSWITCHING CHARACTERISTICS (7.) (C L = 50 pF, T A = 25 C)Characteristic Symbol V DD Min Typ (8.) Max UnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Rise and Fall Timet TLH , t THL = (1.5 ns/pF) C L + 25 nst TLH , t THL = (0.75 ns/pF) C L + 12.5 nst TLH , t THL = (0.55 ns/pF) C L + 9.5 nsPropagation Delay Time — A, B to Outputt PLH , t PHL = (1.7 ns/pF) C L + 135 nst PLH , t PHL = (0.66 ns/pF) C L + 62 nst PLH , t PHL = (0.5 ns/pF) C L + 45 nsPropagation Delay Time — E to Outputt PLH , t PHL = (1.7 ns/pF) C L + 115 nst PLH , t PHL = (0.66 ns/pF) C L + 52 nst PLH , t PHL = (0.5 ns/pF) C L + 40 nst TLH ,t THL 5.01015t PLH ,t PHL 5.01015t PLH ,t PHL 5.010157. The formulas given are for the typical characteristics only at 25 C.8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.—————————10050402209570200856520010080440190140400170130nsnsnsA INPUTS(50% DUTY CYCLE)B INPUTS(50% DUTY CYCLE)OUTPUT Q1INPUT E LOW20 ns 20 ns90%50%10%All 8 outputs connect to respective C L loads.f in respect to a system clock.12fV DDV SSV DDV SSV OHV OLINPUT A HIGH, INPUT E LOW20 ns 20 nsINPUT Bt PHLOUTPUT Q3MC14556Bt THLt PLHOUTPUT Q3MC14555Bt TLH90%50%10%90%50%10%90%50%10%t PLHt TLHt PHLV DDV SSV OHV OLV OHV OLtTHLFigure 1. Dynamic Power Dissipation Signal WaveformsFigure 2. Dynamic Signal WaveformsLOGIC DIAGRAM(1/2 of Dual)*Q0A*Q1B*Q2E*Q3*Eliminated for MC14555Bhttp://onsemi.com386

The MC14557B is a static clocked serial shift register whose lengthmay be programmed to be any number of bits between 1 and 64. Thenumber of bits selected is equal to the sum of the subscripts of theenabled Length Control inputs (L1, L2, L4, L8, L16, and L32) plusone. Serial data may be selected from the A or B data inputs with theA/B select input. This feature is useful for recirculation purposes. AClock Enable (CE) input is provided to allow gating of the clock ornegative edge clocking capability.The device can be effectively used for variable digital delay lines orsimply to implement odd length shift registers.• 1–64 Bit Programmable Length• Q and Q Serial Buffered Outputs• Asynchronous Master Reset• All Inputs Buffered• No Limit On Clock Rise and Fall Times• Supply Voltage Range = 3.0 Vdc to 18 Vdc• Capable of Driving Two Low–power TTL Loads or one Low–powerSchottky TTL Load Over the Rated Temperature RangeMAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 2.)Symbol Parameter Value UnitV DD DC Supply Voltage Range –0.5 to +18.0 VV in , V out Input or Output Voltage Range(DC or Transient)–0.5 to V DD + 0.5 VI in , I outP DInput or Output Current(DC or Transient) per PinPower Dissipation,per Package (Note 3.)±10 mA500 mWT A Ambient Temperature Range –55 to +125 °CT stg Storage Temperature Range –65 to +150 °CT LLead Temperature(8–Second Soldering)260 °C2. Maximum Ratings are those values beyond which damage to the devicemay occur.3. Temperature Derating:Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 CThis device contains protection circuitry to guard against damage due to highstatic voltages or electric fields. However, precautions must be taken to avoidapplications of any voltage higher than maximum rated voltages to thishigh–impedance circuit. For proper operation, V in and V out should be constrainedto the range V SS (V in or V out ) V DD .Unused inputs must always be tied to an appropriate logic voltage level (e.g.,either V SS or V DD ). Unused outputs must be left open.http://onsemi.comPDIP–16P SUFFIXCASE 648SOIC–16DW SUFFIXCASE 751GSOEIAJ–16F SUFFIXCASE 966A = Assembly LocationWL or L = Wafer LotYY or Y = YearWW or W = Work WeekORDERING INFORMATIONMARKINGDIAGRAMS16Device Package ShippingMC14557BCP PDIP–16 2000/BoxMC14557BDW SOIC–16 47/Rail1MC14557BCPAWLYYWW16114557BAWLYYWWMC14557BDWR2 SOIC–16 1000/Tape & ReelMC14557BF SOEIAJ–16 See Note 1.MC14557BFEL SOEIAJ–16 See Note 1.1. For ordering information on the EIAJ version ofthe SOIC packages, please contact your localON Semiconductor representative.161MC14557BAWLYWW© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 3387 Publication Order Number:MC14557B/D

MC14557BPIN ASSIGNMENTL2116V DDL1215L4RESET314L8CLOCK413L16CE512L32B611QV SSA78109QA/B SELBLOCK DIAGRAM3456792115141312RESETCLOCKCEBAA/B SELECTL1L2L4L8L16L32QQ1011V DD = PIN 16V SS = PIN 8TRUTH TABLEInputsOutputRst A/B Clock CE Q0 0 0 B0 1 0 A0 0 1 B0 1 1 A1 X X X 0Q is the output of the first selected shiftregister stage.X = Don’t CareLENGTH SELECT TRUTH TABLEL32 L16 L8 L4 L2 L1 Register Length0000000000011 Bit2 Bits0000103 Bits0000114 Bits0001005 Bits0001016 Bits11000000000133 Bits34 Bits1 1 1 1 0 0 61 Bits1 1 1 1 1 1 62 Bits1 1 1 1 1 0 63 Bits1 1 1 1 0 1 64 BitsNOTE: Length equals the sum of the binary length controlsubscripts plus one.http://onsemi.com388

MC14557BELECTRICAL CHARACTERISTICS (Voltages Referenced to V SS )– 55 C 25 C 125 CV DDVdc Min Max Min Typ (4.) Max Min Max UnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCharacteristicOutput VoltageV in = V DD or 0“0” LevelSymbolV OL 5.01015V 5.0“1” LevelV in = 0 or V DDOH1015Input Voltage“0” Level(V O = 4.5 or 0.5 Vdc)(V O = 9.0 or 1.0 Vdc)(V O = 13.5 or 1.5 Vdc)(V O = 0.5 or 4.5 Vdc)(V O = 1.0 or 9.0 Vdc)(V O = 1.5 or 13.5 Vdc)“1” LevelOutput Drive Current(V OH = 2.5 Vdc) Source(V OH = 4.6 Vdc)(V OH = 9.5 Vdc)(V OH = 13.5 Vdc)(V OL = 0.4 Vdc) Sink(V OL = 0.5 Vdc)(V OL = 1.5 Vdc)V IL5.01015V IH5.01015I OH5.05.01015I OL 5.01015———4.959.9514.95———3.57.011– 3.0– 0.64– 1.6– 4.20.641.64.20.050.050.05———1.53.04.0——————————4.959.9514.95———3.57.011– 2.4– 0.51– 1.3– 3.40005.010152.254.506.752.755.508.25– 4.2– 0.88– 2.25– 8.80.050.050.05———1.53.04.0——————————4.959.9514.95———3.57.011– 1.7– 0.36– 0.9– 2.4Input Current I in 15 — ±0.1 — ±0.00001 ±0.1 — ±1.0 µAdcInput Capacitance(V in = 0)———0.511.33.40.882.258.80.050.050.05C in — — — — 5.0 7.5 — — pF———0.360.92.4———1.53.04.0——————————VdcVdcVdcVdcmAdcQuiescent Current(Per Package)Total Supply Current (5.) (6.)(Dynamic plus Quiescent,Per Package)(C L = 50 pF on all outputs, allbuffers switching)I DD 5.01015I T 5.01015———5.01020———0.0100.0200.0305.01020I T = (1.75 µA/kHz) f + I DDI T = (3.50 µA/kHz) f + I DDI T = (5.25 µA/kHz) f + I DD4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.5. The formulas given are for the typical characteristics only at 25 C.6. To calculate total supply current at loads other than 50 pF:I T (C L ) = I T (50 pF) + (C L – 50) Vfkwhere: I T is in µA (per package), C L in pF, V = (V DD – V SS ) in volts, f in kHz is input frequency, and k = 0.001.———150300600µAdcµAdchttp://onsemi.com389

MC14557BSWITCHING CHARACTERISTICS (7.) (C L = 50 pF, T A = 25 C)Characteristic Symbol V DD Min Typ (8.) Max UnitRise and Fall Time, Q or Q Outputt TLH , t THL = (1.5 ns/pF) C L + 25 nst TLH , t THL = (0.75 ns/pF) C L + 12.5 nst TLH , t THL = (0.55 ns/pF) C L + 9.5 nst TLH ,t THL 51015———100504020010080nsÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPropagation Delay, Clock or CE to Q or Qt PLH , t PHL = (1.7 ns/pF) C L + 215 nst PLH , t PHL = (0.66 ns/pF) C L + 97 nst PLH , t PHL = (0.5 ns/pF) C L + 65 nsPropagation Delay, Reset to Q or Qt PLH , t PHL = (1.7 ns/pF) C L + 215 nst PLH , t PHL = (0.66 ns/pF) C L + 97 nst PLH , t PHL = (0.5 ns/pF) C L + 70 nst PLH ,t PHL 51015t PLH ,t PHL 51015Pulse Width, Clock t WH(cl) 51015Pulse Width, Reset t WH(rst) 51015Clock Frequency (50% Duty Cycle) f cl 51015Setup Time, A or B to Clock or CEWorst case condition: L1 = L2 = L4 = L8 =L16 = L32 = V SS (Register Length = 1)Best case condition: L32 = V DD , L1 through L16 =Don’t Care (Any register length from 33 to 64)Hold Time, Clock or CE to A or BBest case condition: L1 = L2 = L4 = L8 = L16 =L32 = V SS (Register Length = 1)Worst case condition: L32 = V DD , L1 through L16 =Don’t Care (Any register length from 33 to 64)t su5101551015t h5101551015Rise and Fall Time, Clock t r ,5t f 1015Rise and Fall Time, Reset or CE t r ,5t f 1015Removal Time, Reset to Clock or CE t rem 51015——————20010075300140100———700290145400165602001001040018585300130903001309595453515070503.07.513.0350130854550– 150– 60– 50502522No Limit7. The formulas given are for the typical characteristics only at 25 C.8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.———1608070———804035600260180600260190——————1.75.06.7————————————1554———nsnsnsnsMHznsns—µsnshttp://onsemi.com390

MC14557BTIMING DIAGRAMCLOCK50%t WH(cl)V DDV SSA INPUTRESET1–bit length:CE = 0A/B = 1 QL1 = L2 = L4 = L8 = L16 = L32 = 01/f cl50%t sut h50%t TLH t THL PW R90%50%10%t PLH t PHLt PHLt remV DDV SSV DDV SSV OHV OLhttp://onsemi.com391

MC14557BLOGIC DIAGRAMCECLOCKRESETABA/BSELECT543769C R32 BIT12L32C R2 BIT1L2C R16 BIT13L16C R1 BIT2L1C R8 BIT14L8C R1 BITC R4 BIT15L410Q11QVDD= PIN 16VSS= PIN 8http://onsemi.com392

The MC14562B is a 128–bit static shift register constructed withMOS P–channel and N–channel enhancement mode devices in asingle monolithic structure. Data is clocked in and out of the shiftregister on the positive edge of the clock input. Data outputs areavailable every 16 bits, from 16 through bit 128. This complementaryMOS shift register is primarily used where low power dissipationand/or high noise immunity is desired.• Diode Protection on All Inputs• Fully Static Operation• Cascadable to Provide Longer Shift Register Lengths• Supply Voltage Range = 3.0 Vdc to 18 Vdc• Capable of Driving Two Low–power TTL Loads or One Low–powerSchottky TTL Load Over the Rated Temperature RangeMAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 1.)Symbol Parameter Value UnitV DD DC Supply Voltage Range –0.5 to +18.0 VV in , V out Input or Output Voltage Range(DC or Transient)–0.5 to V DD + 0.5 Vhttp://onsemi.comPDIP–14P SUFFIXCASE 64614A = Assembly LocationWL or L = Wafer LotYY or Y = YearWW or W = Work WeekMARKINGDIAGRAMS1MC14562BCPAWLYYWWI in , I outP DInput or Output Current(DC or Transient) per PinPower Dissipation,per Package (Note 2.)±10 mA500 mWT A Ambient Temperature Range –55 to +125 °CT stg Storage Temperature Range –65 to +150 °CT LLead Temperature(8–Second Soldering)260 °C1. Maximum Ratings are those values beyond which damage to the devicemay occur.2. Temperature Derating:Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 CORDERING INFORMATIONDevice Package ShippingMC14562BCP PDIP–14 25/RailThis device contains protection circuitry to guard against damage due to highstatic voltages or electric fields. However, precautions must be taken to avoidapplications of any voltage higher than maximum rated voltages to thishigh–impedance circuit. For proper operation, V in and V out should be constrainedto the range V SS (V in or V out ) V DD .Unused inputs must always be tied to an appropriate logic voltage level (e.g.,either V SS or V DD ). Unused outputs must be left open.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 3393 Publication Order Number:MC14562B/D

MC14562BPIN ASSIGNMENTQ64114V DDQ96213Q32Q128312DATANC411NCCLOCK510Q16Q11269Q48V SS78Q80NC = NO CONNECTIONBLOCK DIAGRAM125DATACLOCKQ16Q32Q48Q64Q80Q96Q112Q1281013918263Pins 4 and 11not used.V DD = PIN 14V SS = PIN 7CLOCK 5LOGIC DIAGRAMDATA IN 12D QCDCQDCQDCQD QC1 2 3 16 17 32 33 48 49 64DCQDCQDCQDCQDCQ10 Q16D QCDCQDC65 80 81 96QDCQD QC97D QC112D QC113D QC12813 Q329 Q481 Q648 Q802 Q966 Q1123 Q128http://onsemi.com394

MC14562BELECTRICAL CHARACTERISTICS (Voltages Referenced to V SS )– 55 C 25 C 125 CV DDVdc Min Max Min Typ (3.) Max Min Max UnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCharacteristicOutput VoltageV in = V DD or 0“0” LevelSymbolV OL 5.01015V 5.0“1” LevelV in = 0 or V DDOH1015Input Voltage“0” Level(V O = 4.5 or 05 Vdc)(V O = 9.0 or 1.0 Vdc)(V O = 13.5 or 1.5 Vdc)(V O = 0.5 or 4.5 Vdc)(V O = 1.0 or 9.0 Vdc)(V O = 1.5 or 13.5 Vdc)“1” LevelOutput Drive Current(V OH = 2.5 Vdc) Source(V OH = 4.6 Vdc)(V OH = 9.5 Vdc)(V OH = 13.5 Vdc)(V OL = 0.4 Vdc) Sink(V OL = 0.5 Vdc)(V OL = 1.5 Vdc)V IL5.01015V IH5.01015I OH5.05.01015I OL 5.01015———4.959.9514.95———3.57.011– 3.0– 0.64– 1.6– 4.20.641.64.20.050.050.05———1.53.04.0——————————4.959.9514.95———3.57.011– 2.4– 0.51– 1.3– 3.40005.010152.254.506.752.755.508.25– 4.2– 0.88– 2.25– 8.80.050.050.05———1.53.04.0——————————4.959.9514.95———3.57.011– 1.7– 0.36– 0.9– 2.4Input Current I in 15 — ±0.1 — ±0.00001 ±0.1 — ±1.0 µAdcInput Capacitance(V in = 0)———0.511.33.40.882.258.80.050.050.05C in — — — — 5.0 7.5 — — pF———0.360.92.4———1.53.04.0——————————VdcVdcVdcVdcmAdcmAdcQuiescent Current(Per Package)Total Supply Current (4.) (5.)(Dynamic plus Quiescent,Per Package)(C L = 50 pF on all outputs, allbuffers switching)I DD 5.01015I T 5.01015———5.01020———0.0100.0200.0305.01020I T = (1.94 µA/kHz) f + I DDI T = (3.81 µA/kHz) f + I DDI T = (5.52 µA/kHz) f + I DD3. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.4. The formulas given are for the typical characteristics only at 25 C.5. To calculate total supply current at loads other than 50 pF:I T (C L ) = I T (50 pF) + (C L – 50) Vfkwhere: I T is in µA (per package), C L in pF, V = (V DD – V SS ) in volts, f in kHz is input frequency, and k = 0.004.———150300600µAdcµAdchttp://onsemi.com395

MC14562BSWITCHING CHARACTERISTICS (6.) (C L = 50 pF, T A = 25 C)Characteristic Symbol V DD Min Typ (7.) Max UnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Rise and Fall Timet TLH , t THL = (1.5 ns/pF) C L + 25 nst TLH , t THL = (0.75 ns/pF) C L + 12.5 nst TLH , t THL = (0.55 ns/pF) C L + 9.5 nsPropagation Delay TimeClock to Qt PLH , t PHL = (1.7 ns/pF) C L + 515 nst PLH , t PHL = (0.66 ns/pF) C L + 217 nst PLH , t PHL = (0.5 ns/pF) C L + 145 nst TLH ,t THL 5.01015t PLH ,t PHL5.01015——————1005040600250170200100801200500340nsnsClock Pulse Width(50% Duty Cycle)t WH 5.01015Clock Pulse Frequency f cl 5.01015Data to Clock Setup Time t su(1) 5.01015t su(0) 5.01015Data to Clock Hold Time t h(1) 5.01015t h(0) 5.01015Clock Input Rise and Fall Times t r , t f 5.010156. The formulas given are for the typical characteristics only at 25 C.7. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.600220150———– 20– 100– 20– 100350165155350200140———300110751.95.68.0– 170– 64– 60– 91– 58– 4826310910026714093——————1.13.04.0————————————1554nsMHznsnsnsnsµshttp://onsemi.com396

MC14562BV DDDATACLOCKQ16Q32Q48Q64Q80Q96Q112Q1287V SSC L C L C L C L C L C L C L C LI D 500 µFf oCLOCKDATA(f = 1/2 f o )V DDV SSV DDV SSFigure 1. Power Dissipation Test Circuit and Waveformshttp://onsemi.com397

MC14562BTIMING DIAGRAMPINNO.’SCLOCK 5PULSE 1PULSE 16 PULSE 32 PULSE 128DATA IN 12Q16 10Q32 13Q28 3AC TEST WAVEFORMSCLOCKPULSE 1 PULSE 2 PULSE 16 PULSE 1750% 50% 50%90%10%50%t WHt WLt rt fV DDV SSDATA IN50% 50%V DDV SSQ16CLOCK50%10%t PHLt THLPULSE 1 PULSE 2 PULSE 16 PULSE 1750% 50% 50%50%t WHt WL90%V DDV SSV DDV SSDATA IN50% 50%t su(1)t h(1)50%V DDV SSQ1690%10%V DDt PLHt THLV SSNOTE: The remaining Data–Bit Outputs (Q32, Q48, Q64, Q80, Q96, Q112 and Q128) will occur at Clock Pulse 32, 48, 64, 80,96, 112, 128 in the same relationship as Q16.http://onsemi.com398

The MC14569B is a programmable divide–by–N dual 4–bit binaryor BCD down counter constructed with MOS P–channel andN–channel enhancement mode devices (complementary MOS) in amonolithic structure.This device has been designed for use with the MC14568B phasecomparator/counter in frequency synthesizers, phase–locked loops,and other frequency division applications requiring low powerdissipation and/or high noise immunity.• Speed–up Circuitry for Zero Detection• Each 4–Bit Counter Can Divide Independently in BCD or BinaryMode• Can be Cascaded With MC14526B forFrequency Synthesizer Applications• All Outputs are Buffered• Schmitt Triggered Clock Conditioninghttp://onsemi.comPDIP–16P SUFFIXCASE 648TSSOP–16DT SUFFIXCASE 948FMARKINGDIAGRAMS161MC14569BCPAWLYYWW16114569BALYWMAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 1.)Symbol Parameter Value UnitV DD DC Supply Voltage Range –0.5 to +18.0 VV in , V out Input or Output Voltage Range(DC or Transient)–0.5 to V DD + 0.5 VSOIC–16DW SUFFIXCASE 751G1614569BAWLYYWW1I in , I outP DInput or Output Current(DC or Transient) per PinPower Dissipation,per Package (Note 2.)±10 mA500 mWA = Assembly LocationWL or L = Wafer LotYY or Y = YearWW or W = Work WeekT A Ambient Temperature Range –55 to +125 °CT stg Storage Temperature Range –65 to +150 °CT LLead Temperature(8–Second Soldering)260 °C1. Maximum Ratings are those values beyond which damage to the devicemay occur.2. Temperature Derating:Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 CThis device contains protection circuitry to guard against damage due to highstatic voltages or electric fields. However, precautions must be taken to avoidapplications of any voltage higher than maximum rated voltages to thishigh–impedance circuit. For proper operation, V in and V out should be constrainedto the range V SS (V in or V out ) V DD .Unused inputs must always be tied to an appropriate logic voltage level (e.g.,either V SS or V DD ). Unused outputs must be left open.ORDERING INFORMATIONDevice Package ShippingMC14569BCP PDIP–16 2000/BoxMC14569BDT TSSOP–16 96/RailMC14569BDW SOIC–16 47/RailMC14569BDWR2 SOIC–16 1000/Tape & Reel© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 3399 Publication Order Number:MC14569B/D

MC14569BPIN ASSIGNMENTZERODETECTCTL1121615V DDQP0 3 14 P7P1 4 13 P6P2 5 12 P5P3 6 11 P4CASCADEFEEDBACK7 10 CTL 2V SS 8 9 CLOCKBLOCK DIAGRAMCTL = Low for Binary CountCTL = High for BCD CountP0 P1 P2 P3 CTL 1 CTL 2 P4 P5 P6 P73 4 5 6 2 10 11 12 13 14V DD = PIN 16V SS = PIN 8CLOCK 9 7BINARY/BCDCOUNTER #1CLOCKLOADBINARY/BCDCOUNTER #215QCASCADEFEEDBACKZERO DETECT ENCODER1 ZERODETECThttp://onsemi.com400

MC14569BELECTRICAL CHARACTERISTICS (Voltages Referenced to V SS )– 55 C 25 C 125 CV DDVdc Min Max Min Typ (3.) Max Min Max UnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCharacteristicOutput VoltageV in = V DD or 0“0” LevelSymbolV OL 5.01015V in = 0 or V DD “1” Level V OH 5.01015Input Voltage“0” Level(V O = 4.5 or 0.5 Vdc)(V O = 9.0 or 1.0 Vdc)(V O = 13.5 or 1.5 Vdc)(V O = 0.5 or 4.5 Vdc) “1” Level(V O = 1.0 or 9.0 Vdc)(V O = 1.5 or 13.5 Vdc)Output Drive Current(V OH = 2.5 Vdc) Source(V OH = 4.6 Vdc)(V OH = 9.5 Vdc)(V OH = 13.5 Vdc)(V OL = 0.4 Vdc) Sink(V OL = 0.5 Vdc)(V OL = 1.5 Vdc)V IL5.01015V IH 5.01015I OH5.05.01015I OL 5.01015———4.959.9514.95———3.57.011– 3.0– 0.64– 1.6– 4.20.641.64.20.050.050.05———1.53.04.0——————————4.959.9514.95———3.57.011– 2.4– 0.51– 1.3– 3.40005.010152.254.506.752.755.508.25– 4.2– 0.88– 2.25– 8.80.050.050.05———1.53.04.0——————————4.959.9514.95———3.57.011– 1.7– 0.36– 0.9– 2.4Input Current I in 15 — ±0.1 — ±0.00001 ±0.1 — ±1.0 µAdcInput Capacitance(V in = 0)———0.511.33.40.882.258.80.050.050.05C in — — — — 5.0 7.5 — — pF———0.360.92.4———1.53.04.0——————————VdcVdcVdcVdcmAdcmAdcQuiescent Current(Per Package)Total Supply Current (4.) (5.)(Dynamic plus Quiescent,Per Package)(C L = 50 pF on all outputs, allbuffers switching)I DD 5.01015I T 5.01015———5.01020———0.0050.0100.0155.01020I T = (0.58 µA/kHz) f + I DDI T = (1.20 µA/kHz) f + I DDI T = (1.95 µA/kHz) f + I DD3. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.4. The formulas given are for the typical characteristics only at 25 C.5. To calculate total supply current at loads other than 50 pF:I T (C L ) = I T (50 pF) + (C L – 50) Vfkwhere: I T is in µA (per package), C L in pF, V = (V DD – V SS ) in volts, f in kHz is input frequency, and k = 0.001.———150300600µAdcµAdchttp://onsemi.com401

SWITCHING CHARACTERISTICS* (C L = 50 pF, T A = 25 C)MC14569BV DDAll TypesVdc Min Typ (6.) Max UnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCharacteristicSymbolOutput Rise Time t TLH 5.01015Output Fall Time t THL 5.01015Turn–On Delay TimeZero Detect Outputt PLH5.01015Q Output 5.01015Turn–Off Delay TimeZero Detect Outputt PHL5.01015Q Output 5.01015Clock Pulse Width t WH 5.01015Clock Pulse Frequency f cl 5.01015Clock Pulse Rise and Fall Time t TLH , t THL 5.01015——————————————————300150115———1005040100504042017512567528520038015010053022515510045303.59.513.0200100802001008070030025012005004006003002001000400300———2.15.17.8nsnsnsnsnsnsnsMHzNO LIMIT µs6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.http://onsemi.com402

MC14569BSWITCHING WAVEFORMS20 nsCLOCKQCLOCK20 nsZERO DETECT10%10%10%90%50%20 nst WHt PLH50%90%t TLHFigure 1.90%50%t WHt PLHt TLH10%20 ns90%Figure 2.t PHLt PHLt THLt THLf in = f maxhttp://onsemi.com403

MC14569BPIN DESCRIPTIONSINPUTSP0, P1, P2, P3 (Pins 3, 4, 5, 6) — Preset Inputs.Programmable inputs for the least significant counter. Maybe binary or BCD depending on the control input.P4, P5, P6, P7 (Pins 11, 12, 13, 14) — Preset Inputs.Programmable inputs for the most significant counter. Maybe binary or BCD depending on the control input.Clock (Pin 9) — Preset data is decremented by one oneach positive transition of this signal.OUTPUTSZero Detect (Pin 1) — This output is normally low andgoes high for one clock cycle when the counter hasdecremented to zero.Q (Pin 15) — Output of the last stage of the mostsignificant counter. This output will be inactive unless thepreset input P7 has been set high.CONTROLSCascade Feedback (Pin 7) — This pin is normally sethigh. When low, loading of the preset inputs (P0 through P7)is inhibited, i.e., P0 through P7 are “don’t cares.” Refer toTable 1 for output characteristics.CTL 1 (Pin 2) — This pin controls the counting mode ofthe least significant counter. When set high, counting modeis BCD. When set low, counting mode is binary.CTL 2 (Pin 10) — This pin controls the counting mode ofthe most significant counter. When set high, counting modeis BCD. When set low, counting mode is binary.SUPPLY PINSV SS (Pin 18) — Negative Supply Voltage. This pin isusually connected to ground.V DD (Pin 16) — Positive Supply Voltage. This pin isconnected to a positive supply voltage ranging from 3.0volts to 18.0 volts.OPERATING CHARACTERISTICSThe MC14569B is a programmable divide–by–N dual4–bit down counter. This counter may be programmed (i.e.,preset) in BCD or binary code through inputs P0 to P7. Foreach counter, the counting sequence may be chosenindependently by applying a high (for BCD count) or a low(for binary count) to the control inputs CTL 1 and CTL 2 .The divide ratio N (N being the value programmed on thepreset inputs P0 to P7) is automatically loaded into thecounter as soon as the count 1 is detected. Therefore, adivision ratio of one is not possible. After N clock cycles,one pulse appears on the Zero Detect output. (See TimingDiagram.) The Q output is the output of the last stage of themost significant counter (See Tables 1 through 5, ModeControls.)When cascading the MC14569B to the MC14526B, theCascade Feedback input, Q, and Zero Detect outputs mustbe respectively connected to “0”, Clock, and Load of thefollowing counter. If the MC14569B is used alone, CascadeFeedback must be connected to V DD .181614C L = 50 pFf, FREQUENCY (MHz), TYPICAL12108.06.04.02.00–40V DD = 15 V10 V5.0 V–200 +20 +40 +60T A , AMBIENT TEMPERATURE (°C)+80 + 100http://onsemi.com404

MC14569BTable 1. Mode Controls (Cascade Feedback = Low)Counter Control ValuesDivide RatioCTL 1 CTL 2 Zero Detect Q0 0 256 2560 1 160 1601 0 160 1601 1 100 100NOTE: Data Preset Inputs (P0–P7) are “Don’t Cares” while Cascade Feedback isLow.Table 2. Mode Controls (CTL 1 = Low, CTL 2 = Low, Cascade Feedback = High)Preset InputsDivide RatioP7 P6 P5 P4 P3 P2 P1 P0ZeroDetect Q Comments0 0 0 0 0 0 0 0 256 256 Max Count0 0 0 0 0 0 0 1 X X Illegal State0 0 0 0 0 0 1 0 2 X Min Count0 0 0 0 0 0 1 1 3 X X X X0 0 0 0 1 1 1 1 15 X0 0 0 1 0 0 0 0 16 X X X X0 0 1 0 0 0 0 0 32 X X X X0 1 0 0 0 0 0 0 64 X X X X0 1 1 1 1 1 1 1 127 X1 0 0 0 0 0 0 0 128 128 Q Output Active 1 0 0 0 1 0 0 0 136 136 1 1 1 1 1 1 1 1 255 2552 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0128 64 32 16 8 4 2 1 Bit ValueCounter #2BinaryX = No Output (Always Low)Counter #1BinaryCountingSequencehttp://onsemi.com405

MC14569BTable 3. Mode Controls (CTL 1 = High, CTL 2 = Low, Cascade Feedback = High)Preset InputsDivide RatioP7 P6 P5 P4 P3 P2 P1 P0ZeroDetect Q Comments0 0 0 0 0 0 0 0 160 160 Max Count0 0 0 0 0 0 0 1 X X Illegal State0 0 0 0 0 0 1 0 2 X Min Count0 0 0 0 0 0 1 1 3 X X X X0 0 0 0 1 0 0 1 9 X0 0 0 1 0 0 0 0 10 X X X X0 0 0 1 1 0 0 1 19 X0 0 1 0 0 0 0 0 20 X X X X0 0 1 1 0 0 0 0 30 X X X X0 1 0 0 0 0 0 0 40 X X X X0 1 0 1 0 0 0 0 50 X X X X0 1 1 0 0 0 0 0 60 X X X X0 1 1 1 0 0 0 0 70 X X X X1 0 0 0 0 0 0 0 80 80 Q Output Active 1 0 0 1 0 0 0 0 90 90 1 1 1 1 0 0 0 0 150 150 1 1 1 1 1 0 0 1 159 15980 40 20 10 8 4 2 1 Bit ValueCounter #2BinaryX = No Output (Always Low)Counter #1BCDCountingSequencehttp://onsemi.com406

MC14569BTable 4. Mode Controls (CTL 1 = Low, CTL 2 = High, Cascade Feedback = High)Preset ValuesDivide RatioP7 P6 P5 P4 P3 P2 P1 P0ZeroDetect Q Comments0 0 0 0 0 0 0 0 160 160 Max Count0 0 0 0 0 0 0 1 X X Illegal State0 0 0 0 0 0 1 0 2 X Min Count0 0 0 0 0 0 1 1 3 X X X X0 0 0 0 1 1 1 1 15 X0 0 0 1 0 0 0 0 16 X X X X0 0 0 1 1 1 1 1 31 X0 0 1 0 0 0 0 0 32 X X X X0 0 1 1 0 0 0 0 48 X 0 1 0 0 0 0 0 0 64 X 0 1 0 1 0 0 0 0 80 X 0 1 1 1 0 0 0 0 112 X 1 0 0 0 0 0 0 0 128 128 Q Output Active 1 0 0 1 0 0 0 0 144 144 1 0 0 1 1 1 1 1 159 1592 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0128 64 32 16 8 4 2 1 Bit ValueCounter #2BCDX = No Output (Always Low)Counter #1BinaryCountingSequencehttp://onsemi.com407

MC14569BTable 5. Mode Controls (CTL 1 = High, CTL 2 = High, Cascade Feedback = High)Preset ValuesDivide RatioP7 P6 P5 P4 P3 P2 P1 P0ZeroDetect Q Comments0 0 0 0 0 0 0 0 100 100 Max Count0 0 0 0 0 0 0 1 X X illegal state0 0 0 0 0 0 1 0 2 X Min Count0 0 0 0 0 0 1 1 3 X X X X0 0 0 0 1 0 0 1 9 X0 0 0 1 0 0 0 0 10 X X X X0 0 1 1 0 0 0 0 30 X X X X0 1 0 0 0 0 0 0 40 X X X X0 1 0 1 0 0 0 0 50 X X X X0 1 1 1 0 0 0 0 70 X X X X1 0 0 0 0 0 0 0 80 80 Q Output Active 1 0 0 1 0 0 0 0 90 90 1 0 0 1 1 0 0 1 99 9980 40 20 10 8 4 2 1 Bit ValueCounter #2BCDX = No Output (Always Low)Counter #1BCDCountingSequenceTIMING DIAGRAM MC14569BCLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16DIVIDEBY 2ZERODETECTOUTPUTDIVIDEBY 3DIVIDEBY 4DIVIDEBY 12http://onsemi.com408

MC14569BCTL 12LOGIC DIAGRAMD PQDPECP03D PQDPECP14D PQDPECD PQPEP25DCP36D PQDPECD PQDPECD PQDPECD PQDIUPECV DDCASCADE 7FEEDBACKV DD1CLOCK9P411D PDQCPEZERODETECTP512D PDQCPEP613D PDQCPE14P710CTL 2D PDQCPE15http://onsemi.com409

MC14569BTYPICAL APPLICATIONSf inCCFQMC14569BZERO DETECTCCFMC14522BQ4ORPE MC14526B “0”CCFMC14522BQ4ORPE MC14526B “0”Q1/C2MC14568BPE “0”DP0 – – – – – – DP3 DP0 – – – – – – DP3 DP0 – – – – – – DP3LSD MSD f outFigure 3. Cascading MC14568B and MC14522B or MC14526B with MC14569B(40 kHz)V SSPC inC1CT1“0”PC outGFQ1/C2V SSV SSVCOf out(144 – 146 MHz)PEDP0 – – – – DP3MC14011V DDQCFMC14569BZERO DETECTC2 kMIXERFrequencies shown in parenthesis are given as an example2 MCRYSTALOSCILLATOR(143.5 MHz)Figure 4. Frequency Synthesizer with MC14568B and MC14569B Using a Mixer(Channel Spacing 10 kHz)http://onsemi.com410

The MC14572UB hex functional gate is constructed with MOSP–channel and N–channel enhancement mode devices in a singlemonolithic structure. These complementary MOS logic gates findprimary use where low power dissipation and/or high noise immunityis desired. The chip contains four inverters, one NOR gate and oneNAND gate.• Diode Protection on All Inputs• Single Supply Operation• Supply Voltage Range = 3.0 Vdc to 18 Vdc• NOR Input Pin Adjacent to V SS Pin to Simplify Use As An Inverter• NAND Input Pin Adjacent to V DD Pin to Simplify Use As AnInverter• NOR Output Pin Adjacent to Inverter Input Pin For OR Application• NAND Output Pin Adjacent to Inverter Input Pin For ANDApplication• Capable of Driving Two Low–power TTL Loads or One Low–PowerSchottky TTL Load over the Rated Temperature RangeMAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 2.)Symbol Parameter Value UnitV DD DC Supply Voltage Range –0.5 to +18.0 VV in , V out Input or Output Voltage Range(DC or Transient)–0.5 to V DD + 0.5 VI in , I outP DInput or Output Current(DC or Transient) per PinPower Dissipation,per Package (Note 3.)±10 mA500 mWT A Ambient Temperature Range –55 to +125 °CT stg Storage Temperature Range –65 to +150 °CT LLead Temperature(8–Second Soldering)260 °C2. Maximum Ratings are those values beyond which damage to the devicemay occur.3. Temperature Derating:Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 CThis device contains protection circuitry to guard against damage due to highstatic voltages or electric fields. However, precautions must be taken to avoidapplications of any voltage higher than maximum rated voltages to thishigh–impedance circuit. For proper operation, V in and V out should be constrainedto the range V SS (V in or V out ) V DD .Unused inputs must always be tied to an appropriate logic voltage level (e.g.,either V SS or V DD ). Unused outputs must be left open.http://onsemi.comPDIP–16P SUFFIXCASE 648SOIC–16D SUFFIXCASE 751BSOEIAJ–16F SUFFIXCASE 966A = Assembly LocationWL or L = Wafer LotYY or Y = YearWW or W = Work WeekORDERING INFORMATIONMARKINGDIAGRAMSDevice Package ShippingMC14572UBCP PDIP–16 2000/BoxMC14572UBD SOIC–16 48/RailMC14572UBDR2 SOIC–16 2500/Tape & Reel1. For ordering information on the EIAJ version ofthe SOIC packages, please contact your localON Semiconductor representative.16MC14572UBCPAWLYYWW116116114572UAWLYWWMC14572UBAWLYWWMC14572UBF SOEIAJ–16 See Note 1.MC14572UBFEL SOEIAJ–16 See Note 1.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 3411 Publication Order Number:MC14572UB/D

MC14572UBPIN ASSIGNMENTOUT A116V DDIN A215IN 2 FOUT B314IN 1 FIN B413OUT F512IN EOUT CLOGIC DIAGRAMIN 1 C611OUT EIN 2 C710IN DV SS89OUT D21436751091211141513V DD = PIN 16V SS = PIN 8CIRCUIT SCHEMATICV DDV DDV DD21713V SS6514V SS15V SShttp://onsemi.com412

MC14572UBELECTRICAL CHARACTERISTICS (Voltages Referenced to V SS )V DD– 55 C 25 C 125 CÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput VoltageV in = V DD or 0Characteristic Symbol Vdc Min Max Min Typ (4.) Max Min Max Unit“0” LevelV OL 5.01015V in = 0 or V DD “1” Level V OH 5.01015Input Voltage“0” Level(V O = 4.5 or 0.5 Vdc)(V O = 9.0 or 1.0 Vdc)(V O = 13.5 or 1.5 Vdc)(V O = 0.5 or 4.5 Vdc)(V O = 1.0 or 9.0 Vdc)(V O = 1.5 or 13.5 Vdc)“1” LevelOutput Drive Current(V OH = 2.5 Vdc) Source(V OH = 4.6 Vdc)(V OH = 9.5 Vdc)(V OH = 13.5 Vdc)(V OL = 0.4 Vdc) Sink(V OL = 0.5 Vdc)(V OL = 1.5 Vdc)V IL5.01015V IH5.01015I OH5.05.01015I OL 5.01015———4.959.9514.95———4.08.012.5– 1.2– 0.25– 0.62– 1.80.641.64.20.050.050.05———1.02.02.5——————————4.959.9514.95———4.08.012.5– 1.0– 0.2– 0.5– 1.50005.010152.254.506.752.755.508.25– 1.7– 0.36– 0.9– 3.50.050.050.05———1.02.02.5——————————4.959.9514.95———4.08.012.5– 0.7– 0.14– 0.35– 1.1Input Current I in 15 — ±0.1 — ±0.00001 ±0.1 — ±1.0 µAdcInput Capacitance(V in = 0)———0.511.33.40.882.258.80.050.050.05C in — — — — 5.0 7.5 — — pF———0.360.92.4———1.02.02.5——————————VdcVdcVdcVdcmAdcmAdcQuiescent Current(Per Package)Total Supply Current (5.) (6.)(Dynamic plus Quiescent,Per Package)(C L = 50 pF on all outputs, allbuffers switching)I DD 5.01015I T 5.01015———0.250.51.0———0.00050.00100.00150.250.51.0I T = (1.89 µA/kHz) f + I DDI T = (3.80 µA/kHz) f + I DDI T = (5.68 µA/kHz) f + I DD4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.5. The formulas given are for the typical characteristics only at 25 C.6. To calculate total supply current at loads other than 50 pF:I T (C L ) = I T (50 pF) + (C L – 50) Vfkwhere: I T is in µA (per package), C L in pF, V = (V DD – V SS ) in volts, f in kHz is input frequency, and k = 0.006.———7.51530µAdcµAdchttp://onsemi.com413

MC14572UBSWITCHING CHARACTERISTICS (7.) (C L = 50 pF, T A = 25 C)Characteristic Symbol V DD Min Typ (8.) Max UnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Rise Timet TLH = (3.0 ns/pF) C L + 30 nst TLH = (1.5 ns/pF) C L + 15 nst TLH = (1.1 ns/pF) C L + 10 nsOutput Fall Timet THL = (1.5 ns/pF) C L + 25 nst THL = (0.75 ns/pF) C L + 12.5 nst THL = (0.55 ns/pF) C L + 9.5 nsPropagation Delay Timet PLH , t PHL = (1.7 ns/pF) C L + 5 nst PLH , t PHL = (0.66 ns/pF) C L + 17 nst PLH , t PHL = (0.5 ns/pF) C L + 15 nst TLH5.01015t THL5.01015t PLH ,t PHL 5.010157. The formulas given are for the typical characteristics only at 25 C.8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.—————————180906510050409050403601801302001008018010080nsnsnsV DDPULSEGENERATORPULSEGENERATORINPUT15INPUT2148 V SS8V DD1616V SSOUTPUT1C LOUTPUT13C LINPUTOUTPUTPULSEGENERATOR90%50%10%INPUT76V DD1658 V SS C L20 ns 20 nsV90% DD50%10%t PHLt PLH90%90%50%10% 10%50%t f t rV SSV OHV OLOUTPUTFigure 1. Switching Time Test Circuits and Waveformshttp://onsemi.com414

The MC14584B Hex Schmitt Trigger is constructed with MOSP–channel and N–channel enhancement mode devices in a singlemonolithic structure. These devices find primary use where low powerdissipation and/or high noise immunity is desired. The MC14584Bmay be used in place of the MC14069UB hex inverter for enhancednoise immunity to “square up” slowly changing waveforms.• Supply Voltage Range = 3.0 Vdc to 18 Vdc• Capable of Driving Two Low–power TTL Loads or One Low–powerSchottky TTL Load over the Rated Temperature Range• Double Diode Protection on All Inputs• Can Be Used to Replace MC14069UB• For Greater Hysteresis, Use MC14106B which is Pin–for–PinReplacement for CD40106B and MM74Cl4MAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 2.)Symbol Parameter Value UnitV DD DC Supply Voltage Range –0.5 to +18.0 VV in , V out Input or Output Voltage Range(DC or Transient)–0.5 to V DD + 0.5 VI in , I outP DInput or Output Current(DC or Transient) per PinPower Dissipation,per Package (Note 3.)±10 mA500 mWT A Ambient Temperature Range –55 to +125 °CT stg Storage Temperature Range –65 to +150 °CT LLead Temperature(8–Second Soldering)260 °C2. Maximum Ratings are those values beyond which damage to the devicemay occur.3. Temperature Derating:Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 CThis device contains protection circuitry to guard against damage due to highstatic voltages or electric fields. However, precautions must be taken to avoidapplications of any voltage higher than maximum rated voltages to thishigh–impedance circuit. For proper operation, V in and V out should be constrainedto the range V SS (V in or V out ) V DD .Unused inputs must always be tied to an appropriate logic voltage level (e.g.,either V SS or V DD ). Unused outputs must be left open.http://onsemi.comPDIP–14P SUFFIXCASE 646SOIC–14D SUFFIXCASE 751ATSSOP–14DT SUFFIXCASE 948GSOEIAJ–14F SUFFIXCASE 965MARKINGDIAGRAMS14A = Assembly LocationWL or L = Wafer LotYY or Y = YearWW or W = Work Week114114MC14584BCPAWLYYWW14584BAWLYWW14ORDERING INFORMATION1114584BALYWMC14584BAWLYWWDevice Package ShippingMC14584BCP PDIP–14 2000/BoxMC14584BD SOIC–14 55/RailMC14584BDR2 SOIC–14 2500/Tape & ReelMC14584BDT TSSOP–14 96/RailMC14584BDTEL TSSOP–14 2000/Tape & ReelMC14584BF SOEIAJ–14 See Note 1.MC14584BFEL SOEIAJ–14 See Note 1.1. For ordering information on the EIAJ version ofthe SOIC packages, please contact your localON Semiconductor representative.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 3415 Publication Order Number:MC14584B/D

MC14584BPIN ASSIGNMENTIN 1114V DDOUT 1213IN 6IN 2312OUT 6OUT 2411IN 5IN 3510OUT 5OUT 369IN 4V SS78OUT 4LOGIC DIAGRAM1234569811101312V DD = PIN 14V SS = PIN 7EQIVALENT CIRCUIT SCHEMATIC(1/6 OF CIRCUIT SHOWN)http://onsemi.com416

MC14584BELECTRICAL CHARACTERISTICS (Voltages Referenced to V SS )– 55 C 25 C 125 CV DDVdc Min Max Min Typ (4.) Max Min Max UnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCharacteristicSymbolV 5.0Output Voltage“0” LevelV in = V DDOL1015V in = 0 “1” Level V OH 5.01015Output Drive Current(V OH = 2.5 Vdc) Source(V OH = 4.6 Vdc)(V OH = 9.5 Vdc)(V OH = 13.5 Vdc)(V OL = 0.4 Vdc) Sink(V OL = 0.5 Vdc)(V OL = 1.5 Vdc)I OH5.05.01015I OL 5.01015———4.959.9514.95– 3.0– 0.64– 1.6– 4.20.641.64.20.050.050.05——————————4.959.9514.95– 2.4– 0.51– 1.3– 3.40005.01015– 4.2– 0.88– 2.25– 8.80.050.050.05——————————4.959.9514.95– 1.7– 0.36– 0.9– 2.4Input Current I in 15 — ±0.1 — ±0.00001 ±0.1 — ±1.0 µAdcInput Capacitance(V in = 0)———0.511.33.40.882.258.80.050.050.05C in — — — — 5.0 7.5 — — pF———0.360.92.4——————————VdcVdcmAdcmAdcQuiescent Current(Per Package)I DD 5.01015———0.250.51.0———0.00050.00100.00150.250.51.0———7.51530µAdcTotal Supply Current (5.) (6.)(Dynamic plus Quiescent,Per Package)(C L = 50 pF on all outputs, allbuffers switching)I T 5.01015I T = (1.8 µA/kHz) f + I DDI T = (3.6 µA/kHz) f + I DDI T = (5.4 µA/kHz) f + I DDµAdcHysteresis Voltage V (7.) H 5.01015Threshold VoltagePositive–GoingV T+5.01015Negative–Going V T– 5.010150.270.360.771.93.45.21.63.04.54. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.5. The formulas given are for the typical characteristics only at 25 C.6. To calculate total supply current at loads other than 50 pF:I T (C L ) = I T (50 pF) + (C L – 50) Vfkwhere: I T is in µA (per package), C L in pF, V = (V DD – V SS ) in volts, f in kHz is input frequency, and k = 0.001.7. V H = V T+ – V T– (But maximum variation of V H is specified as less than V T + max – V T – min ).1.01.31.73.57.010.63.36.79.70.250.30.61.83.35.21.63.04.60.60.71.12.75.38.02.14.66.91.01.21.53.46.910.53.26.79.80.210.250.501.73.25.21.53.04.71.01.21.43.46.910.53.26.79.9VdcVdcVdchttp://onsemi.com417

MC14584BSWITCHING CHARACTERISTICS (C L = 50 pF, T A = 25 C)CharacteristicSymbolV DDVdc Min Typ (8.) Max UnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Rise Time t TLH 5.01015Output Fall Time t THL 5.01015Propagation Delay Time t PLH , t PHL 5.010158. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.—————————100504010050401255040200100802001008025010080nsnsnshttp://onsemi.com418

MC14584BPULSEGENERATORINPUT7V DD14OUTPUTV SSC L20 ns 20 nsINPUTt PHLOUTPUT90%50%10%90%50%10%t PLHV DDV SSV OHV OLt ft rFigure 1. Switching Time Test Circuit and WaveformsV inV outV H V DDV H V DDV in V T–V inV T–V T+V T+V SSV SSV DDV DDV outV outV SS(a) Schmitt Triggers will square up inputs with slowrise and fall times.Figure 2. Typical Schmitt Trigger ApplicationsV SS(b) A Schmitt trigger offers maximum noise immunityin gate applications.V DD0Vout , OUTPUT VOLTAGE (Vdc)0V T–V T+V DDV HV in , INPUT VOLTAGE (Vdc)Figure 3. Typical Transfer Characteristicshttp://onsemi.com419

The MC14585B 4–Bit Magnitude Comparator is constructed withcomplementary MOS (CMOS) enhancement mode devices. Thecircuit has eight comparing inputs (A3, B3, A2, B2, A1, B1, A0, B0),three cascading inputs (A < B, A = B, and A > B), and three outputs (A< B, A = B, and A > B). This device compares two 4–bit words (A andB) and determines whether they are “less than”, “equal to”, or “greaterthan” by a high level on the appropriate output. For words greater than4–bits, units can be cascaded by connecting outputs (A > B), (A < B),and (A = B) to the corresponding inputs of the next significantcomparator. Inputs (A < B), (A = B), and (A > B) on the leastsignificant (first) comparator are connected to a low, a high, and a low,respectively.Applications include logic in CPU’s, correction and/or detection ofinstrumentation conditions, comparator in testers, converters, andcontrols.• Diode Protection on All Inputs• Expandable• Applicable to Binary or 8421–BCD Code• Supply Voltage Range = 3.0 Vdc to 18 Vdc• Capable of Driving Two Low–power TTL Loads or One Low–powerSchottky TTL Load over the Rated Temperature Range• Can be Cascaded – See Fig. 3MAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 2.)Symbol Parameter Value UnitV DD DC Supply Voltage Range –0.5 to +18.0 VV in , V out Input or Output Voltage Range(DC or Transient)–0.5 to V DD + 0.5 VI in , I outP DInput or Output Current(DC or Transient) per PinPower Dissipation,per Package (Note 3.)±10 mA500 mWT A Ambient Temperature Range –55 to +125 °CT stg Storage Temperature Range –65 to +150 °CT LLead Temperature(8–Second Soldering)260 °C2. Maximum Ratings are those values beyond which damage to the devicemay occur.3. Temperature Derating:Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 Chttp://onsemi.comPDIP–16P SUFFIXCASE 648SOIC–16D SUFFIXCASE 751BSOEIAJ–16F SUFFIXCASE 966A = Assembly LocationWL or L = Wafer LotYY or Y = YearWW or W = Work WeekORDERING INFORMATIONMARKINGDIAGRAMSDevice Package ShippingMC14585BCP PDIP–16 2000/BoxMC14585BD SOIC–16 48/RailMC14585BDR2 SOIC–16 2500/Tape & Reel1. For ordering information on the EIAJ version ofthe SOIC packages, please contact your localON Semiconductor representative.161161161MC14585BCPAWLYYWW14585BAWLYWWMC14585BAWLYWWMC14585BF SOEIAJ–16 See Note 1.This device contains protection circuitry to guard against damage due to highstatic voltages or electric fields. However, precautions must be taken to avoidapplications of any voltage higher than maximum rated voltages to thishigh–impedance circuit. For proper operation, V in and V out should be constrainedto the range V SS (V in or V out ) V DD .Unused inputs must always be tied to an appropriate logic voltage level (e.g.,either V SS or V DD ). Unused outputs must be left open.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 3420 Publication Order Number:MC14585B/D

MC14585BPIN ASSIGNMENTB2116V DDA2215A3(A = B) out314B3(A B) in413(A B) out512(A B) out(A B) inBLOCK DIAGRAM(A = B) in611B0A1710A0V SS89B1465101179211514(A > B) in(A = B) in(A < B) inA0B0A1B1A2B2A3B3(A > B) out(A = B) out(A < B) out13312V DD = PIN 16V SS = PIN 8TRUTH TABLE (x = Don’t Care)InputsComparing Cascading OutputsA3, B3 A2, B2 A1, B1 A0, B0 A < B A = B A > B A < B A = B A > BA3 > B3 x x x x x x 0 0 1A3 = B3 A2 > B2 x x x x x 0 0 1A3 = B3 A2 = B2 A1 > B1 x x x x 0 0 1A3 = B3 A2 = B2 A1 = B1 A0 > B0 x x x 0 0 1A3 = B3 A2 = B2 A1 = B1 A0 = B0 0 0 x 0 0 1A3 = B3 A2 = B2 A1 = B1 A0 = B0 0 1 x 0 1 0A3 = B3 A2 = B2 A1 = B1 A0 = B0 1 0 x 1 0 0A3 = B3 A2 = B2 A1 = B1 A0 = B0 1 1 x 1 1 0A3 = B3 A2 = B2 A1 = B1 A0 < B0 x x x 1 0 0A3 = B3 A2 = B2 A1 < B1 x x x x 1 0 0A3 = B3 A2 < B2 x x x x x 1 0 0A3 < B3 x x x x x x 1 0 0http://onsemi.com421

MC14585BELECTRICAL CHARACTERISTICS (Voltages Referenced to V SS )– 55 C 25 C 125 CV DDVdc Min Max Min Typ (4.) Max Min Max UnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCharacteristicOutput VoltageV in = V DD or 0“0” LevelSymbolV OL 5.01015V 5.0“1” LevelV in = 0 or V DDOH1015Input Voltage“0” Level(V O = 4.5 or 0.5 Vdc)(V O = 9.0 or 1.0 Vdc)(V O = 13.5 or 1.5 Vdc)(V O = 0.5 or 4.5 Vdc)(V O = 1.0 or 9.0 Vdc)(V O = 1.5 or 13.5 Vdc)“1” LevelOutput Drive Current(V OH = 2.5 Vdc) Source(V OH = 4.6 Vdc)(V OH = 9.5 Vdc)(V OH = 13.5 Vdc)(V OL = 0.4 Vdc) Sink(V OL = 0.5 Vdc)(V OL = 1.5 Vdc)V IL5.01015V IH5.01015I OH5.05.01015I OL 5.01015———4.959.9514.95———3.57.011– 3.0– 0.64– 1.6– 4.20.641.64.20.050.050.05———1.53.04.0——————————4.959.9514.95———3.57.011– 2.4– 0.51– 1.3– 3.40005.010152.254.506.752.755.508.25– 4.2– 0.88– 2.25– 8.80.050.050.05———1.53.04.0——————————4.959.9514.95———3.57.011– 1.7– 0.36– 0.9– 2.4Input Current I in 15 — ±0.1 — ±0.00001 ±0.1 — ±1.0 µAdcInput Capacitance(V in = 0)———0.511.33.40.882.258.80.050.050.05C in — — — — 5.0 7.5 — — pF———0.360.92.4———1.53.04.0——————————VdcVdcVdcVdcmAdcmAdcQuiescent Current(Per Package)Total Supply Current (5.) (6.)(Dynamic plus Quiescent,Per Package)(C L = 50 pF on all outputs, allbuffers switching)I DD 5.01015I T 5.01015———5.01020———0.0050.0100.0155.01020I T = (0.6 µA/kHz) f + I DDI T = (1.2 µA/kHz) f + I DDI T = (1.8 µA/kHz) f + I DD4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.5. The formulas given are for the typical characteristics only at 25 C.6. To calculate total supply current at loads other than 50 pF:I T (C L ) = I T (50 pF) + (C L – 50) Vfkwhere: I T is in µA (per package), C L in pF, V = (V DD – V SS ) in volts, f in kHz is input frequency, and k = 0.001.———150300600µAdcµAdchttp://onsemi.com422

MC14585BSWITCHING CHARACTERISTICS (7.) (C L = 50 pF, T A = 25 C)Characteristic Symbol V DD Min Typ (8.) Max UnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Rise and Fall Timet TLH , t THL = (1.5 ns/pF) C L + 25 nst TLH , t THL = (0.75 ns/pF) C L + 12.5 nst TLH , t THL = (0.55 ns/pF) C L + 9.5 nsTurn–On, Turn–Off Delay Timet PLH , t PHL = (1.7 ns/pF) C L + 345 nst PLH , t PHL = (0.66 ns/pF) C L + 147 nst PLH , t PHL = (0.5 ns/pF) C L + 105 nst TLH ,t THL 5.01015t PLH ,t PHL 5.010157. The formulas given are for the typical characteristics only at 25 C.8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.——————100504043018013020010080860360260nsns20 ns20 nsV DDA312fV SSV DDB3V SSV OH20 ns 20 ns(A > B) out90%V OLV OHB050%10%(A = B) out t PLHt PHLV OL90%V OH50%(A < B) out(A < B) out10%V OLt TLHt THLInputs (A>B) and (A=B) high, and inputs B2, A2, B1,A1, B0, A0 and (AB) and (A=B) high, and inputs B3, A3, B2,A2, B1, A1, A0, and (A

MC14585BWORDB = B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0WORDA = A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0VSS V DD V SSB3 A3 B2 A2 B1 A1 B0 A0OUTPUTMC14585B(AB)(AB)INPUTSMC14585BMC14585B(AB)OUTPUTSFigure 3. Cascading ComparatorsWORD B = B11, B10, ... , B0.WORD A = A11, A10, ... , A0.15A3LOGIC DIAGRAM14B32A21B27A112(A < B) out9B110A011B05(A < B) in6(A = B) in4(A > B) in3(A = B) out13(A > B) outhttp://onsemi.com424

The MC14598B is an 8–bit latch addressed with an external binaryaddress. The 8 latch–outputs are high drive, three–state and bus linecompatible. The drive capability allows direct applications with MPUsystems such as the Motorola 6800 family.The latches of the MC14598B are accessed via the Address pins,A0, A1, and A2.All 8 outputs from the latches are available in parallel when Enableis in the low state. Data is entered into a selected latch from the Datapin when the Strobe is high. Master reset is available on both parts.• Serial Data Input• Three–State Bus Compatible Parallel Outputs• Three–State Control Pin (Enable) TTL Compatible Input• Open Drain Full Flag (Multiple Latch Wire–O Ring)• Master Reset• Level Shifting Inputs on All Except Enable• Diode Protection — All Inputs• Supply Voltage Range — 3.0 Vdc to 18 Vdc• Capable of Driving TTL Over Rated Temperature RangeWith Fanout as Follows:1 TTL Load4 LSTTL LoadsPDIP–18P SUFFIXCASE 707http://onsemi.com181MARKINGDIAGRAMSMC14598BCPAWLYYWWA = Assembly LocationWL or L = Wafer LotYY or Y = YearWW or W = Work WeekMAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 1.)Symbol Parameter Value UnitV DD DC Supply Voltage Range –0.5 to +18.0 VV in Input Voltage Range,Enable (DC or Transient)–0.5 to V DD + 0.5 VORDERING INFORMATIONDevice Package ShippingMC14598BCP PDIP–18 20/RailV inV outI in , I outInput Voltage Range, All OtherInputs (DC or Transient)Output Voltage Range,(DC or Transient)Input or Output Current(DC or Transient) per Pin–0.5 to V DD + 12 V–0.5 to V DD + 0.5 V±10 mAP DPower Dissipation,per Package (Note 2.)500 mWT A Ambient Temperature Range –55 to +125 °CT stg Storage Temperature Range –65 to +150 °CT LLead Temperature(8–Second Soldering)260 °C1. Maximum Ratings are those values beyond which damage to the devicemay occur.2. Temperature Derating:Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 CThis device contains protection circuitry to guardagainst damage due to high static voltages or electricfields. However, precautions must be taken to avoid applicationsof any voltage higher than maximum ratedvoltages to this high–impedance circuit. For properoperation, V in and V out should be constrained to therange V SS (V in or V out ) V DD .Unused inputs must always be tied to an appropriatelogic voltage level (e.g., either V SS or V DD ). Unused outputsmust be left open.© Semiconductor Components Industries, LLC, 2000March, 2000 – Rev. 3425 Publication Order Number:MC14598B/D

MC14598BPIN ASSIGNMENTD0118V DDRESET217D1DATA316D2ENABLE415D3NC514D4STROBE613D5A0712D6A1811D7V SS910A2BLOCK DIAGRAMSRESETDATASTROBEA0A1A27810MC14598BADDRESSDECODERV DD = 18V SS = 92368LATCHESENABLE4THREESTATEOUTPUTBUFFERS117161514131211D0D1D2D3D4D5D6D7OUTPUTTRUTH TABLEEnable Outputs1 High Impedance0 D nD n = State of nth latchNC = NO CONNECTIONhttp://onsemi.com426

MC14598BELECTRICAL CHARACTERISTICS (Voltages Referenced to V SS )CharacteristicSymbolÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput VoltageV in = V DD or 0“0” LevelV OL 5.01015V 5.0“1” LevelV in = 0 or V DDOH1015Input Voltage (4.) — Enable “0” Level(V O = 4.5 or 0.5 Vdc)(V O = 9.0 or 1.0 Vdc)(V O = 13.5 or 1.5 Vdc)“1” Level(V O = 0.5 or 4.5 Vdc)(V O = 1.0 or 9.0 Vdc)(V O = 1.5 or 13.5 Vdc)Input Voltage“0” LevelOther Inputs(V O = 4.5 or 0.5 Vdc)(V O = 9.0 or 1.0 Vdc)(V O = 13.5 or 1.5 Vdc)(V O = 0.5 or 4.5 Vdc) “1” Level(V O = 1.0 or 9.0 Vdc)(V O = 1.5 or 13.5 Vdc)Output Drive Current Source(Full — Sink Only)(V OH = 4.6 Vdc)(V OH = 9.5 Vdc)(V OH = 13.5 Vdc)(V OL = 0.4 Vdc) Sink(V OL = 0.5 Vdc)(V OL = 1.5 Vdc)V IL5.01015V IH5.01015V IL5.01015V IH 5.01015I OH5.0101 5I OL 5.01015V DD– 55 C 25 C 125 CVdc Min Max Min Typ (3.) Max Min Max Unit— 0.05 — 0 0.05 — 0.05 Vdc— 0.05 — 0 0.05 — 0.05— 0.05 — 0 0.05 — 0.054.959.9514.95———2.06.010———3.57.011– 1.0——1.6—————0.81.62.4———1.53.04.04.959.9514.95———2.06.010———5.010151.12.23.41.93.14.32.254.506.75———0.81.62.4———1.53.04.04.959.9514.95Input Current I in 15 — ±0.1 — ±0.00001 ±0.1 — ±1.0 µAdcThree–State Leakage Current I TL 15 — ±0.1 — ±0.00001 ±0.1 — ±3.0 µAdcInput Capacitance (V in = 0) C in — — — — 5.0 7.5 — — pFQuiescent CurrentµAdc(Per Package)I DD 5.01015Total Supply Current at anI T 5.0**130 pF (4.)**External Load Capacitance of10——————–—————5.010203.57.011– 1.0——1.6—————2.755.508.25– 2.0– 6.0– 123.26.0120.0050.0100.015—————————5.01020I T = (2.0 µA/kHz) f + I DDI T = (4.0 µA/kHz) f + I DDI T = (6.0 µA/kHz) f + I DD3. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.4. The formulas given are for the typical characteristics only at 25 C.———2.06.010———3.57.011– 1.0——1.6————————0.81.62.4———1.53.04.0—————————150300600VdcVdcVdcVdcVdcmAdcmAdcµAdchttp://onsemi.com427

MC14598BSWITCHING CHARACTERISTICS (5.) (T A = 25 C, C L = 130 pF + 1 TTL Load)V DDAll TypesVdc Min Typ (6.) Max UnitÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCharacteristicOutput Rise and Fall Timet TLH , t THL = (0.5 ns/pF) C L + 35 nst TLH , t THL = (0.2 ns/pF) C L + 25 nst TLH , t THL = (0.16 ns/pF) C L + 20 nsPropagation Delay TimeEnable to OutputSymbolt TLH ,t THL 5.01015t PLH ,t PHL 5.01015Strobe to Output 5.01015Reset to Output 5.01015Pulse WidthEnablet WH ,t WL 5.01015Strobe 5.01015Increment 5.01015Reset 5.01015Setup TimeDatat su5.01015Address 5.01015Hold TimeDatat h5.01015Address 5.01015Reset Removal Time t rem 5.010155. The formulas given are for the typical characteristics only at 25 C.6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.————————————3202401602001008020010080300160100100503520010070100503510050352020201005040160125100200100801759070160120801005040100504015080505025201005035502520502520– 25– 15– 1020010080320250200400200160350180140———————————————————————————nsnsnsnsnsnshttp://onsemi.com428

MC14598BMC14598B FUNCTION DIAGRAMRESET 2V DDDATA 3STROBE 6TO OTHERLATCHES1 D0ENABLE 4A0 7A1 8A2 10(M.S.B)TO OTHERLATCHESADDRESSDECODERZEROSELECTEACH LATCHADDITIONAL 7 LATCHESV SS17 D116 D215 D314 D41312D5D611 D7MC14598B TIMING DIAGRAM50%90%10%D7 1t PLH50%t PHLt TLHt THL t PLH90%10%RESETA0, A1, A2t W50%20 ns90%10%t sut hDATASTROBEENABLE*t sut h90%10% 50% 90%10%20 ns20 ns t Wt W*1.4 V with V DD = 5.0 VNOTES:1. High–impedance output state (another device controls bus).2. Output Load as for MC14597B.http://onsemi.com429

MC14598BLATCH TRUTH TABLEAddress OtherStrobe Reset Latch Latches0 1 * *1 1 Data *X 0 0 0*= No change in state of latchX = Don’t careTRUTH TABLE FOR MC14597BAddressIncrement Enable Reset Counter FullX 1 Count Up —X 1 No Change —X 1 0 Reset to Zero Set to OneX 0 1 No Change Set to OneIf atTo Zero onX 1 1 ADDRESS 7 Falling Edgeof STROBEX = Don’t careTEST LOADALL OUTPUTS+5.0 VR L = 2.5 kD n130 pF11.7 kCircuit diagrams external to or containing Motorolaproducts are included as a means of illustration only.Complete information sufficient for construction purposesmay not be fully illustrated. Although the information hereinhas been carefully checked and is believed to be reliable.Motorola assumes no responsibility for inaccuracies.Information herein does not convey to the purchaser anylicense under the patent rights of Motorola or others.The information contained herein is for guidance only,with no warranty of any type, expressed or implied.Motorola reserves the right to make any changes to theinformation and the product(s) to which the informationapplies and to discontinue manufacture of the product(s) atany time.http://onsemi.com430

http://onsemi.com431CHAPTER 7CMOS Reliability

RELIABILITYParamount in the mind of every semiconductor user is thequestion of device performance versus time. After theapplicability of a particular device has been established, itseffectiveness depends on the length of troublefree service itcan offer. The reliability of a device is exactly that — anexpression of how well it will serve the customer. Thefollowing discussion will attempt to present an overview ofON Semiconductor’s reliability efforts.BASIC CONCEPTSIt is essential to begin with an explanation of the variousparameters of Reliability. These are probably summarizedbest in the Bathtub Curve (Figure 1). The reliabilityperformance of a device is characterized by three phases:infant mortality, useful life, and wearout. When a device isproduced, there is often a small distribution of failuremechanisms which will exhibit themselves under relativelymoderate stress levels and therefore appear early. Thisperiod of early failures, termed infant mortality is reducedsignificantly through proper manufacturing controls andscreening techniques. The most effective period is that inwhich only occasional random failure mechanisms appear.The useful life typically spans a long period of time with avery low failure rate. The final period is that in which thedevices literally wear out due to continuous phenomenawhich existed at the time of manufacture. Using strictlycontrolled design techniques and selectivity in applications,this period is shifted well beyond the lifetime required by theuser.usually expressed in percent failures per thousand hours.Other forms include FIT (Failures in Time = (%/10 3 hrs) x10 –4 = 10 –9 failures per hour) and MTTF (Mean Time ToFailure) or MTBF (Mean Time Between Failures), bothbeing equal to 1/λ and having units of hours.Since reliability evaluations usually involve only samplesof an entire population of devices, the concepts of theCentral Limit Theorem apply and λ is calculated using x 2distribution through the equation:x 2 (x, 2r + 2)λ 2nt100 – CLwhere x =100CL = Confidence Limit in percentr = Number of rejectsn = Number of devicest = Duration of testThe confidence limit is the degree of conservatism desiredin the calculation. The Central Limit Theorem states that thevalues of any sample of units out of a large population willproduce a normal distribution. A 50% confidence limit istermed the best estimate and is the mean of this distribution.A 90% confidence limit is a very conservative value andresults in a higher λ which represents the point at which 90%of the area of the distribution is to the left of that value(Figure 2). The term (2r + 2) is called the degrees of freedomand is an expression of the number of rejects in a formsuitable to x 2 tables.50% CLFAILURE RATEINFANT MORTALITY(SUCH AS EARLYBURN–IN FAILURES)FREQUENCY90% CLUSEFUL LIFEWEAROUTFAILURESλ, FAILURE RATEFigure 2.101001000 10,000 100,000TIME (HOURS)Figure 1.1,000,000Both the infant mortality and random failure rate regionscan be described through the same types of calculations.During this time the probability of having no failures to aspecific point in time can be expressed by the equation:P o = e –λtwhere λ is the failure rate and t is time. Since λ is changingrapidly during infant mortality, the expression does notbecome useful until the random period, where λ is relativelyconstant. In this equation λ is failures per unit of time. It isThe number of rejects is a critical factor since thedefinition of rejects often differs between manufacturers.While ON Semiconductor uses data sheet limits todetermine failures, sometimes rejects are counted only ifthey are catastrophic. Due to the increasing chance of a testnot being representative of the entire population, as samplesize and test time are decreased, the x 2 calculation producessurprisingly high values of λ for short test durations eventhough the true long term failure rate may be quite low. Forthis reason relatively large amounts of data must be gatheredto demonstrate the real long term failure rate.Since this would require years of testing on thousands ofdevices, methods of accelerated testing have beendeveloped.http://onsemi.com432

Years of semiconductor device testing has shown thattemperature will accelerate failures and that this behaviorfits the form of the Arrhenius equation:R (t) = R 0 (t)e – θ/kTwhere R(t) = Reaction rate as a function of time andtemperatureR 0 = A constantt = Timeθ = Activation energy in electron voltsk = Boltzman’s constantT = Temperature in degrees KelvinTo provide time–temperature equivalents this equation isapplied to failure rate calculations in the form:t = t 0 e θ/kTwhere t = timet 0 = A constantThe Arrhenius equation essentially states that reactionrate increases exponentially with temperature. Thisproduces a straight line when plotted in log–linear paperwith a slope expressed by Θ. Θ may be physicallyinterpreted as the energy threshold of a particular reaction orfailure mechanism. The activation energy exhibited bysemiconductors varies from about 0.3 eV. Although therelationships do not prohibit devices from having poorfailure rates and high activation energies, good performanceusually does not imply a high Θ. Studies by Bell TelephoneLaboratories have indicated that an overall Θ forsemiconductors is 1.0 eV. This value has been accepted bythe Rome Air Development Command fortime–temperature acceleration in powered burn–in. Datataken by ON Semiconductor on Integrated Circuits haveverified this number and it is therefore applied as ourstandard time–temperature regression for extrapolation ofhigh temperature failure rates to temperatures at which the1.2 1.6 2.0 2.4 2.8 3.2 3.61000 kdevices will be used (Figure 3). For Discrete products, 0.7eV is generally applied.To accomplish this, the time in device hours (t1) andtemperature (T1) of the test are plotted as point P1. A verticalline is drawn at the temperature of interest (T2) and a linewith a 1.0 eV slope is drawn through point P1.Its intersection with the vertical line defines point P2, anddetermines the number of equivalent device hours (t2). Thisnumber may then be used with the x 2 formula to determinethe failure rate at the temperature of interest. Assuming T1of 125 C at t1 of 10,000 hours, a t2 of 7.8 million hoursresults at a T2 of 50 C. If one reject results in the 10,000device hours of testing at 125 C, the failure rate at thattemperature will be 0.1%/1,000 hours using a 60%confidence level. One reject at the equivalent 7.8 milliondevice hours at 50 C will result in a 0.0008%/1,000 hourfailure rate, as illustrated in Figure 4.Three parameters determine the failure rate quoted by themanufacturer: the failure rate at the test temperature, theactivation energy employed, and the difference between thetest temperature and the temperature of the quoted λ. A termoften used in this manipulation is the “acceleration factor”which is simply the equivalent device hours at the lowertemperature divided by the actual test device hours.Every device will eventually fail, but with the presenttechniques in Semiconductor design and applications, thewearout phase is extended far beyond the lifetime required.During wearout, as in infant mortality, the failure rate ischanging rapidly and therefore loses its value. Theparameter used to describe performance in this area is“Median Life” and is the point at which 50% of the deviceshave failed. There are currently only few significant wearoutmechanisms: electromigration of circuit metallization,electrolytic corrosion in plastic devices and metal fatigue forPower devices.1.2 1.6 2.0 2.4 2.8 3.2 3.6100100 k100 k10TIME (HOURS)10 kt21.0 k10010t11.0P11.0 eVSLOPEP2λ , FAILURE RATE (%/1000 HOURS)1.0λ20.01λ10.00010.1T1 T2500 200 100 50 0TEMPERATURE (°C)Figure 3. Normalized Time–TemperatureRegressions for Various Activation Energy Values0.00001500 200 100 50 0TEMPERATURE (°C)Figure 4. Failure Ratehttp://onsemi.com433

For increased flexibility in working with a broad range ofdevice hours, the time–temperature regression lines havebeen normalized to 500 C and the time scale omitted,permitting the user to define the scale based on his ownrequirements.THERMAL MANAGEMENTCircuit performance and long–term circuit reliability areaffected by die temperature. Normally, both are improved bykeeping the IC junction temperatures low.Electrical power dissipated in any integrated circuit is asource of heat. This heat source increases the temperature ofthe die relative to some reference point, normally theambient temperature of 25 C in still air. The temperatureincrease, then, depends on the amount of power dissipatedin the circuit and on the net thermal resistance between theheat source and the reference point.The temperature at the junction is a function of thepackaging and mounting system’s ability to remove heatgenerated in the circuit — from the junction region to theambient environment. The basic formula for convertingpower dissipation to estimated junction temperature is:T J = T A + P D (θ JC + θ CA ) (1)or T J = T A + P D (θ JA ) (2)whereT J = maximum junction temperatureT A = maximum ambient temperatureP D = calculated maximum power dissipationincluding effects of external loads (seePower Dissipation in section III).θ JC = average thermal resistance, junction to caseθ CA = average thermal resistance, case to ambientθ JA = average thermal resistance, junction toambientThis ON Semiconductor recommended formula has beenapproved by RADC or DESC for calculating a “practical”maximum operating junction temperature forMIL–M–38510 (JAN) devices.Only two terms on the right side of equation (1) can bevaried by the user — the ambient temperature, and thedevice case–to–ambient thermal resistance, θ CA . (To someextent the device power dissipation can also be controlled,but under recommended use the V CC supply and loadingdictate a fixed power dissipation.) Both system air flow andthe package mounting technique affect the θ CA thermalresistance term. θ JC is essentially independent of air flowand external mounting method, but is sensitive to packagematerial, die bonding method, and die area.Thermal Resistance in Still AirPackage DescriptionÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎNo.BodyBodyBodyDieDie Areaθ JC ( C/Watt)Flag Area(Sq. Mils) Avg. Max.ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎLeadsÎÎÎÎStyle MaterialÎÎÎÎÎ ÎÎÎÎW x L BondsÎÎÎÎÎ ÎÎÎÎÎ(Sq. Mils)ÎÎÎÎ1416DILDILEpoxyEpoxy1/4″ x 3/4″1/4″ x 3/4″EpoxyEpoxyÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎNOTES:1. All plastic packages use copper lead frames.ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ409640966,40012,1002. Body style DIL is “Dual–In–Line.”3. Standard Mounting Method: Dual–In–Line Socket or P/C board with no contact between bottom of package and socket or P/C board.Figure 5. Thermal Resistance Values for Standard I/C Packages38346154For applications where the case is held at essentially afixed temperature by mounting on a large ortemperature–controlled heat sink, the estimated junctiontemperature is calculated by:T J = T C + P D (θ JC ) (3)where T C = maximum case temperature and the otherparameters are as previously defined.The maximum and average θ JC resistance values forstandard IC packages are given in Figure 5.AIR FLOWThe majority of users employ some form of air–flowcooling. As air passes over each device on a printed circuitboard, it absorbs heat from each package. This heat gradientfrom the first package to the last package is a function of theair flow rate and individual package dissipations. Figure 6provides gradient data at power levels of 200 mW, 250 mW,300 mW, and 400 mW with an air flow rate of 500 Ifpm.These figures show the proportionate increase in thejunction temperature of each dual in–line package as the airpasses over each device. For higher rates of air flow thechange in junction temperature from package to packagedown the airstream will be lower due to greater cooling.Power Dissipation(mW)Junction Temperature Gradient( C/Package)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ200 ÎÎÎÎÎÎÎÎÎÎ0.4ÎÎÎÎÎÎÎÎÎÎÎÎ250 ÎÎÎÎÎÎÎÎÎÎ0.5300 ÎÎÎÎÎÎÎÎÎÎ0.63ÎÎÎÎÎÎÎÎÎÎÎÎ400 ÎÎÎÎÎÎÎÎÎÎ0.88Devices mounted on 0.062″ PC board with Z axis spacing of 0.5″.Air flow is 500 Ifpm along the Z axis.Figure 6. Thermal Gradient of Junction Temperature(16–Pin Dual–in–Line Package)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎhttp://onsemi.com434

OPTIMIZING THE LONG TERM RELIABILITY OFPLASTIC PACKAGESTodays plastic integrated circuit packages are as reliableas ceramic packages under most environmental conditions.However when the ultimate in system reliability is required,thermal management must be considered as a prime systemdesign goal.Modern plastic package assembly technology utilizesgold wire bonded to aluminum bonding pads throughout theelectronics industry. When exposed to high temperatures forprotracted periods of time an intermetallic compound canform in the bond area resulting in high impedance contactsand degradation of device performance. Since the formationof intermetallic compounds is directly related to devicejunction temperature, it is incumbent on the designer todetermine that the device junction temperatures areconsistent with system reliability goals.Predicting Bond Failure Time:Based on the results of almost ten (10) years of +125 Coperating life testing, a special arrhenius equation has beendeveloped to show the relationship between junctiontemperature and reliability.11554.267Eq. (1) T = (6.376 x 10 9 )e 273.15 + TJWhere: T = Time in hours to 0.1% bond failureT = (1 failure per 1,000 bonds).T J = Device junction temperature, C.And:Eq. (2) T J = T A + P D θ JA = T A + ∆T JWhere: T J = Device junction temperature, C.T A = Ambient temperature, C.P D = Device power dissipation in watts.θ JA = Device thermal resistance, junction to air,C/Watt.∆T J = Increase in junction temperature due toon–chip power dissipation.Table 1 shows the relationship between junctiontemperature, and continuous operating time to 0.1%. bondfailure, (1 failure per 1,000 bonds).Table 1. Device Junction Temperature versus Timeto 0.1% Bond FailuresJunctionTemperature C80Time, Hours1,032,200Time, Years117.8ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ90419,30047.9ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ100ÎÎÎÎÎÎ20.4178,700ÎÎÎÎÎÎÎÎÎÎÎÎ110ÎÎÎÎÎÎ79,600 ÎÎÎÎÎÎ9.4ÎÎÎÎÎÎÎÎÎÎÎÎ120 ÎÎÎÎÎÎ 4.237,000 ÎÎÎÎÎÎÎÎÎÎÎÎ130 ÎÎÎÎÎÎ17,800 ÎÎÎÎÎÎ2.0ÎÎÎÎÎÎ140 ÎÎÎÎÎÎ8,900 1.0Table 1 is graphically illustrated in Figure 7 which showsthat the reliability for plastic and ceramic devices are thesame until elevated junction temperatures inducesintermetallic failures in plastic devices. Early and mid–lifefailure rates of plastic devices are not effected by thisintermetallic mechanism.NORMALIZED FAILURE RATE11FAILURE RATE OF PLASTIC = CERAMICUNTIL INTERMETALLIC FAILURES OCCURTJ = 130 ° CT J = 120 ° CTJ = 110 ° C10T J = 100 ° CTIME, YEARS100Figure 7. Failure Rate versus TimeJunction Temperature1000ProcedureAfter the desired system failure rate has been establishedfor failure mechanisms other than intermetallics, eachdevice in the system should be evaluated for maximumjunction temperature. Knowing the maximum junctiontemperature, refer to Table 1 or Equation 1 to determine thecontinuous operating time required to 0.1% bond failuresdue to intermetallic formation. At this time, systemreliability departs from the desired value as indicated inFigure 7.Air flow is one method of thermal management whichshould be considered for system longevity. Other commonlyused methods include heat sinks for higher powered devices,refrigerated air flow and lower density board stuffing. Sinceθ CA is entirely dependent on the application, it is theresponsibility of the designer to determine its value. This canbe achieved by various techniques including simulation,modeling, actual measurement, etc.The material presented here emphasizes the need toconsider thermal management as an integral part of systemdesign and also the tools to determine if the managementmethods being considered are adequate to produce thedesired system reliability.TJ = 90 ° CTJ = 80 ° CÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎhttp://onsemi.com435

TJ , JUNCTION TEMPERATURE ( ° C)150°C125°C100°C75°C99°C81°C50°C25°CT J SOICT J PDIP139°C121°C65°CT A , AMBIENT TEMPERATURE137°C134°CP DPDIP & SOIC– 7 mW/°C500400300200100125°CPD, MAXIMUM POWER DISSIPATION PER PACKAGE (mW)T J , JUNCTION TEMPERATURE ( ° C)150°C125°C100°C75°CT J SOIC89°C58°C50°C25°CT J PDIP129°C65°CT A , AMBIENT TEMPERATURE135°C130°CP DPDIP & SOIC98°C – 7 mW/°C500400300200100125°CPD, MAXIMUM POWER DISSIPATION PER PACKAGE (mW)Figure 8. Junction Temperature for Worst CaseCMOS Logic DeviceThis graph illustrates junction temperature for the worst case CMOSLogic device (MC14007UB) — smallest die area operating atmaximum power dissipation limit in still air. The solid line indicatesthe junction temperature, T J , in a Dual–In–Line (PDIP) package andin a Small Outline IC (SOIC) package versus ambient temperature,T A . The dotted line indicates maximum allowable power dissipationderated over the ambient temperature range, 25 C to 125 C.Figure 9. Junction Temperature for TypicalCMOS Logic DeviceThis graph illustrates junction temperature for a CMOS Logic device(MC14053B) — average die area operating at maximum powerdissipation limit in still air. The solid line indicates the junctiontemperature, T J , in a Dual–In–Line (PDIP) package and in a SmallOutline IC (SOIC) package versus ambient temperature, T A . Thedotted line indicates maximum allowable power dissipation deratedover the ambient temperature range, 25 C to 125 C.http://onsemi.com436

http://onsemi.com437CHAPTER 8Equivalent Gate Count

The following is a list of equivalent gate counts for some of ON Semiconductor’s CMOS devices. In general for CMOS,the number of equivalent gates is equal to the total number of transistors on chip divided by four. This list includes only thosedevices with equivalent gate counts known at the time of this printing.EQUIVALENTEQUIVALENTDEVICE GATE COUNT DEVICE GATE COUNTMC14001B 8 MC14081B 10MC14001UB 4 MC14082B 8MC14007UB 1.5 MC14093B 18MC14008B 40 MC14094B 79MC14011B 8 MC14099B 70MC14011UB 4 MC14174B 43.5MC14012B 7 MC14175B 39.5MC14013B 16 MC14490 136.5MC14014B 74 MC14503B 17MC14015B 53 MC14504B 37.5MC14016B 8 MC14511B 54MC14017B 62.5 MC14512B 17.25MC14018B 38.25 MC14514B 59MC14020B 84 MC14515B 67MC14021B 74 MC14516B 61MC14023B 9 MC14517B 119MC14024B 59 MC14518B 43.5MC14025B 9 MC14520B 43.5MC14028B 26 MC14526B 86MC14029B 65.5 MC14528B 24MC14040B 73 MC14532B 38.5MC14042B 17.5 MC14536B 103MC14046B 35 MC14538B 38MC14049UB 3 MC14541B 93MC14049B 9 MC14543B 52MC14050B 6 MC14549B 122MC14051B 48.5 MC14551B 35MC14052B 38.5 MC14553B 147.5MC14053B 38 MC14555B 21MC14060B 73.5 MC14556B 25MC14066B 13 MC14557B 232.5MC14067B 65 MC14559B 122MC14069UB 3 MC14562B 206MC14071B 10 MC14569B 156MC14073B 10.5 MC14572UB 4MC14076B 32.5 MC14584B 18http://onsemi.com438

CHAPTER 9Packaging Information Including Surface Mountshttp://onsemi.com439

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The standard package availability for each device is indicated on the front page of the individual data sheets. Dimensionsfor the packages are given in this chapter. Surface mount packages may be special ordered by specifying the following suffixes:“D” (narrow SOIC), “DW” (wide SOIC), or “DT” (TSSOP). For example, to order a quad NOR gate, use MC14001BD. 14 81 7BPDIP–14P SUFFIXPLASTIC PACKAGECASE 646–06ISSUE MNOTES:1. DIMENSIONING AND TOLERANCING PER ANSIY14.5M, 1982.2. CONTROLLING DIMENSION: INCH.3. DIMENSION L TO CENTER OF LEADS WHENFORMED PARALLEL.4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.5. ROUNDED CORNERS OPTIONAL.–T–SEATINGPLANENAINCHES MILLIMETERSDIM MIN MAX MIN MAXA 0.715 0.770 18.16 18.80FLB 0.240 0.260 6.10 6.60C 0.145 0.185 3.69 4.69D 0.015 0.021 0.38 0.53CF 0.040 0.070 1.02 1.78G 0.100 BSC 2.54 BSCH 0.052 0.095 1.32 2.41J 0.008 0.015 0.20 0.38K 0.115 0.135 2.92 3.43K JL 0.290 0.310 7.37 7.87M ––– 10 ––– 10H G D 14 PLMN 0.015 0.039 0.38 1.010.13 (0.005) MSOIC–14D SUFFIXPLASTIC PACKAGECASE 751A–03ISSUE F–A–14 817–B–P 7 PL0.25 (0.010) M B MNOTES:1. DIMENSIONING AND TOLERANCING PER ANSIY14.5M, 1982.2. CONTROLLING DIMENSION: MILLIMETER.3. DIMENSIONS A AND B DO NOT INCLUDEMOLD PROTRUSION.4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)PER SIDE.5. DIMENSION D DOES NOT INCLUDE DAMBARPROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL BE 0.127 (0.005) TOTALIN EXCESS OF THE D DIMENSION ATMAXIMUM MATERIAL CONDITION.–T–SEATINGPLANEGD 14 PLKC0.25 (0.010) M T B S A SR X 45MJFMILLIMETERS INCHESDIM MIN MAX MIN MAXA 8.55 8.75 0.337 0.344B 3.80 4.00 0.150 0.157C 1.35 1.75 0.054 0.068D 0.35 0.49 0.014 0.019F 0.40 1.25 0.016 0.049G 1.27 BSC 0.050 BSCJ 0.19 0.25 0.008 0.009K 0.10 0.25 0.004 0.009M 0 7 0 7P 5.80 6.20 0.228 0.244R 0.25 0.50 0.010 0.019http://onsemi.com441

(continued)TSSOP–14DT SUFFIXPLASTIC PACKAGECASE 948G–01ISSUE O0.15 (0.006) T0.15 (0.006) TL0.10 (0.004)–T– SEATINGPLANEUUS2X L/2PIN 1IDENT.SDC141G14X K REFA–V–0.10 (0.004) M T U S V S87B–U–HNJ J1NFDETAIL EDETAIL EKK1SECTION N–NÇÇÇ ÉÉÉÉÉÉ ÇÇÇ0.25 (0.010)M–W–NOTES:1. DIMENSIONING AND TOLERANCING PER ANSIY14.5M, 1982.2. CONTROLLING DIMENSION: MILLIMETER.3. DIMENSION A DOES NOT INCLUDE MOLDFLASH, PROTRUSIONS OR GATE BURRS. MOLDFLASH OR GATE BURRS SHALL NOT EXCEED 0.15(0.006) PER SIDE.4. DIMENSION B DOES NOT INCLUDE INTERLEADFLASH OR PROTRUSION. INTERLEAD FLASH ORPROTRUSION SHALL NOT EXCEED0.25 (0.010) PER SIDE.5. DIMENSION K DOES NOT INCLUDE DAMBARPROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL BE 0.08 (0.003) TOTAL INEXCESS OF THE K DIMENSION AT MAXIMUMMATERIAL CONDITION.6. TERMINAL NUMBERS ARE SHOWN FORREFERENCE ONLY.7. DIMENSION A AND B ARE TO BE DETERMINEDAT DATUM PLANE –W–.MILLIMETERS INCHESDIM MIN MAX MIN MAXA 4.90 5.10 0.193 0.200B 4.30 4.50 0.169 0.177C ––– 1.20 ––– 0.047D 0.05 0.15 0.002 0.006F 0.50 0.75 0.020 0.030G 0.65 BSC 0.026 BSCH 0.50 0.60 0.020 0.024J 0.09 0.20 0.004 0.008J1 0.09 0.16 0.004 0.006K 0.19 0.30 0.007 0.012K1 0.19 0.25 0.007 0.010L 6.40 BSC 0.252 BSCM 0 8 0 8SOEIAJ–14F SUFFIXPLASTIC PACKAGENOTES:CASE 965–01ISSUE OL EQ 11. DIMENSIONING AND TOLERANCING PER ANSIY14.5M, 1982.2. CONTROLLING DIMENSION: MILLIMETER.3. DIMENSIONS D AND E DO NOT INCLUDEMOLD FLASH OR PROTRUSIONS AND AREMEASURED AT THE PARTING LINE. MOLD FLASHOR PROTRUSIONS SHALL NOT EXCEED 0.15(0.006) PER SIDE.4. TERMINAL NUMBERS ARE SHOWN FOR14 8REFERENCE ONLY.5. THE LEAD WIDTH DIMENSION (b) DOES NOTINCLUDE DAMBAR PROTRUSION. ALLOWABLEE H E MDAMBAR PROTRUSION SHALL BE 0.08 (0.003)TOTAL IN EXCESS OF THE LEAD WIDTHDIMENSION AT MAXIMUM MATERIAL CONDITION.DAMBAR CANNOT BE LOCATED ON THE LOWER17LRADIUS OR THE FOOT. MINIMUM SPACEBETWEEN PROTRUSIONS AND ADJACENT LEADTO BE 0.46 ( 0.018).ZDETAIL PMILLIMETERS INCHESDIM MIN MAX MIN MAXDA ––– 2.05 ––– 0.081b0.50 0.50 0.85 0.020 0.033A 1 L E 1.10 1.50 0.043 0.059A 1 0.05 0.20 0.002 0.008VIEW Pb 0.35 0.50 0.014 0.020eAc 0.18 0.27 0.007 0.011cD 9.90 10.50 0.390 0.413E 5.10 5.45 0.201 0.215e 1.27 BSC 0.050 BSCH E 7.40 8.20 0.291 0.3230.13 (0.005) M 0.10 (0.004)10 0 10M 0Q 1 0.70 0.90 0.028 0.035Z ––– 1.42 ––– 0.056http://onsemi.com442

16H–A–1 8GF9D 16 PLBSCK0.25 (0.010) M TSEATING–T– PLANEAPDIP–16P SUFFIXPLASTIC PACKAGECASE 648–08ISSUE RMJLMNOTES:1. DIMENSIONING AND TOLERANCING PER ANSIY14.5M, 1982.2. CONTROLLING DIMENSION: INCH.3. DIMENSION L TO CENTER OF LEADS WHENFORMED PARALLEL.4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.5. ROUNDED CORNERS OPTIONAL.INCHES MILLIMETERSDIM MIN MAX MIN MAXA 0.740 0.770 18.80 19.55B 0.250 0.270 6.35 6.85C 0.145 0.175 3.69 4.44D 0.015 0.021 0.39 0.53F 0.040 0.70 1.02 1.77G 0.100 BSC 2.54 BSCH 0.050 BSC 1.27 BSCJ 0.008 0.015 0.21 0.38K 0.110 0.130 2.80 3.30L 0.295 0.305 7.50 7.74M 0 10 0 10S 0.020 0.040 0.51 1.01–T–SEATINGPLANE16 91 8G–A–K–B–D 16 PL0.25 (0.010) M T B S A SP 8 PL0.25 (0.010) M B SCSOIC–16D SUFFIXPLASTIC PACKAGECASE 751B–05ISSUE JMR X 45JFNOTES:1. DIMENSIONING AND TOLERANCING PER ANSIY14.5M, 1982.2. CONTROLLING DIMENSION: MILLIMETER.3. DIMENSIONS A AND B DO NOT INCLUDEMOLD PROTRUSION.4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)PER SIDE.5. DIMENSION D DOES NOT INCLUDE DAMBARPROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL BE 0.127 (0.005) TOTALIN EXCESS OF THE D DIMENSION ATMAXIMUM MATERIAL CONDITION.MILLIMETERS INCHESDIM MIN MAX MIN MAXA 9.80 10.00 0.386 0.393B 3.80 4.00 0.150 0.157C 1.35 1.75 0.054 0.068D 0.35 0.49 0.014 0.019F 0.40 1.25 0.016 0.049G 1.27 BSC 0.050 BSCJ 0.19 0.25 0.008 0.009K 0.10 0.25 0.004 0.009M 0 7 0 7P 5.80 6.20 0.229 0.244R 0.25 0.50 0.010 0.019http://onsemi.com443

e16 91ZbD (continued)H E0.13 (0.005) M0.10 (0.004)8ESOEIAJ–16F SUFFIXNOTES:PLASTIC PACKAGECASE 966–01ISSUE OL EQ 1ML1. DIMENSIONING AND TOLERANCING PER ANSIY14.5M, 1982.2. CONTROLLING DIMENSION: MILLIMETER.3. DIMENSIONS D AND E DO NOT INCLUDEMOLD FLASH OR PROTRUSIONS AND AREMEASURED AT THE PARTING LINE. MOLD FLASHOR PROTRUSIONS SHALL NOT EXCEED 0.15(0.006) PER SIDE.4. TERMINAL NUMBERS ARE SHOWN FORREFERENCE ONLY.5. THE LEAD WIDTH DIMENSION (b) DOES NOTINCLUDE DAMBAR PROTRUSION. ALLOWABLEDAMBAR PROTRUSION SHALL BE 0.08 (0.003)TOTAL IN EXCESS OF THE LEAD WIDTHDIMENSION AT MAXIMUM MATERIAL CONDITION.DAMBAR CANNOT BE LOCATED ON THE LOWERRADIUS OR THE FOOT. MINIMUM SPACEBETWEEN PROTRUSIONS AND ADJACENT LEADTO BE 0.46 ( 0.018).DETAIL PMILLIMETERS INCHESA 1L 0.50 0.85 0.020 0.033DIM MIN MAX MIN MAXA ––– 2.05 ––– 0.081VIEW PA 1 0.05 0.20 0.002 0.008Ab 0.35 0.50 0.014 0.020cc 0.18 0.27 0.007 0.011D 9.90 10.50 0.390 0.413E 5.10 5.45 0.201 0.215e 1.27 BSC 0.050 BSCH E 7.40 8.20 0.291 0.323L E 1.10 1.50 0.043 0.059M 0 10 0 10Q 1 0.70 0.90 0.028 0.035Z ––– 0.78 ––– 0.0310.15 (0.006) T0.15 (0.006) TLUPIN 1IDENT.USS2X L/216X K REF16 91 8A–V–TSSOP–16DT SUFFIXPLASTIC PACKAGECASE 948F–01ISSUE O0.10 (0.004) M T U S V SB–U–NNJJ1FDETAIL EKK1SECTION N–NÇÇÇ ÉÉÉÉ ÇÇÇ0.25 (0.010)MNOTES:1. DIMENSIONING AND TOLERANCING PER ANSIY14.5M, 1982.2. CONTROLLING DIMENSION: MILLIMETER.3. DIMENSION A DOES NOT INCLUDE MOLDFLASH. PROTRUSIONS OR GATE BURRS. MOLDFLASH OR GATE BURRS SHALL NOT EXCEED 0.15(0.006) PER SIDE.4. DIMENSION B DOES NOT INCLUDE INTERLEADFLASH OR PROTRUSION. INTERLEAD FLASH ORPROTRUSION SHALL NOT EXCEED0.25 (0.010) PER SIDE.5. DIMENSION K DOES NOT INCLUDE DAMBARPROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL BE 0.08 (0.003) TOTAL INEXCESS OF THE K DIMENSION AT MAXIMUMMATERIAL CONDITION.6. TERMINAL NUMBERS ARE SHOWN FORREFERENCE ONLY.7. DIMENSION A AND B ARE TO BE DETERMINEDAT DATUM PLANE –W–.MILLIMETERS INCHESDIM MIN MAX MIN MAXA 4.90 5.10 0.193 0.200B 4.30 4.50 0.169 0.177C ––– 1.20 ––– 0.047D 0.05 0.15 0.002 0.006F 0.50 0.75 0.020 0.030G 0.65 BSC 0.026 BSCH 0.18 0.28 0.007 0.011J 0.09 0.20 0.004 0.008J1 0.09 0.16 0.004 0.006K 0.19 0.30 0.007 0.012K1 0.19 0.25 0.007 0.010L 6.40 BSC 0.252 BSCM 0 8 0 8C–W–0.10 (0.004)–T– SEATINGPLANEDGHDETAIL Ehttp://onsemi.com444

(continued)DASOIC–16DW SUFFIXPLASTIC PACKAGECASE 751G–03ISSUE B8X H0.25 M B M16 9114X16X B0.25 M T A S B Se8A1AEBTSEATINGPLANEh X 45CLNOTES:1. DIMENSIONS ARE IN MILLIMETERS.2. INTERPRET DIMENSIONS AND TOLERANCESPER ASME Y14.5M, 1994.3. DIMENSIONS D AND E DO NOT INLCUDE MOLDPROTRUSION.4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.5. DIMENSION B DOES NOT INCLUDE DAMBARPROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL BE 0.13 TOTAL IN EXCESSOF THE B DIMENSION AT MAXIMUM MATERIALCONDITION.MILLIMETERSDIM MIN MAXA 2.35 2.65A1 0.10 0.25B 0.35 0.49C 0.23 0.32D 10.15 10.45E 7.40 7.60e 1.27 BSCH 10.05 10.55h 0.25 0.75L 0.50 0.90 0 7 PDIP–18P SUFFIXPLASTIC PACKAGECASE 707–02ISSUE C181109BNOTES:1. POSITIONAL TOLERANCE OF LEADS (D),SHALL BE WITHIN 0.25 (0.010) AT MAXIMUMMATERIAL CONDITION, IN RELATION TOSEATING PLANE AND EACH OTHER.2. DIMENSION L TO CENTER OF LEADS WHENFORMED PARALLEL.3. DIMENSION B DOES NOT INCLUDE MOLDFLASH.HFGADNCSEATINGPLANEKLMJMILLIMETERS INCHESDIM MIN MAX MIN MAXA 22.22 23.24 0.875 0.915B 6.10 6.60 0.240 0.260C 3.56 4.57 0.140 0.180D 0.36 0.56 0.014 0.022F 1.27 1.78 0.050 0.070G 2.54 BSC 0.100 BSCH 1.02 1.52 0.040 0.060J 0.20 0.30 0.008 0.012K 2.92 3.43 0.115 0.135L 7.62 BSC 0.300 BSCM 0 15 0 15N 0.51 1.02 0.020 0.040http://onsemi.com445

24131 12BPDIP–24P SUFFIXPLASTIC PACKAGECASE 709–02ISSUE CNOTES:1. POSITIONAL TOLERANCE OF LEADS (D),SHALL BE WITHIN 0.25 (0.010) AT MAXIMUMMATERIAL CONDITION, IN RELATION TOSEATING PLANE AND EACH OTHER.2. DIMENSION L TO CENTER OF LEADS WHENFORMED PARALLEL.3. DIMENSION B DOES NOT INCLUDE MOLDFLASH.HGFADNKSEATINGPLANECMLJMILLIMETERS INCHESDIM MIN MAX MIN MAXA 31.37 32.13 1.235 1.265B 13.72 14.22 0.540 0.560C 3.94 5.08 0.155 0.200D 0.36 0.56 0.014 0.022F 1.02 1.52 0.040 0.060G 2.54 BSC 0.100 BSCH 1.65 2.03 0.065 0.080J 0.20 0.38 0.008 0.015K 2.92 3.43 0.115 0.135L 15.24 BSC 0.600 BSCM 0 15 0 15N 0.51 1.02 0.020 0.040SOIC–24DW SUFFIXPLASTIC PACKAGECASE 751E–04ISSUE E–A––T–SEATINGPLANE24113–B– 12X1224X D0.010 (0.25) M T A S B SC22X GKP0.010 (0.25) M B MJFMR X 45NOTES:1. DIMENSIONING AND TOLERANCING PER ANSIY14.5M, 1982.2. CONTROLLING DIMENSION: MILLIMETER.3. DIMENSIONS A AND B DO NOT INCLUDEMOLD PROTRUSION.4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)PER SIDE.5. DIMENSION D DOES NOT INCLUDE DAMBARPROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL BE 0.13 (0.005) TOTAL INEXCESS OF D DIMENSION AT MAXIMUMMATERIAL CONDITION.MILLIMETERS INCHESDIM MIN MAX MIN MAXA 15.25 15.54 0.601 0.612B 7.40 7.60 0.292 0.299C 2.35 2.65 0.093 0.104D 0.35 0.49 0.014 0.019F 0.41 0.90 0.016 0.035G 1.27 BSC 0.050 BSCJ 0.23 0.32 0.009 0.013K 0.13 0.29 0.005 0.011M 0 8 0 8P 10.05 10.55 0.395 0.415R 0.25 0.75 0.010 0.029http://onsemi.com446

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