Problem 8: Pattern Generator for Built-In Self-Test

¡¡¡¡¡Output patterns of PRPG in VCD format.V. Language/PlatformLanguage: CPlatform: Sun/SolarisVI. EvaluationFault coverage (most important) based on SynTest tools, CPU time, and memory requirement.The contestants may also use Verifault (from Cadence) or other fault simulator, if available, toobtain their fault coverage reports. The evaluation, however, will be based on the results reportedby the SynTest tools. (It should be noted that different fault simulators might report different resultson fault coverage.)VII. Technical SupportTools provided by SynTest:A Verilog parser that can parse a Verilog source code into an AST. A library withprogramming language interface (PI) is available to convert the AST into your datastructure. (In fact, you really don’t need the parser to work on this problem; all youneed is to identify related keywords. Hopefully, this remark can make you feel morecomfortable with this problem set.)A fault-simulation tool to read in the output of PRPG (in VCD format) and to report faultcoverage.Additional tools will be provided by SynTest, if necessary. Please email Guli atfor further information.¢ £ ¤ ¥ £ ¦ § ¨ © § VIII. QuestionsPlease report any question regarding this problem to cad@cis.nctu.edu.tw with the emailsubject “CAD Contest: Problem 8.” Your question(s) will be answered in two weeks, and theQ&A’s will be posted at the contest web site.References:[1] M. Abramovoci, M. Breuer, and A Friedman, Digital Systems Testing and Testable Designs,Chapters 10 and 11, Publisher: Computer Science Press.[2] P. Bardell, “Analysis of cellular automata used as pseudo random pattern generator,”Proceedings of 1990 International Test Conference (ITC'90), page 762-768.

Appendix:Hint:There are two ways to enhance your PRPG design. The basic idea is to do fault simulation on agiven core circuit with the patterns generated by PRPG and then modify the PRPG to get higherfault coverage.1. Using ASICGEN & Verilog simulatorSynTest will provide a fault simulation tool called ASICGEN. Here is the process:a. Use Verilog to simulate your PRPG and dump the simulation result in VCD format.b. Use VCDIN provided by SynTest to translate VCD format to SynTest test patternformat, .TP.c. Using front end tools provided by SynTest to translate a given core circuit into the SynTestdatabase.d. ASICGEN reads in the TP file and database, and reports the fault coverage.2. Using VerifaultYou can also use Verifault to do fault simulation on PRPG and the given full-scan circuit.Please note that the fault model in Verifault and SynTest are somewhat different, thus the faultcoverage are not the same all the time. You should only compare the results generated by onemethodology.ATTENTION: The evaluation will be based on the result reported by ASICGEN.Bonus:The advanced approach is to insert test points. You can design a tool to report the locations withvery poor controllability and observability. Insert test points as an extra scan chain eitherautomatically or manually. Do fault simulation to verify your progress.

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