Mentor Graphics Provides Design, Verification and Test Solutions for ...

Electronic Specifier DesignPhilip LingU.K.October 18, 2012http://www.electronicspecifier.com/Design/TSMCs-20nm-Design-Infrastructure-Mentor-Graphics-Provides-Design-Verification-and-Test-Solutions.aspMentor Graphics Provides Design, Verification and Test Solutions for TSMC's 20nmDesign InfrastructureNews Release from: Mentor Graphics Corporation16 October 2012Mentor Graphics today announced new capabilities to complement TSMC's 20nmmanufacturing processes. Enhancements to support both digital and analog/mixed signal20nm reference flows include new features in the PyxisT IC Station platform, the Eldo fastSPICE simulation products, the Olympus-SoCT place and route system, the CalibreRnmDRCT, Calibre RealTime, Calibre PERCT and Calibre xACT 3D solutions, and the TessentRsilicon test product suite.Each successive process node brings new challenges that require greater understanding between design andmanufacturing to resolve, said Wally Rhines, chairman and CEO of Mentor Graphics. Our close collaboration with TSMC hasenabled us to create solutions that codify this understanding so that mutual customers have confidence of a 'first timeright' design that is fully optimized for highest performance and yield.Mentor enables designers to take new 20nm requirements such as double patterning in stride while providing a range ofenhancements for low power, SmartFill, litho checking, and improved testing, said Suk Lee, TSMC senior director, DesignInfrastructure Marketing Division.Physical DesignOlympus-SoC has a comprehensive feature set to support the 20nm flow requirements including DRC/DP-aware routing,litho pattern matching, fixing and timing closure, coloring aware pin access, critical net routing, and DP-aware placement.The tool also provides database support for DP and pre-coloring, post-route dynamic power optimization, intelligent gatesizing and Vt assignment, voltage-dependent design spacing rules, in-chip overlay (ICOVL), dummy typical criticaldimension (DTCD) and boundary cell insertion.For custom and analog designs, the Pyxis IC Station solution provides a complete custom design flow from design capturethrough floor planning, polygon editing, physical layout, schematic-driven layout, chip assembly and interactive customrouting. Based on TSMC 20nm requirements, a new sensitivity analysis feature is implemented to work in conjunction withthe EldoR fast SPICE simulation products, and voltage-dependent design rule checking (DRC) works seamlessly withCalibre nmDRC, Calibre nmLVST and Calibre RealTime products.Physical VerificationThe Calibre nmDRC platform has a new engine to support DP anchoring and pre-coloring, DP design rule checking, voltagedependentchecking and patented real-time graphical error rings for coloring conflict resolution to reduce time consumingiterations when fixing DP violations.Mentor and TSMC collaborated on a circuit verification solution for 20nm that addresses potential reliability issues such aselectrostatic discharge(ESD) and latch-up. The Calibre PERC product checks for potential sources of electrical failure, including checks that TSMChas advocated but have not been addressed by other EDA tools. It provides a powerful environment for debuggingproblems with an integrated view of circuit connectivity, topology, physical layout and design rules that is not available inany other tool, and is fully scalable to handle full-chip signoff of the largest designs.Another innovation in the Mentor 20nm reference flow for TSMC is the Calibre SmartFill solution, which optimizes fillingtechniques to reduce the risk of differences between pre- and post-fill timing analysis, while ensuring that overall run timesand files sizes are controlled despite the significant increase in GDS data at 20nm. The flow also incorporates the CalibreLFDT product working with the TSMC Unified DFM Engine, which incorporates Calibre Pattern Matching technology toGlobalpress Connection, Inc.http://www.globalpresspr.com/news/client-coverage

Electronic Specifier DesignPhilip LingU.K.October 18, 2012http://www.electronicspecifier.com/Design/TSMCs-20nm-Design-Infrastructure-Mentor-Graphics-Provides-Design-Verification-and-Test-Solutions.aspaccelerate the litho hot spot detection at 20nm.The Calibre RealTime product, which provides immediate design rule checking and fixing guidance during custom layoutediting, has been extended to support full sign-off verification of 20nm rules, including DP checking and debugging aids,and voltage-dependent checks. Calibre RealTime brings signoff verification into the design creation process, providingdynamic feedback to layout engineers as they create and edit the layout. It also helps users create compact and optimizedlayout when designing with multiple supply voltages. Calibre RealTime is interoperable with the MentorR Pyxis IC Station,Mentor DESIGNrevT, and SpringSoft Laker layout tools.ExtractionThe Calibre xACT 3D tool provides reference-level (field solver) extraction accuracy with fast turnaround to address newcomplexities such as unavoidable misalignment of layout masks associated with double patterning (DPT). The Calibre xACT3D product is able to interoperate with the customer's layout design environment through TSMC-defined applicationprotocol interface.Silicon TestThe Tessent silicon test product suite for 20nm provides user-defined fault models and cell-aware test pattern generation,which allows test engineers to improve the coverage and quality of IC test. Cell-aware testing detects bridging and opendefects internal to cells, which are undetected by conventional fault models that only test the cell periphery andinterconnections. The Tessent TestKompressR product generates patterns to specifically target these additional defects,providing higher confidence in production testing with minimal impact to test time.Globalpress Connection, Inc.http://www.globalpresspr.com/news/client-coverage