Impact of Address Alignment• Warps should access aligned regions for maximum memory throughput• L1 can help for misaligned loads if several warps are accessing a contiguous region• ECC further significantly reduces misaligned store throughputExperiment:– Copy 16MB of floats– 256 threads/blockGreatest throughputdrop:– CA loads: 15%– CG loads: 32%© NVIDIA Corporation 2011
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