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24AA08/24LC08BFIGURE 1-1:BUS TIMING DATASCLSDAIN14765328 9 104SDAOUT1112FIGURE 1-2:BUS TIMING START/STOPD4SCL7610SDAStartStopDS21710E-page 4© 2005 Microchip Technology Inc.
24AA08/24LC08B2.0 FUNCTIONAL DESCRIPTIONThe 24XX08 supports a bidirectional, 2-wire bus anddata transmission protocol. A device that sends dataonto the bus is defined as a transmitter, while a devicereceiving data is defined as a receiver. The bus has tobe controlled by a master device which generates theSerial Clock (SCL), controls the bus access andgenerates the Start and Stop conditions, while the24XX08 works as slave. Both master and slave canoperate as transmitter or receiver, but the masterdevice determines which mode is activated.3.0 BUS CHARACTERISTICSThe following bus protocol has been defined:• Data transfer may be initiated only when the busis not busy.• During data transfer, the data line must remainstable whenever the clock line is high. Changes inthe data line while the clock line is high will beinterpreted as a Start or Stop condition.Accordingly, the following bus conditions have beendefined (Figure 3-1).3.1 Bus Not Busy (A)Both data and clock lines remain high.3.2 Start Data Transfer (B)A high-to-low transition of the SDA line while the clock(SCL) is high determines a Start condition. Allcommands must be preceded by a Start condition.3.3 Stop Data Transfer (C)A low-to-high transition of the SDA line while the clock(SCL) is high determines a Stop condition. Alloperations must be ended with a Stop condition.3.4 Data Valid (D)The state of the data line represents valid data when,after a Start condition, the data line is stable for theduration of the high period of the clock signal.The data on the line must be changed during the lowperiod of the clock signal. There is one clock pulse perbit of data.Each data transfer is initiated with a Start condition andterminated with a Stop condition. The number of thedata bytes transferred between the Start and Stopconditions is determined by the master device and istheoretically unlimited, although only the last sixteenwill be stored when doing a write operation. When anoverwrite does occur it will replace data in a first-in firstout(FIFO) fashion.3.5 AcknowledgeEach receiving device, when addressed, is obliged togenerate an acknowledge after the reception of eachbyte. The master device must generate an extra clockpulse which is associated with this Acknowledge bit.Note:The 24XX08 does not generate anyAcknowledge bits if an internal programmingcycle is in progress.The device that acknowledges, has to pull down theSDA line during the acknowledge clock pulse in such away that the SDA line is stable low during the highperiod of the acknowledge related clock pulse. Ofcourse, setup and hold times must be taken intoaccount. During reads, a master must signal an end ofdata to the slave by not generating an Acknowledge biton the last byte that has been clocked out of the slave.In this case, the slave (24XX08) will leave the data linehigh to enable the master to generate the Stopcondition.FIGURE 3-1:DATA TRANSFER SEQUENCE ON THE SERIAL BUSSCL(A) (B) (D) (D) (C) (A)SDAStartConditionAddress orAcknowledgeValidDataAllowedto ChangeStopCondition© 2005 Microchip Technology Inc. DS21710E-page 5
Page 1 and 2: 24AA08/24LC08B8K I 2 C Serial EEPR
Page 3: 24AA08/24LC08BTABLE 1-2:AC CHARACTE
Page 8: 24AA08/24LC08B5.0 ACKNOWLEDGE POLLI
Page 11 and 12: 24AA08/24LC08B8.0 PIN DESCRIPTIONST
Page 13 and 14: 24AA08/24LC08B1st Line MarkingSOT-2
Page 15 and 16: 24AA08/24LC08B8-Lead Plastic Small
Page 17 and 18: 24AA08/24LC08B8-Lead Plastic Micro
Page 19 and 20: 24AA08/24LC08B8-Lead Plastic Dual F
Page 21 and 22: 24AA08/24LC08BTHE MICROCHIP WEB SIT
Page 23 and 24: 24AA08/24LC08BPRODUCT IDENTIFICATIO
Page 25 and 26: Note the following details of the c

datasheet: pdf - AdvanIDe

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