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Gain Valuable Market Intelligence and Generate Leads with Detailed Demographics Market Research/Lead Generation Topics Include: �� Sponsor benefits/opportunities include: �� questions �� Sponsor Fee: $5,000 Reach Targeted Audiences with Chip Design Email Newsletters Chip Designer e-Newsletter (Bi-monthly) SoC digital and analog designers, system �� tion engineers benefit from the latest news, viewpoints and technical articles. Covers such �� The #1 Magazine for the Advanced IC Design Market Fall 2012 ARCHITECTURAL CHANGES AHEAD ANALOG HITS THE POWER WALL IC MANUFACTURING CHALLENGES LENGES ARM TIPS STRATEGY TO CRACK RACK K SERVER ER MARKET BLACK BELT POWER MANAGEMENT GEMENT www.chipdesignmag.comm Affiliate Sponsors: FPGA & CPLD Quarterly Update e-newsletter �� engineers. Marketing & Editorial Contacts �� with detailed demographics �� questions (at an additional fee of $2,500 per program) IP Designer – Integrator e-Newsletter (Monthly) Intellectual Property (IP) design and integration remains one of the hottest trends in the chip industry. Coverage includes trends in analogdigital, core-memory, design, verification, integration and qualification of IP in the SoC space. RF & Microwave Systems enewsletter (Quarterly) Trends, viewpoints, news and technical articles for design engineers and �� Chip Design covers all of the technical challenges and implementation options that engineers face in �� SoC design and the semiconductor manufacturing process as it affects the design of SoCs including FPGAs and other programmable devices. Make sure you participate in the following 2012 Interoperability Guides: �� Sponsor or participate in: ➡ RF & Microwave Systems Special Issue (May release) ➡ Focus On: Design for Yield (July release) Options Exclusive Roadblock-- Limited to one Sponsor 468x60 banner at top center position; side banner 125 x up to 728; up to three text ads; - $6,000/issue Platinum Sponsor 468x90 banner at top center position and first text ad - $2,500/issue Don’t be left out of these important 2013 Annual Engineers’ Guide Integrated Marketing Programs �� qualified engineers, embedded developers and chip designers make effective design and purchasing decisions all year long. Fall 2012 ARCHITECTURAL CHANGES AHEAD ANALOG HITS THE POWER WALL IC MANUFACTURING CHALLENGES ARM TIPS STRATEGY TO CRACK SERVER MARKET BLACK BELT POWER MANAGEMENT www.chipdesignmag.com Affiliate Sponsors: Advertising / Marketing Karen Popp Publisher, Sales Director 415.305.5557 kpopp@extensionmedia.com CONTACTS Advertising / Marketing Marcy Carnerie Sales Manager 510.919.4788 mcarnerie@extensionmedia.com Article / Abstract Submission John Blyler Editor-in-Chief 503.614.1082 jblyler@extensionmedia.com Custom Research and Lead Generation Program Gain valuable market intelligence and generate leads with detailed demographics. Sponsor provides up to 15 questions. We provide a �� contact information on survey respondents. 125 guaranteed �� Gold Sponsor Skyscraper top right banner position and second text ad - $2,000/issue Silver Sponsor Second from top 125x125 banner position and third text ad - $1,500/issue 1786 18th Street San Francisco, CA 94107 Tel: +1 415.255.0390 Fax: +1 415.255.9214 www.extensionmedia.com Options ➲ Full Page - $3,500 ➲ 2 Page Spread - $5,000 ➲ 1/2 Page - $2,500 ➲ Premium Positions - add 15% ➲ 1 Page Advertorial - $1,500 ➲ 2 Page Advertorial - $2,500 ➲ Full Page Product Showcase - $1,000 ➲ 1/2 Page Product Showcase - $750 ➲ Full Page Datasheet - $1,250 ➲ Additional Datasheet - $1,000 ➲ 2 Page Spread - $2,950 ➲ 1 Page 4/c - $2,000 ➲ Integrated Resource Catalog Marketing Sponsorships combine print, digital, website and email newsletter exposure. Prices range from $7,500 to $15,000 - ask for details. About Extension Media Extension Media is a publisher of business-to-business magazines, resource catalogs and web sites that address high-technology industry platforms and emerging technologies such as embedded systems, chip design, intellectual property, software and infrastructure, architectures and operating systems.
2013 Editorial Calendar Editorial Leadership John Blyler, Editorial Director �� Ed Sperling, Consulting Editor �� Electronic Business. Mark LaPedus, Senior Editor �� Cheryl Berglund Coupé, EECatalog.com Editor �� ® �� Jenn Burkhardt, Managing Editor �� Pallab Chatterjee, Regional Editor �� Dave Bursky, Senior Editor, �� Cheryl Ajluni, Contributing Editor �� Ann Steffora Mutschler, Contributing Editor �� Editorial Board �� 2013 Chip Design Editorial Calendar Issue Focus Report/ Insert Key Editorial Topics Winter Mentor Graphics Partner Interoperability Guide �� Interoperability Guide Winter Mentor Graphics Partner Interoperability Guide 2013 Special Issues �� Magazines, Special Issues, Webcasts, and Market Research & Lead Generation Programs Show Distribution Ad Close Materials Deadline �� Jan. 10 Jan. 14 �� Valley �� Feb. 25 Feb. 27 May 14 May 17 �� Issue Key Editorial Topics Show Distribution Ad Close �� Custom Content Marketing Solutions and Reprints from Chip Design EECatalog SPECIAL FEATURE Dodge the ‘Gotchas’ of FPGA-based Design Connect Tech experts ask the right questions to guide board-level designers through sequencing, power and configuration challenges. By Cheryl Coupé With the large-scale integration of today’s systems-on-chips (SoCs), FPGAs can help embedded designers reduce cost, weight, area and power; they also offer flexibility so that designers can respond to new standards, evolving customer needs and other requirement changes and still meet their time-to-market window. But the complex architectures of these devices can also present new challenges to board-level designers. EECatalog talked to Matt Ferraro and Patrick Dietrich, Connect Tech hardware design engineers and FPGA specialists, about today’s FPGA-based designs and how to bring these boards to production more efficiently and costeffectively, while addressing both current and future needs. EECatalog: In what kinds of circumstances do developers typically need help with FPGA-based designs? Ferraro: Connect Tech’s customers are generally those engineering teams that are knowledgeable, often engineers who have board-level design experience with general-purpose CPUs or microcontrollers, but only have experience using CPLDs as glue logic. They may lack experience using FPGA’s or have limited resources recognizing that taking on a given project internally will jeopardize time to market. Dietrich: Another typical situation is that experienced FPGA IP developers come to us once they’ve implemented their custom design in a development board,either from us or the FPGA vendor, but now want to bring their product to market. They may not have the experience or the resources to create the board-level design themselves. This is the ideal time to leverage our experienced FPGA developers, maintaining time to market as well as budgetary requirements. EECatalog: What has changed in programmable logic that makes today’s board designs so complex? Patrick Dietrich: The latest-generation FPGAs often have built-in logic (or hard IP) to implement features such as Ethernet MACs, DDR memory, PCI Express (PCIe) endpoints, etc., so FPGAs are not only for glue logic like they were 10 years ago. Signals and interconnects have changed, clock frequencies are increasing and rise times are decreasing. A designer can no longer use any pin as a general-purpose I/O pin when designing with higher-speed signals – things like clocking resources and special transceivers are now grouped to specific pins or banks of pins. Matt Ferraro: Today’s FPGAs are directly interfacing with all sorts of peripherals at high speeds, such as DDR3 memory, PCIe, SATA, HDMI/DVI, etc. Every peripheral has a different electrical interface standard, which has different voltage and timing requirements. To accommodate this, FPGAs have many special dual-purpose pins, such as voltage references,impedance references, I/O clock and strobes. Previous-generation FPGAs may have only had the global clock inputs, where every other pin is created equal – not unlike many of today’s CPLDs. The challenge now is to juggle all of these interface requirements in relation to the needs of the FPGA RTL design You can’t afford to let the board design dictate the direction of the FPGA design or vice versa. itself. You can’t afford to let the board design dictate the direction of the FPGA design or vice versa;both designs teams must work in concert to avoid rework in the design cycle. EECatalog: When you start work on a new FPGA-based design, what are the first issues you address? Dietrich: The first things we look at are the peripheral interfaces in the customer’s design that will be connected to the FPGA. Then we analyze each of these interconnects and determine their speed, interface, voltage level, I/O standards and how many pins are required. Another early issue we look at is estimating the actual FPGA design metrics. This leads to an indication of the logic density and speed grade needed from the FPGA, as well as clock rate and resource usage. Ferraro: Definitely, I/O interfaces are key. We ask a lot of questions to make sure we anticipate everything. What I/O standard are they using, and what’s the required voltage? How fast do they operate? What impedance is required? What’s the data rate? How many pins are required to support the 10 Engineers’ Guide to FPGA and CPLD Solutions 2012 �� International �� Materials Deadline �� June 17 June 20 Hire the Chip Design Editorial and Marketing teams to produce and deliver valuable, relevant and compelling content for your customers and prospects on a consistent basis. Content marketing positions you as a trusted expert, impacts buying decisions, generates leads and improves SEO results! All custom content may also be featured on www.chipdesignmag.com. Articles or Case Study (2 to 4 pages) �� Branded Email Newsletters �� Featured in Editorial Video (less than 10 minutes) �� White Papers (8 to 10 pages)�� Custom Blog �� Digital Magazines, print magazines, microsites, ebooks, social media add-ons quoted upon request Reprints: Turn Chip Design print or online content into a powerful marketing piece and testimonial (print and online options) - ��
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