Online. Gateway Sponsorships. Newsletters ... - Chip Design

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2013 Media Kit

Chip Design, www.chipdesignmag.com and Chip Design email newsletters reach over 

100,000 design engineers and engineering managers working on advanced SoC designs. 

Chip Design’s readers and www.chipdesignmag.com visitors are chip, programmable logic device and IP-related architects, designers, and testers. 

The readership also includes software protocol-application engineers and technical program managers. These architect-design-test engineers and 

managers are responsible for creating the latest generations of ASICs, structured ASIC, ASSPs , FPGAs, memory cores and SoC devices. 

Average Monthly Visitors 

on www.chipdesignmag.com 

Page Views: 237,598 

Visits: 42,053 

Average Time on Site: 48:31 

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Circulation Breakdown by Purchasing Responsibility 

94.8% 80.6% 70.1% 52.9% 57.2% 35.6% 

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Engineering Management 27.9% 

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Chip Design Magazine is distributed to over 

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Email Newsletters 

Readership 

➲ Chip Designer is distributed to 32,011 subscribers 

➲ IP Designer & Integrator is distributed to 28,214 subscribers 

➲ FPGA & PLD E-Product Alert is distributed to 44,018 subscribers 

➲ RF & Microwave Systems is distributed to 27,018 subscribers 

System architect, design and test engineers and engineering managers working on advanced SoC designs—Chip Design readers—account for a 

third of all design engineers. These key enablers influence the purchase of nearly 80% of the total EDA market—or about $4 billion. 

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The #1 Magazine for the Advanced IC Design Market 

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www.chipdesignmag.com 

Affiliate Sponsors: 

Advertising / Marketing 

Karen Popp 

Publisher, Sales Director 

415.305.5557 

kpopp@extensionmedia.com 

CONTACTS 


Marcy Carnerie 

Sales Manager 

510.919.4788 

mcarnerie@extensionmedia.com 

Article / Abstract Submission 

John Blyler 

Editor-in-Chief 

503.614.1082 

jblyler@extensionmedia.com 

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About Extension Media 

Extension Media is a publisher of business-to-business 

magazines, resource 

catalogs and web sites that address 

high-technology industry platforms 

and emerging technologies such as 

embedded systems, chip design, intellectual 

property, software and infrastructure, 

architectures and operating 

systems.

2013 Editorial Calendar 

Editorial Leadership 

John Blyler, Editorial Director 

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Ed Sperling, Consulting Editor 

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Electronic Business. 

Mark LaPedus, Senior Editor 

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Cheryl Berglund Coupé, EECatalog.com Editor 

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Jenn Burkhardt, Managing Editor 

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Pallab Chatterjee, Regional Editor 

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Dave Bursky, Senior Editor, 

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Cheryl Ajluni, Contributing Editor 

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Ann Steffora Mutschler, Contributing Editor 

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Editorial Board 

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2013 Chip Design Editorial Calendar 

Issue 

Focus Report/ 

Insert Key Editorial Topics 

Winter Mentor Graphics 

Partner 

Interoperability 

Guide 

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Guide 

Winter Mentor Graphics 

Partner 


Guide 

2013 Special Issues 

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Magazines, Special Issues, 

Webcasts, and Market Research & 

Lead Generation Programs 

Show 

Distribution 

Ad 

Close 

Materials 

Deadline 

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Valley 

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Feb. 25 Feb. 27 

May 14 May 17 

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Issue Key Editorial Topics Show Distribution Ad Close 

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Custom Content Marketing Solutions and Reprints from Chip Design 

EECatalog SPECIAL FEATURE 

Dodge the ‘Gotchas’ of 

FPGA-based Design 

Connect Tech experts ask the right questions to guide board-level designers 

through sequencing, power and configuration challenges. 

By Cheryl Coupé 

With the large-scale integration of today’s systems-on-chips 

(SoCs), FPGAs can help embedded designers reduce cost, 

weight, area and power; they also offer flexibility so that 

designers can respond to new standards, evolving customer 

needs and other requirement changes and still meet their 

time-to-market window. But the complex architectures of 

these devices can also present new challenges to board-level 

designers. EECatalog talked to Matt Ferraro and Patrick 

Dietrich, Connect Tech hardware design engineers and FPGA 

specialists, about today’s FPGA-based designs and how to 

bring these boards to production more efficiently and costeffectively, 

while addressing both current and future needs. 

EECatalog: In what kinds of circumstances do developers 

typically need help with FPGA-based designs? 

Ferraro: Connect Tech’s customers are generally those 

engineering teams that are knowledgeable, often engineers 

who have board-level 

design experience with 

general-purpose CPUs 

or microcontrollers, 

but only have experience 

using CPLDs as 

glue logic. They may 

lack experience using 

FPGA’s or have limited 

resources recognizing 

that taking on a given 

project internally will jeopardize time to market. 

Dietrich: Another typical situation is that experienced FPGA 

IP developers come to us once they’ve implemented their 

custom design in a development board,either from us or the 

FPGA vendor, but now want to bring their product to market. 

They may not have the experience or the resources to create 

the board-level design themselves. This is the ideal time to 

leverage our experienced FPGA developers, maintaining time 

to market as well as budgetary requirements. 

EECatalog: What has changed in programmable logic that 

makes today’s board designs so complex? 

Patrick Dietrich: The latest-generation FPGAs often have 

built-in logic (or hard IP) to implement features such as Ethernet 

MACs, DDR memory, PCI Express (PCIe) endpoints, etc., 

so FPGAs are not only for glue logic like they were 10 years 

ago. Signals and interconnects have changed, clock frequencies 

are increasing and rise times are decreasing. A designer 

can no longer use any pin as a general-purpose I/O pin when 

designing with higher-speed signals – things like clocking 

resources and special transceivers are now grouped to specific 

pins or banks of pins. 

Matt Ferraro: Today’s FPGAs are directly interfacing with all 

sorts of peripherals at high speeds, such as DDR3 memory, 

PCIe, SATA, HDMI/DVI, etc. Every peripheral has a different 

electrical interface standard, which has different voltage and 

timing requirements. To accommodate this, FPGAs have many 

special dual-purpose pins, such as voltage references,impedance 

references, I/O clock and strobes. Previous-generation FPGAs 

may have only had the global clock inputs, where every other 

pin is created equal – not unlike many of today’s CPLDs. The 

challenge now is to juggle all of these interface requirements 

in relation to the needs 

of the FPGA RTL design 

You can’t afford to let the board 

design dictate the direction of 

the FPGA design or vice versa. 

itself. You can’t afford 

to let the board design 

dictate the direction 

of the FPGA design or 

vice versa;both designs 

teams must work in 

concert to avoid rework 

in the design cycle. 

EECatalog: When you start work on a new FPGA-based design, 

what are the first issues you address? 

Dietrich: The first things we look at are the peripheral interfaces 

in the customer’s design that will be connected to the 

FPGA. Then we analyze each of these interconnects and determine 

their speed, interface, voltage level, I/O standards and 

how many pins are required. Another early issue we look at is 

estimating the actual FPGA design metrics. This leads to an 

indication of the logic density and speed grade needed from 

the FPGA, as well as clock rate and resource usage. 

Ferraro: Definitely, I/O interfaces are key. We ask a lot of 

questions to make sure we anticipate everything. What I/O 

standard are they using, and what’s the required voltage? How 

fast do they operate? What impedance is required? What’s 

the data rate? How many pins are required to support the 

10 Engineers’ Guide to FPGA and CPLD Solutions 2012 

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International 

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Materials 

Deadline 

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Hire the Chip Design Editorial and Marketing teams to produce and deliver valuable, relevant 

and compelling content for your customers and prospects on a consistent basis. Content 

marketing positions you as a trusted expert, impacts buying decisions, generates leads and 

improves SEO results! All custom content may also be featured on www.chipdesignmag.com. 

Articles or Case Study (2 to 4 

pages) 

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Branded Email Newsletters 

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Featured in Editorial Video (less than 10 minutes) 

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White Papers (8 to 10 pages)�� 

Custom Blog 

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Digital Magazines, print magazines, microsites, ebooks, 

social media add-ons quoted upon request 

Reprints: Turn Chip Design print or online content into 

a powerful marketing piece and testimonial (print and 

online options) 

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2013 Editorial Calendar 

Chip Design Email Newsletter Editorial Calendar 

Chip Designer newsletter 

Issue Feature Topic Ad Close Materials 

January �� Jan 11 Jan 14 

�� Jan 25 

February �� Feb 8 

��Multicore Issues Feb 20 Feb 22 

March �� Mar 8 Mar 11 

�� Mar 22 Mar 25 

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��Interconnect �� 

May �� May 8 May 10 

�� May 22 May 24 

June �� Jun 5 Jun 7 

�� Jun 19 Jun 21 

IP Designer & Integrator newsletter 


January �� Jan 18 

February �� Feb 15 

March �� Mar 12 Mar 14 

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May �� May 15 May 17 

June IP Metrics Jun 12 Jun 14 

FPGA IP Designer & CPLD & Quarterly Integrator Update newsletter Newsletter 

Issue Ad Close Materials 

�� Feb 1 Feb 4 

�� May 1 �� 

RF IP Designer & Microwave & Integrator Systemsnewsletter 


�� Feb 28 

�� May 10 �� 


Karen Popp 

Publisher, Sales Director 

415.305.5557 

kpopp@extensionmedia.com 

Advertising / Marketing Article / Abstract Submission 

Marcy Carnerie 

John Blyler 

Sales Manager 

Editor-in-Chief 

510.919.4788 

503.614.1082 

mcarnerie@extensionmedia.com 

jblyler@extensionmedia.com 

Newsletters 

and Resource Catalogs 


July �� Jul 10 Jul 12 

�� Jul 24 �� 

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July �� Jul 17 Jul 19 

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2013 Annual Engineers’ Guide Editorial Calendar 

Market Focus Pub Date Space Deadline Materials Deadline Targeted Reach Bonus Distribution 

Low Power System Design March March 5 March 8 

Multicore and 

VirtualizationTechnologies 

Engineers’ Guide to Sensors 

and MEMS Design 

May �� May 2 

May May 10 May 14 


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Chip Design Engineers’ Guide June May 15 May 21 �� 

Marketing & Editorial Contacts 

1786 18th Street 

San Francisco, CA 94107 

Tel: +1 415.255.0390 

Fax: +1 415.255.9214 

www.extensionmedia.com 

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FPGA and PLD Solutions �� 

About Extension Media 

Extension Media is a publisher of business-to-business 

magazines, resource 

catalogs and web sites that address 

high-technology industry platforms and 

emerging technologies such as embedded 

systems, chip design, intellectual 

property, software and infrastructure, 

architectures and operating systems.

Online. Gateway Sponsorships. Newsletters ... - Chip Design

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