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IBM System/7 Functional Characteristics - All about the IBM 1130 ...

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Significant Bits Meaning7* Data set error. The data set has become inactive while <strong>the</strong> ACCA is intransmit or receive mode. ISW bit 13 is also set if <strong>the</strong> interruptionrequest from <strong>the</strong> previous character is still pending. (ISW bit 7 is notused with <strong>IBM</strong> line adapters.)8 Binary data mode. The ACCA has recognized two consecutive DScharacters while in receive mode; subsequent data received will be inbinary mode. This status bit is set along with o<strong>the</strong>r ISW bits as longas <strong>the</strong> ACCA is in binary data mode. This bit does not generate aninterrupt.10 Receive mode. The ACCA is in receive mode. This bit does not generatean interrupt.12 Device busy. The ACCA is transmitting or receiving a character as aresult of a transmit or a read character command. The status of thisbit does not cause interruption requests nor does a read ISW commandreset <strong>the</strong> bit.13 Device end. This status bit is set on when all interruption requests arepresented to <strong>the</strong> processor with <strong>the</strong> possible exceptions of overrun(bit 2) and data set error (bit 7). ISW bit 13 will be set when an overrunor data set error occurs only if <strong>the</strong> pending interruption requestthat set bit 13 has not been accepted by <strong>the</strong> processor.Bit 13 is <strong>the</strong> only ISW bit set when <strong>the</strong> ACCA detects an end-oftransmission(EOT) character and <strong>the</strong> ACCA is in receive mode. Atthis time <strong>the</strong> ACCA enters receive status and subsequent characters(including EOT) are presented to <strong>the</strong> program as described previouslyunder condition 2. for ISW bit 4. The summary status indicator isalso set if bit 13 is <strong>the</strong> only ISW bit set.14* Data check. A negative response, a synchronization error, a longitudinalredundancy check (LRC), or a vertical redundancy check (VRC)error has occurred. An LRC error is indicated by <strong>the</strong> presence ofISW bit 3 (end of block) along with <strong>the</strong> data check indicator. VRCand synchronization errors are indicated by <strong>the</strong> presence of ISW bit 4.A negative response is indicated by <strong>the</strong> presence of ISW bit 6.- - •...mmumn 1111111111.• 1MM11011111111111131111111111111111111111o111 mulminimmuorrr,

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