IBM System/7 Functional Characteristics - All about the IBM 1130 ...

PROCESSOR MODULE DATA FLOWA general data flow for the processor module is shown in Figure 2-1. The 1130 attachment,if installed, can directly address System/7 storage.Data flow within the processor module is shown in Figure 2-2. All System/7commands are interpreted and executed by the processor. The first word of acommand enters the operation (Op) register for decoding.Storage is normally addressed from the processor by the storage address register (SAR).All data entering or leaving main storage must pass through the storage data register(SDR), with the exception of cycle steal.The arithmetic and logic unit (ALU) performs addition; subtraction; the logicaloperations AND, OR, and exclusive OR; and address arithmetic. (Address arithmetic isexplained in Chapter 4 under "Effective Address Generation.")The Y register shifts data to the left or to the right, or acts as a buffer for one operandof the ALU.Most registers in the processor are duplicated for each level to permit fast statusswitching. The registers associated with a particular level are used only when theprocessor is operating on that level.StorageProcessorAA1130SACHostAttachmentOr-4DirectControlChannelI/OmodulesmutuallyexclusiveACCA--....„Timers5028OperatorStationAdapterData lines--JControl lines 5 5Figure 2-1 (Part 1 of 2). General data flow for 5010 Processor Module: without cycle steal (Part 1)and with cycle steal (Part 2)2-2 GA34-0003