D-ATV DVB-S Transmitter Configuration File

faces are byte parallel interfaces consisting of eight data lines, a clock line, and several optional synchronisationlines. Table 2 shows the transport stream connector signal assignment.Signal Pins SignalV5.0 1 2 V5.0V5.0 3 4 V5.0SDA 5 6 XERROR or IRQ VCSCL 7 8 XRESETGND 9 10 GNDCK 11 12 SYVL 13 14 END6 15 16 D7D4 17 18 D5D2 19 20 D3D0 21 22 D1GND 23 24 GNDSDOUT 25 26 PLLTHRSCLK 27 28 SDINGND 29 30 GNDMCLKI 31 32 ASCLKRSTDA 33 34 BCLKTable 2: Transportstream-ConnectorTS1 and TS2 both have a FIFO in the signal path. The direction of the TS clock signal (CK) is thereforeconfigurable, that is, it can either be sourced by the D-ATV baseband board or the data source.TS3 and TS4, on the other hand, do not have a FIFO. The TS clock signal must therefore be driven by theD-ATV baseband board to avoid data loss. These ports are therefore mainly for use with the D-ATV MPEG2encoder.2.2 Board section2.2.1 Clock FrequencyThe clock parameter indicates the frequency of the crystal oscillator on the D-ATV baseband board. All timingsare derived from this crystal. The D-ATV board is normally shipped with a 60 MHz crystal, but for very lowbitrate applications, this crystal frequency may be reduced. The maximum is 62 MHz.Example:2.3 Modulator section2.3.1 FEC Rateclock = 60000000;This parameter specifies the inner Forward Error Correction code rate. It allows a trade-off between user bitrate and robustness of the modulation signal. Possible values are 1/2, 2/3, 3/4, 5/6 and 7/8.Example:2.3.2 Transmitter Frequencyfec = 5/6;The frequency parameter specifies the transmission frequency. It must lie either within the 23cm or the 13cmamateur radio band.Example:frequency = 1275M;5