Hardware accelerated virtualization in the ARM Cortex ... - Xen
Hardware accelerated virtualization in the ARM Cortex ... - Xen
Hardware accelerated virtualization in the ARM Cortex ... - Xen
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Virtual GIC<br />
� GIC now has separate sets of <strong>in</strong>ternal registers:<br />
� Physical registers and virtual registers<br />
� Non-virtualized system and hypervisor access <strong>the</strong> physical registers<br />
� Virtual mach<strong>in</strong>es access <strong>the</strong> virtual registers<br />
� Guest OS functionality does not change when access<strong>in</strong>g <strong>the</strong> vGIC<br />
� Virtual registers are remapped by hypervisor so that <strong>the</strong> Guest<br />
OS th<strong>in</strong>ks it is access<strong>in</strong>g <strong>the</strong> physical registers<br />
� GIC registers and functionality are identical<br />
� Hypervisor can set IRQs as virtual <strong>in</strong> <strong>the</strong> HCR<br />
� Interrupts are configured to generate a Hypervisor trap<br />
� Hypervisor can deliver an <strong>in</strong>terrupt to a CPU runn<strong>in</strong>g a virtual process<br />
us<strong>in</strong>g “register lists” of <strong>in</strong>terrupts<br />
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