The ARM Architecture
The ARM Architecture
The ARM Architecture
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1<br />
<strong>The</strong> <strong>ARM</strong> <strong>Architecture</strong><br />
Joe Bungo<br />
Applications Engineer<br />
<strong>ARM</strong> University Program
Agenda<br />
� Introduction to <strong>ARM</strong> Ltd<br />
<strong>ARM</strong> <strong>Architecture</strong>/Programmers Model<br />
2<br />
Data Path and Pipelines<br />
System Design<br />
Development Tools
<strong>ARM</strong> Ltd<br />
� Founded in November 1990<br />
� Spun out of Acorn Computers<br />
� Initial funding from Apple, Acorn and VLSI<br />
� Designs the <strong>ARM</strong> range of RISC processor cores<br />
� Licenses <strong>ARM</strong> core designs to semiconductor<br />
partners who fabricate and sell to their<br />
customers<br />
� <strong>ARM</strong> does not fabricate silicon itself<br />
� Also develop technologies to assist with the designin<br />
of the <strong>ARM</strong> architecture<br />
� Software tools, boards, debug hardware<br />
� Application software<br />
� Bus architectures<br />
� Peripherals, etc<br />
3
<strong>ARM</strong>’s Activities<br />
Processors<br />
System Level IP:<br />
Data Engines<br />
Fabric<br />
3D Graphics<br />
Physical IP<br />
4<br />
SoC<br />
memory<br />
Connected Community<br />
Development Tools<br />
Software IP
<strong>ARM</strong> Connected Community – 700+<br />
5<br />
5
Huge Range of Applications<br />
Tele-parking<br />
6<br />
Intelligent toys<br />
Utility<br />
Meters<br />
IR Fire<br />
Detector<br />
Exercise<br />
Machines<br />
Energy Efficient Appliances<br />
Equipment Adopting 32-bit <strong>ARM</strong><br />
Microcontrollers<br />
Intelligent<br />
Vending
World’s Smallest <strong>ARM</strong> Computer?<br />
7<br />
Cortex-M0; 65¢<br />
University of Michigan<br />
Wireless Sensor Network<br />
Sensors, timers<br />
Cortex-M0 +16KB RAM 65nm<br />
UWB Radio antenna<br />
10 kB Storage memory<br />
~3fW/bit<br />
12µAh Li-ion Battery<br />
A B C<br />
Battery Solar Cells<br />
Processor, SRAM and PMU<br />
Wirelessly networked into large scale<br />
sensor arrays
World’s Largest <strong>ARM</strong> Computer?<br />
8<br />
4200 <strong>ARM</strong> powered<br />
Neutrino Detectors<br />
70 bore holes 2.5km deep<br />
60 detectors per string<br />
starting 1.5km down<br />
1km 3 of active telescope<br />
Work supported by the National Science Foundation and University of Wisconsin-Madison
From 1mm 3 to 1km 3<br />
9<br />
1mm 3 1km 3<br />
10¢ $1000<br />
Mobile Home Mobile Computing Server<br />
Embedded Consumer Enterprise PC<br />
HPC
Agenda<br />
Introduction to <strong>ARM</strong> Ltd<br />
� <strong>ARM</strong> <strong>Architecture</strong>/Programmers Model<br />
Data Path and Pipelines<br />
11<br />
System Design<br />
Development Tools
<strong>ARM</strong> Classic Processor Portfolio<br />
12<br />
<strong>ARM</strong>v4<br />
<strong>ARM</strong>7TDMI(S) <br />
<strong>ARM</strong>v5<br />
<strong>ARM</strong>7EJ-S <br />
<strong>ARM</strong>922T <br />
<strong>ARM</strong>v6<br />
<strong>ARM</strong>1136J(F)-S <br />
<strong>ARM</strong>926EJ-S <br />
<strong>ARM</strong>1176JZ(F)-S <br />
SC100 <br />
<strong>ARM</strong>946E-S <br />
x1-4<br />
<strong>ARM</strong>11 MPCore <br />
<strong>ARM</strong>1156T2(F)-S <br />
<strong>ARM</strong>968E-S
<strong>ARM</strong> Cortex Processors (v7)<br />
� <strong>ARM</strong> Cortex-A family (v7-A):<br />
� Applications processors for full OS<br />
and 3 rd party applications<br />
� <strong>ARM</strong> Cortex-R family (v7-R):<br />
� Embedded processors for real-time<br />
signal processing, control applications<br />
� <strong>ARM</strong> Cortex-M family (v7-M):<br />
� Microcontroller-oriented processors<br />
for MCU and SoC applications<br />
13<br />
Cortex-A8<br />
Cortex-R4<br />
Cortex -M3<br />
x1-4<br />
...2.5GHz<br />
x1-4<br />
Cortex-A9<br />
Cortex-M1<br />
Cortex-A15<br />
x1-4<br />
Cortex-A5<br />
1-2<br />
R Heron<br />
Cortex-M4<br />
SC300 <br />
Cortex-M0<br />
12k gates...
Relative Performance*<br />
Max Frequency (Mhz)<br />
14<br />
2500<br />
2000<br />
1500<br />
1000<br />
500<br />
0<br />
Cortex-<br />
M0<br />
Cortex-<br />
M3<br />
<strong>ARM</strong>7 <strong>ARM</strong>926 <strong>ARM</strong>1026 <strong>ARM</strong>1136 <strong>ARM</strong>1176 Cortex-A8 Cortex-A9<br />
Dual-core<br />
Max Freq (MHz) 50 150 184 470 540 610 750 1100 2000<br />
Min Power (mW/MHz) 0.012 0.06 0.35 0.235 0.36 0.335 0.568 0.43 0.5<br />
*Represents attainable speeds in 130, 90, 65, or 45nm processes
Cortex family<br />
Cortex-A8<br />
� <strong>Architecture</strong> v7A<br />
� MMU<br />
� AXI<br />
� VFP & NEON support<br />
15<br />
Cortex-R4<br />
� <strong>Architecture</strong> v7R<br />
� MPU (optional)<br />
� AXI<br />
� Dual Issue<br />
Cortex-M3<br />
� <strong>Architecture</strong> v7M<br />
� MPU (optional)<br />
� AHB Lite & APB
Data Sizes and Instruction Sets<br />
� <strong>The</strong> <strong>ARM</strong> is a 32-bit architecture.<br />
� When used in relation to the <strong>ARM</strong>:<br />
� Byte means 8 bits<br />
� Halfword means 16 bits (two bytes)<br />
� Word means 32 bits (four bytes)<br />
� Most <strong>ARM</strong>’s implement two instruction sets<br />
� 32-bit <strong>ARM</strong> Instruction Set<br />
� 16-bit Thumb Instruction Set<br />
� Jazelle cores can also execute Java bytecode<br />
16
<strong>ARM</strong> and Thumb Performance<br />
Dhrystone 2.1/sec<br />
@ 20MHz<br />
17<br />
30000<br />
25000<br />
20000<br />
15000<br />
10000<br />
5000<br />
0<br />
32-bit 16-bit 16-bit with<br />
32-bit stack<br />
Memory width (zero wait state)<br />
<strong>ARM</strong><br />
Thumb
<strong>The</strong> Thumb-2 instruction set<br />
� Variable-length instructions<br />
� <strong>ARM</strong> instructions are a fixed length of 32 bits<br />
� Thumb instructions are a fixed length of 16<br />
bits<br />
� Thumb-2 instructions can be either 16-bit or<br />
32-bit<br />
� Thumb-2 gives approximately 26%<br />
improvement in code density over <strong>ARM</strong><br />
� Thumb-2 gives approximately 25%<br />
improvement in performance over<br />
Thumb<br />
18
Cortex-M3 Programmer’s Model<br />
19<br />
� Fully programmable in C<br />
� Stack-based exception model<br />
� Only two processor modes<br />
� Thread Mode for User tasks<br />
� Handler Mode for OS tasks and exceptions<br />
� Vector table contains addresses<br />
Main<br />
r0<br />
r1<br />
r2<br />
r3<br />
r4<br />
r5<br />
r6<br />
r7<br />
r8<br />
r9<br />
r10<br />
r11<br />
r12<br />
sp<br />
lr<br />
r15 (pc)<br />
xPSR<br />
sp<br />
Process
Cortex-M3 Processor Privilege<br />
20<br />
Supervisor<br />
Handler Mode<br />
User<br />
Thread Mode<br />
Privileged<br />
OS<br />
Non-Privileged<br />
Application code<br />
Memory<br />
Instructions & Data<br />
<strong>ARM</strong> Cortex-M3<br />
System Call (SVCall)<br />
Undefined Instruction<br />
Aborts<br />
Interrupts<br />
Reset
Cortex-M3 Interrupt Handling<br />
� One Non-Maskable Interrupt (INTNMI) supported<br />
� 1-240 prioritizable interrupts supported<br />
� Interrupts can be masked<br />
� Implementation option selects number of interrupts supported<br />
� Nested Vectored Interrupt Controller (NVIC) is tightly coupled with processor core<br />
� Interrupt inputs are active HIGH<br />
21<br />
INTNMI<br />
1-240 Interrupts<br />
INTISR[239:0] …<br />
NVIC<br />
Cortex-M3<br />
Cortex-M3<br />
Processor Core
Cortex-M3 Exception Handling<br />
22<br />
� Reset : power-on or system reset<br />
� NMI : cannot be stopped or preempted by any exception other than reset<br />
� Faults<br />
� Hard Fault : default Fault or any fault unable to activate<br />
� Memory Manage : MPU violations<br />
� Bus Fault : prefetch and memory access violations<br />
� Usage Fault : undef instructions, divide by zero, etc.<br />
� SVCall : privileged OS requests<br />
� Debug Monitor : debug monitor program<br />
� PendSV : pending SVCalls<br />
� SysTick Interrupt : internal sys timer, i.e., used by RTOS to periodically<br />
check resources or peripherals<br />
� External Interrupt : i.e., external peripherals
Cortex-M3 Program Status Register<br />
� One Status Register consisting of<br />
� APSR - Application Program Status Register – ALU flags<br />
� IPSR - Interrupt Program Status Register – Interrupt/Exception No.<br />
� EPSR - Execution Program Status Register<br />
� IT field – If/<strong>The</strong>n block information<br />
� ICI field – Interruptible-Continuable Instruction information<br />
� xPSR<br />
� Composite of the 3 PSRs<br />
� Stored on the stack on exception entry<br />
23<br />
31<br />
N Z C V Q<br />
28 27 26 25 24 23 16 15 10 7<br />
0<br />
IT<br />
T<br />
IT/ICI<br />
ISR Number
Conditional Execution<br />
� If – <strong>The</strong>n (IT) instruction added (16 bit)<br />
� Up to 3 additional “then” or “else” conditions maybe specified (T or E)<br />
� Makes up to 4 following instructions conditional<br />
24<br />
ITTET EQ<br />
Inst 1<br />
Inst 2<br />
Inst 3<br />
Inst 4<br />
MOVEQ<br />
ADDEQ<br />
SUBNE<br />
ORREQ<br />
� Any normal <strong>ARM</strong> condition code can be used<br />
� 16-bit instructions in block do not affect condition code flags<br />
� Apart from comparison instruction<br />
� 32 bit instructions may affect flags (normal rules apply)<br />
� Current “if-then status” stored in CPSR<br />
� Conditional block maybe safely interrupted and returned to<br />
� Must NOT branch into or out of ‘if-then’ block
Classes of Instructions (v4T)<br />
25<br />
Load/Store<br />
Miscellaneous<br />
Data Operations<br />
Change of Flow<br />
MOV PC, Rm<br />
Bcc<br />
BL<br />
BLX
Branch instructions<br />
� Branch : B{} label<br />
� Branch with Link : BL{} subroutine_label<br />
� <strong>The</strong> processor core shifts the offset field left by 2 positions, sign-extends it<br />
and adds it to the PC<br />
� ± 32 Mbyte range<br />
� How to perform longer branches?<br />
26<br />
31 28 27 25 24 23<br />
0<br />
Cond 1 0 1 L Offset<br />
Link bit 0 = Branch<br />
1 = Branch with link<br />
Condition field
Data processing Instructions<br />
� Consist of :<br />
� Arithmetic: ADD ADC SUB SBC RSB RSC<br />
� Logical: AND ORR EOR BIC<br />
� Comparisons: CMP CMN TST TEQ<br />
� Data movement: MOV MVN<br />
� <strong>The</strong>se instructions only work on registers, NOT memory.<br />
� Syntax:<br />
27<br />
{}{S} Rd, Rn, Operand2<br />
� Comparisons set flags only - they do not specify Rd<br />
� Data movement does not specify Rn<br />
� Second operand is sent to the ALU via barrel shifter.
Using a Barrel Shifter:<strong>The</strong> 2nd Operand<br />
28<br />
Operand<br />
1<br />
ALU<br />
Result<br />
Operand<br />
2<br />
Barrel<br />
Shifter<br />
Register, optionally with shift operation<br />
� Shift value can be either be:<br />
� 5 bit unsigned integer<br />
� Specified in bottom byte of<br />
another register.<br />
� Used for multiplication by constant<br />
Immediate value<br />
� 8 bit number, with a range of 0-255.<br />
� Rotated right through even<br />
number of positions<br />
� Allows increased range of 32-bit<br />
constants to be loaded directly into<br />
registers
Single register data transfer<br />
29<br />
LDR STR Word<br />
LDRB STRB Byte<br />
LDRH STRH Halfword<br />
LDRSB Signed byte load<br />
LDRSH Signed halfword load<br />
� Memory system must support all access sizes<br />
� Syntax:<br />
� LDR{}{} Rd, <br />
� STR{}{} Rd, <br />
e.g.LDREQB
Agenda<br />
30<br />
Introduction to <strong>ARM</strong> Ltd<br />
<strong>ARM</strong> <strong>Architecture</strong>/Programmers Model<br />
� Data Path and Pipelines<br />
System Design<br />
Development Tools
Cortex-M3 Datapath<br />
I_HADDR<br />
31<br />
I_HRDATA<br />
D_HADDR Address<br />
Register<br />
Address<br />
Incrementer<br />
Address<br />
Incrementer<br />
Address<br />
Register<br />
Instruction<br />
Decode<br />
INTADDR<br />
Register<br />
Bank<br />
B<br />
A<br />
Writeback<br />
Mul/Div<br />
Write Data<br />
Register<br />
Read Data<br />
Register<br />
Barrel<br />
Shifter<br />
ALU<br />
D_HWDATA<br />
D_HRDATA<br />
ALU
Cortex-M3 Pipeline<br />
32<br />
� Cortex-M3 has 3-stage fetch-decode-execute pipeline<br />
� Similar to <strong>ARM</strong>7<br />
� Cortex-M3 does more in each stage to increase overall<br />
performance<br />
1 st Stage - Fetch 2 nd Stage - Decode 3 rd Stage - Execute<br />
Fetch<br />
(Prefetch)<br />
Branch forwarding & speculation<br />
AGU<br />
Instruction<br />
Decode &<br />
Register Read<br />
Branch<br />
Execute stage branch (ALU branch & Load Store Branch)<br />
Address<br />
Phase & Write<br />
Back<br />
Data Phase<br />
Load/Store &<br />
Branch<br />
Multiply & Divide<br />
Shift ALU & Branch<br />
Write
<strong>ARM</strong>10 vs. <strong>ARM</strong>11 Pipelines<br />
<strong>ARM</strong>10<br />
<strong>ARM</strong>11<br />
33<br />
Branch<br />
Prediction<br />
Instruction<br />
Fetch<br />
Fetch<br />
1<br />
Fetch<br />
2<br />
<strong>ARM</strong> or<br />
Thumb Reg Read<br />
Shift + ALU<br />
Memory<br />
Access Reg<br />
Instruction<br />
Write<br />
Decode<br />
Multiply<br />
Multiply<br />
Add<br />
FETCH ISSUE DECODE EXECUTE MEMORY WRITE<br />
Decode Issue<br />
Shift ALU Saturate<br />
MAC<br />
1<br />
Address<br />
MAC<br />
2<br />
Data<br />
Cache<br />
1<br />
MAC<br />
3<br />
Data<br />
Cache<br />
2<br />
Write<br />
back
Full Cortex-A8 Pipeline Diagram<br />
34<br />
13-Stage Integer Pipeline 10-Stage NEON Pipeline<br />
Architectural register file<br />
NEON register file
Agenda<br />
35<br />
Introduction to <strong>ARM</strong> Ltd<br />
<strong>ARM</strong> <strong>Architecture</strong>/Programmers Model<br />
Data Path and Pipelines<br />
� System Design<br />
Development Tools
An Example AMBA System<br />
36<br />
High<br />
Bandwidth<br />
External<br />
Memory<br />
Interface<br />
High-bandwidth<br />
on-chip RAM<br />
High Performance<br />
<strong>ARM</strong> processor<br />
AHB<br />
High Performance<br />
Pipelined<br />
Burst Support<br />
Multiple Bus Masters<br />
DMA<br />
Bus Master<br />
APB<br />
Bridge<br />
APB<br />
UART<br />
Timer<br />
Keypad<br />
PIO<br />
Low Power<br />
Non-pipelined<br />
Simple Interface
AHB Structure<br />
37<br />
Master<br />
#1<br />
Master<br />
#2<br />
Master<br />
#3<br />
HADDR<br />
HWDATA<br />
HRDATA<br />
Arbiter<br />
Address/Control<br />
Write Data<br />
Read Data<br />
Decoder<br />
HRDATA<br />
HADDR<br />
HWDATA<br />
Slave<br />
#1<br />
Slave<br />
#2<br />
Slave<br />
#3<br />
Slave<br />
#4
Mali200 + GP2 SoC Integration<br />
38<br />
Clock<br />
Reset<br />
IRQs<br />
IDLEs<br />
APB<br />
AXI<br />
Mali 200<br />
AXI Fabric<br />
MMU<br />
Mali GP2<br />
� Shipped as synthesizable<br />
Verilog<br />
� Mali 200 + GP2 requires a<br />
single instant in the SoC,<br />
with a small number of<br />
connections to be made.<br />
� IDLES can be used for<br />
gating the Mali200 and GP2<br />
core clock
Typical GPU SoC Design<br />
39<br />
<strong>ARM</strong>1176JZF<br />
D I<br />
L230<br />
PL390<br />
GIC<br />
APB Peripheral Sub-System<br />
Sys<br />
Ctrl<br />
Int<br />
nRst<br />
APB<br />
PL301 High-performance matrix<br />
Mali 200 Mali GP2<br />
Local AXI Interconnect<br />
Mali<br />
MMU<br />
M<br />
S<br />
CLCD<br />
PL111<br />
M<br />
SDRAMC<br />
PL340<br />
� Designed and optimised for AMBA: provides easier integration with <strong>ARM</strong> cores and fabric IP<br />
� Unified Memory <strong>Architecture</strong><br />
DDR<br />
PHY
<strong>ARM</strong> PIPD Logic Product Families<br />
High Speed<br />
Low Power<br />
Low Area<br />
40<br />
High Density (SAGE-X )<br />
(SC9 / SC10 tapped tapped)<br />
180nm 130nm 90nm 65nm<br />
High Performance (Advantage-HS / SAGE-HS)<br />
(SC12)<br />
Ultra High Density (Metro )<br />
(SC7 / SC8)<br />
Power Management Kits<br />
High Density (Advantage )<br />
(SC9 / SC10)<br />
ECO Kits<br />
45nm 32nm 28nm<br />
Power Management Management Kits<br />
ECO Kits<br />
Process<br />
Geometry
Agenda<br />
41<br />
Introduction to <strong>ARM</strong> Ltd<br />
<strong>ARM</strong> <strong>Architecture</strong>/Programmers Model<br />
Data Path and Pipelines<br />
System Design<br />
� Development Tools
<strong>ARM</strong> Debug <strong>Architecture</strong><br />
42<br />
Debugger (+ optional<br />
trace tools)<br />
� EmbeddedICE Logic<br />
� Provides breakpoints and processor/system<br />
access<br />
� JTAG interface (ICE)<br />
� Converts debugger commands to JTAG<br />
signals<br />
� Embedded trace Macrocell (ETM)<br />
� Compresses real-time instruction and data<br />
access trace<br />
� Contains ICE features (trigger & filter logic)<br />
� Trace port analyzer (TPA)<br />
� Captures trace in a deep buffer<br />
Ethernet<br />
JTAG port<br />
TAP<br />
controller<br />
EmbeddedICE<br />
Logic<br />
<strong>ARM</strong><br />
core<br />
Trace Port<br />
ETM
Keil Development Tools for <strong>ARM</strong><br />
� Includes <strong>ARM</strong> macro assembler, compilers (<strong>ARM</strong> RealView C/C++<br />
Compiler, Keil C<strong>ARM</strong> Compiler, or GNU compiler), <strong>ARM</strong> linker, Keil uVision<br />
Debugger and Keil uVision IDE<br />
� Keil uVision Debugger accurately simulates on-chip peripherals (I 2 C, CAN,<br />
UART, SPI, Interrupts, I/O Ports, A/D and D/A converters, PWM, etc.)<br />
� Evaluation Limitations<br />
� 16K byte object code + 16K data limitation<br />
� Some linker restrictions such as base addresses for code/constants<br />
� GNU tools provided are not restricted in any way<br />
� http://www.keil.com/demo/<br />
43
Keil Development Tools for <strong>ARM</strong><br />
44
University Resources<br />
�http://www.arm.com/support/university/<br />
�University@arm.com<br />
46
TI Panda Board<br />
OMAP4430 Processor<br />
� 1 GHz Dual-core <strong>ARM</strong><br />
Cortex-A9 (NEON+VFP)<br />
� C64x+ DSP<br />
� PowerVR SGX 3D GPU<br />
� 1080p Video Support<br />
POP Memory<br />
� 1 GB LPDDR2 RAM<br />
USB Powered<br />
� < 4W max consumption<br />
(OMAP small % of that)<br />
� Many adapter options<br />
(Car, wall, battery, solar, ..)<br />
47
Project Ideas Using Panda<br />
� OS Projects<br />
� OS porting to <strong>ARM</strong>/Cortex (TI OMAP)<br />
� MythTV system<br />
� “Super-Panda” – stack of Pandas as compute engine and task<br />
distribution<br />
� Linux applications<br />
� NEON Optimization Projects<br />
� Codec optimization in ffmpeg (pick your favorite codec)<br />
� Voice and image recognition<br />
� Open-source Flash player optimizations (swfdec)<br />
48
49<br />
Fin
Nokia N95 Multimedia Computer<br />
50<br />
OMAP 2420<br />
Applications Processor<br />
<strong>ARM</strong>1136 processor-based<br />
SoC, developed using Magma ®<br />
Blast® family and winner of<br />
2005 INSIGHT Award for ‘Most<br />
Innovative SoC’<br />
Symbian OS v9.2<br />
Operating System supporting <strong>ARM</strong><br />
processor-based mobile devices,<br />
developed using <strong>ARM</strong>® RealView®<br />
Compilation Tools<br />
S60 3 rd Edition<br />
S60 Platform supporting <strong>ARM</strong><br />
processor-based mobile devices<br />
Mobiclip Video Codec<br />
Software video codec for <strong>ARM</strong><br />
processor-based mobile devices<br />
ST WLAN Solution<br />
Ultra-low power 802.11b/g WLAN<br />
chip with <strong>ARM</strong>9 processor-based<br />
MAC<br />
Connect. Collaborate. Create.
51<br />
Beagle Board
Targeting community development<br />
> 1000 participants<br />
and growing<br />
Open access to<br />
hardware<br />
documentation<br />
52<br />
Active &<br />
technical<br />
community<br />
Opportunity<br />
to tinker and<br />
learn<br />
$149<br />
Personally<br />
affordable<br />
Addressing<br />
open source<br />
community<br />
needs<br />
Wikis, blogs,<br />
promotion of<br />
community<br />
activity<br />
Freedom to<br />
innovate<br />
Instant access to<br />
>10 million lines<br />
of code<br />
Free<br />
software
Fast, low power, flexible expansion<br />
OMAP3530 Processor<br />
� 600MHz Cortex-A8<br />
53<br />
� NEON+VFPv3<br />
� 16KB/16KB L1$<br />
� 256KB L2$<br />
� 430MHz C64x+ DSP<br />
� 32K/32K L1$<br />
� 48K L1D<br />
� 32K L2<br />
� PowerVR SGX GPU<br />
� 64K on-chip RAM<br />
POP Memory<br />
� 128MB LPDDR RAM<br />
3”<br />
Peripheral I/O<br />
� DVI-D video out<br />
� SD/MMC+<br />
� S-Video out<br />
� USB 2.0 HS OTG<br />
� I 2 C, I 2 S, SPI,<br />
MMC/SD<br />
� JTAG<br />
� Stereo in/out<br />
� Alternate power<br />
� RS-232 serial<br />
� 256MB NAND flash USB Powered<br />
� 2W maximum consumption<br />
� OMAP is small % of that<br />
� Many adapter options<br />
� Car, wall, battery, solar, …
And more…<br />
54<br />
Other Features<br />
� 4 LEDs<br />
� USR0<br />
� USR1<br />
� PMU_STAT<br />
� PWR<br />
� 2 buttons<br />
� USER<br />
� RESET<br />
� 4 boot sources<br />
� SD/MMC<br />
� NAND flash<br />
� USB<br />
� Serial<br />
On-going collaboration at BeagleBoard.org<br />
� Live chat via IRC for 24/7 community support<br />
� Links to software projects to download<br />
3”<br />
Peripheral I/O<br />
� DVI-D video out<br />
� SD/MMC+<br />
� S-Video out<br />
� USB HS OTG<br />
� I 2 C, I 2 S, SPI,<br />
MMC/SD<br />
� JTAG<br />
� Stereo in/out<br />
� Alternate power<br />
� RS-232 serial
Project Ideas Using Beagle<br />
� OS Projects<br />
� OS porting to <strong>ARM</strong>/Cortex (TI OMAP)<br />
� MythTV system<br />
� “Super-Beagle” – stack of Beagles as compute engine and task<br />
distribution<br />
� Linux applications<br />
� NEON Optimization Projects<br />
� Codec optimization in ffmpeg (pick your favorite codec)<br />
� Voice and image recognition<br />
� Open-source Flash player optimizations (swfdec)<br />
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